1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/export.h> 8 #include <linux/clk-provider.h> 9 #include <linux/regmap.h> 10 #include <linux/delay.h> 11 12 #include "clk-alpha-pll.h" 13 #include "common.h" 14 15 #define PLL_MODE(p) ((p)->offset + 0x0) 16 # define PLL_OUTCTRL BIT(0) 17 # define PLL_BYPASSNL BIT(1) 18 # define PLL_RESET_N BIT(2) 19 # define PLL_OFFLINE_REQ BIT(7) 20 # define PLL_LOCK_COUNT_SHIFT 8 21 # define PLL_LOCK_COUNT_MASK 0x3f 22 # define PLL_BIAS_COUNT_SHIFT 14 23 # define PLL_BIAS_COUNT_MASK 0x3f 24 # define PLL_VOTE_FSM_ENA BIT(20) 25 # define PLL_FSM_ENA BIT(20) 26 # define PLL_VOTE_FSM_RESET BIT(21) 27 # define PLL_UPDATE BIT(22) 28 # define PLL_UPDATE_BYPASS BIT(23) 29 # define PLL_OFFLINE_ACK BIT(28) 30 # define ALPHA_PLL_ACK_LATCH BIT(29) 31 # define PLL_ACTIVE_FLAG BIT(30) 32 # define PLL_LOCK_DET BIT(31) 33 34 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 35 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 36 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 37 38 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 39 # define PLL_POST_DIV_SHIFT 8 40 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) 41 # define PLL_ALPHA_EN BIT(24) 42 # define PLL_ALPHA_MODE BIT(25) 43 # define PLL_VCO_SHIFT 20 44 # define PLL_VCO_MASK 0x3 45 46 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 47 48 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 49 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 50 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 51 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 52 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 53 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 54 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 55 56 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 57 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 58 [PLL_OFF_L_VAL] = 0x04, 59 [PLL_OFF_ALPHA_VAL] = 0x08, 60 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 61 [PLL_OFF_USER_CTL] = 0x10, 62 [PLL_OFF_USER_CTL_U] = 0x14, 63 [PLL_OFF_CONFIG_CTL] = 0x18, 64 [PLL_OFF_TEST_CTL] = 0x1c, 65 [PLL_OFF_TEST_CTL_U] = 0x20, 66 [PLL_OFF_STATUS] = 0x24, 67 }, 68 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 69 [PLL_OFF_L_VAL] = 0x04, 70 [PLL_OFF_ALPHA_VAL] = 0x08, 71 [PLL_OFF_USER_CTL] = 0x10, 72 [PLL_OFF_CONFIG_CTL] = 0x14, 73 [PLL_OFF_CONFIG_CTL_U] = 0x18, 74 [PLL_OFF_TEST_CTL] = 0x1c, 75 [PLL_OFF_TEST_CTL_U] = 0x20, 76 [PLL_OFF_STATUS] = 0x24, 77 }, 78 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 79 [PLL_OFF_L_VAL] = 0x04, 80 [PLL_OFF_ALPHA_VAL] = 0x08, 81 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 82 [PLL_OFF_USER_CTL] = 0x10, 83 [PLL_OFF_CONFIG_CTL] = 0x18, 84 [PLL_OFF_TEST_CTL] = 0x1c, 85 [PLL_OFF_STATUS] = 0x24, 86 }, 87 [CLK_ALPHA_PLL_TYPE_FABIA] = { 88 [PLL_OFF_L_VAL] = 0x04, 89 [PLL_OFF_USER_CTL] = 0x0c, 90 [PLL_OFF_USER_CTL_U] = 0x10, 91 [PLL_OFF_CONFIG_CTL] = 0x14, 92 [PLL_OFF_CONFIG_CTL_U] = 0x18, 93 [PLL_OFF_TEST_CTL] = 0x1c, 94 [PLL_OFF_TEST_CTL_U] = 0x20, 95 [PLL_OFF_STATUS] = 0x24, 96 [PLL_OFF_OPMODE] = 0x2c, 97 [PLL_OFF_FRAC] = 0x38, 98 }, 99 }; 100 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 101 102 /* 103 * Even though 40 bits are present, use only 32 for ease of calculation. 104 */ 105 #define ALPHA_REG_BITWIDTH 40 106 #define ALPHA_REG_16BIT_WIDTH 16 107 #define ALPHA_BITWIDTH 32U 108 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 109 110 #define PLL_HUAYRA_M_WIDTH 8 111 #define PLL_HUAYRA_M_SHIFT 8 112 #define PLL_HUAYRA_M_MASK 0xff 113 #define PLL_HUAYRA_N_SHIFT 0 114 #define PLL_HUAYRA_N_MASK 0xff 115 #define PLL_HUAYRA_ALPHA_WIDTH 16 116 117 #define FABIA_OPMODE_STANDBY 0x0 118 #define FABIA_OPMODE_RUN 0x1 119 120 #define FABIA_PLL_OUT_MASK 0x7 121 #define FABIA_PLL_RATE_MARGIN 500 122 123 #define pll_alpha_width(p) \ 124 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 125 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 126 127 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 128 129 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 130 struct clk_alpha_pll, clkr) 131 132 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 133 struct clk_alpha_pll_postdiv, clkr) 134 135 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 136 const char *action) 137 { 138 u32 val; 139 int count; 140 int ret; 141 const char *name = clk_hw_get_name(&pll->clkr.hw); 142 143 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 144 if (ret) 145 return ret; 146 147 for (count = 100; count > 0; count--) { 148 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 149 if (ret) 150 return ret; 151 if (inverse && !(val & mask)) 152 return 0; 153 else if ((val & mask) == mask) 154 return 0; 155 156 udelay(1); 157 } 158 159 WARN(1, "%s failed to %s!\n", name, action); 160 return -ETIMEDOUT; 161 } 162 163 #define wait_for_pll_enable_active(pll) \ 164 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 165 166 #define wait_for_pll_enable_lock(pll) \ 167 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 168 169 #define wait_for_pll_disable(pll) \ 170 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 171 172 #define wait_for_pll_offline(pll) \ 173 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 174 175 #define wait_for_pll_update(pll) \ 176 wait_for_pll(pll, PLL_UPDATE, 1, "update") 177 178 #define wait_for_pll_update_ack_set(pll) \ 179 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 180 181 #define wait_for_pll_update_ack_clear(pll) \ 182 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 183 184 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 185 const struct alpha_pll_config *config) 186 { 187 u32 val, mask; 188 189 regmap_write(regmap, PLL_L_VAL(pll), config->l); 190 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 191 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 192 193 if (pll_has_64bit_config(pll)) 194 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 195 config->config_ctl_hi_val); 196 197 if (pll_alpha_width(pll) > 32) 198 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 199 200 val = config->main_output_mask; 201 val |= config->aux_output_mask; 202 val |= config->aux2_output_mask; 203 val |= config->early_output_mask; 204 val |= config->pre_div_val; 205 val |= config->post_div_val; 206 val |= config->vco_val; 207 val |= config->alpha_en_mask; 208 val |= config->alpha_mode_mask; 209 210 mask = config->main_output_mask; 211 mask |= config->aux_output_mask; 212 mask |= config->aux2_output_mask; 213 mask |= config->early_output_mask; 214 mask |= config->pre_div_mask; 215 mask |= config->post_div_mask; 216 mask |= config->vco_mask; 217 218 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 219 220 if (pll->flags & SUPPORTS_FSM_MODE) 221 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 222 } 223 224 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 225 { 226 int ret; 227 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 228 u32 val; 229 230 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 231 if (ret) 232 return ret; 233 234 val |= PLL_FSM_ENA; 235 236 if (pll->flags & SUPPORTS_OFFLINE_REQ) 237 val &= ~PLL_OFFLINE_REQ; 238 239 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 240 if (ret) 241 return ret; 242 243 /* Make sure enable request goes through before waiting for update */ 244 mb(); 245 246 return wait_for_pll_enable_active(pll); 247 } 248 249 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 250 { 251 int ret; 252 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 253 u32 val; 254 255 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 256 if (ret) 257 return; 258 259 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 260 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 261 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 262 if (ret) 263 return; 264 265 ret = wait_for_pll_offline(pll); 266 if (ret) 267 return; 268 } 269 270 /* Disable hwfsm */ 271 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 272 PLL_FSM_ENA, 0); 273 if (ret) 274 return; 275 276 wait_for_pll_disable(pll); 277 } 278 279 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 280 { 281 int ret; 282 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 283 u32 val; 284 285 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 286 if (ret) 287 return ret; 288 289 return !!(val & mask); 290 } 291 292 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 293 { 294 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 295 } 296 297 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 298 { 299 return pll_is_enabled(hw, PLL_LOCK_DET); 300 } 301 302 static int clk_alpha_pll_enable(struct clk_hw *hw) 303 { 304 int ret; 305 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 306 u32 val, mask; 307 308 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 309 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 310 if (ret) 311 return ret; 312 313 /* If in FSM mode, just vote for it */ 314 if (val & PLL_VOTE_FSM_ENA) { 315 ret = clk_enable_regmap(hw); 316 if (ret) 317 return ret; 318 return wait_for_pll_enable_active(pll); 319 } 320 321 /* Skip if already enabled */ 322 if ((val & mask) == mask) 323 return 0; 324 325 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 326 PLL_BYPASSNL, PLL_BYPASSNL); 327 if (ret) 328 return ret; 329 330 /* 331 * H/W requires a 5us delay between disabling the bypass and 332 * de-asserting the reset. 333 */ 334 mb(); 335 udelay(5); 336 337 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 338 PLL_RESET_N, PLL_RESET_N); 339 if (ret) 340 return ret; 341 342 ret = wait_for_pll_enable_lock(pll); 343 if (ret) 344 return ret; 345 346 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 347 PLL_OUTCTRL, PLL_OUTCTRL); 348 349 /* Ensure that the write above goes through before returning. */ 350 mb(); 351 return ret; 352 } 353 354 static void clk_alpha_pll_disable(struct clk_hw *hw) 355 { 356 int ret; 357 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 358 u32 val, mask; 359 360 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 361 if (ret) 362 return; 363 364 /* If in FSM mode, just unvote it */ 365 if (val & PLL_VOTE_FSM_ENA) { 366 clk_disable_regmap(hw); 367 return; 368 } 369 370 mask = PLL_OUTCTRL; 371 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 372 373 /* Delay of 2 output clock ticks required until output is disabled */ 374 mb(); 375 udelay(1); 376 377 mask = PLL_RESET_N | PLL_BYPASSNL; 378 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 379 } 380 381 static unsigned long 382 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 383 { 384 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 385 } 386 387 static unsigned long 388 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 389 u32 alpha_width) 390 { 391 u64 remainder; 392 u64 quotient; 393 394 quotient = rate; 395 remainder = do_div(quotient, prate); 396 *l = quotient; 397 398 if (!remainder) { 399 *a = 0; 400 return rate; 401 } 402 403 /* Upper ALPHA_BITWIDTH bits of Alpha */ 404 quotient = remainder << ALPHA_SHIFT(alpha_width); 405 406 remainder = do_div(quotient, prate); 407 408 if (remainder) 409 quotient++; 410 411 *a = quotient; 412 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 413 } 414 415 static const struct pll_vco * 416 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 417 { 418 const struct pll_vco *v = pll->vco_table; 419 const struct pll_vco *end = v + pll->num_vco; 420 421 for (; v < end; v++) 422 if (rate >= v->min_freq && rate <= v->max_freq) 423 return v; 424 425 return NULL; 426 } 427 428 static unsigned long 429 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 430 { 431 u32 l, low, high, ctl; 432 u64 a = 0, prate = parent_rate; 433 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 434 u32 alpha_width = pll_alpha_width(pll); 435 436 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 437 438 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 439 if (ctl & PLL_ALPHA_EN) { 440 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 441 if (alpha_width > 32) { 442 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 443 &high); 444 a = (u64)high << 32 | low; 445 } else { 446 a = low & GENMASK(alpha_width - 1, 0); 447 } 448 449 if (alpha_width > ALPHA_BITWIDTH) 450 a >>= alpha_width - ALPHA_BITWIDTH; 451 } 452 453 return alpha_pll_calc_rate(prate, l, a, alpha_width); 454 } 455 456 457 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 458 { 459 int ret; 460 u32 mode; 461 462 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 463 464 /* Latch the input to the PLL */ 465 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 466 PLL_UPDATE); 467 468 /* Wait for 2 reference cycle before checking ACK bit */ 469 udelay(1); 470 471 /* 472 * PLL will latch the new L, Alpha and freq control word. 473 * PLL will respond by raising PLL_ACK_LATCH output when new programming 474 * has been latched in and PLL is being updated. When 475 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 476 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 477 */ 478 if (mode & PLL_UPDATE_BYPASS) { 479 ret = wait_for_pll_update_ack_set(pll); 480 if (ret) 481 return ret; 482 483 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 484 } else { 485 ret = wait_for_pll_update(pll); 486 if (ret) 487 return ret; 488 } 489 490 ret = wait_for_pll_update_ack_clear(pll); 491 if (ret) 492 return ret; 493 494 /* Wait for PLL output to stabilize */ 495 udelay(10); 496 497 return 0; 498 } 499 500 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 501 int (*is_enabled)(struct clk_hw *)) 502 { 503 if (!is_enabled(&pll->clkr.hw) || 504 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 505 return 0; 506 507 return __clk_alpha_pll_update_latch(pll); 508 } 509 510 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 511 unsigned long prate, 512 int (*is_enabled)(struct clk_hw *)) 513 { 514 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 515 const struct pll_vco *vco; 516 u32 l, alpha_width = pll_alpha_width(pll); 517 u64 a; 518 519 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 520 vco = alpha_pll_find_vco(pll, rate); 521 if (pll->vco_table && !vco) { 522 pr_err("alpha pll not in a valid vco range\n"); 523 return -EINVAL; 524 } 525 526 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 527 528 if (alpha_width > ALPHA_BITWIDTH) 529 a <<= alpha_width - ALPHA_BITWIDTH; 530 531 if (alpha_width > 32) 532 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 533 534 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 535 536 if (vco) { 537 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 538 PLL_VCO_MASK << PLL_VCO_SHIFT, 539 vco->val << PLL_VCO_SHIFT); 540 } 541 542 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 543 PLL_ALPHA_EN, PLL_ALPHA_EN); 544 545 return clk_alpha_pll_update_latch(pll, is_enabled); 546 } 547 548 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 549 unsigned long prate) 550 { 551 return __clk_alpha_pll_set_rate(hw, rate, prate, 552 clk_alpha_pll_is_enabled); 553 } 554 555 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 556 unsigned long prate) 557 { 558 return __clk_alpha_pll_set_rate(hw, rate, prate, 559 clk_alpha_pll_hwfsm_is_enabled); 560 } 561 562 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 563 unsigned long *prate) 564 { 565 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 566 u32 l, alpha_width = pll_alpha_width(pll); 567 u64 a; 568 unsigned long min_freq, max_freq; 569 570 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 571 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 572 return rate; 573 574 min_freq = pll->vco_table[0].min_freq; 575 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 576 577 return clamp(rate, min_freq, max_freq); 578 } 579 580 static unsigned long 581 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 582 { 583 /* 584 * a contains 16 bit alpha_val in two’s compliment number in the range 585 * of [-0.5, 0.5). 586 */ 587 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 588 l -= 1; 589 590 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 591 } 592 593 static unsigned long 594 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 595 u32 *l, u32 *a) 596 { 597 u64 remainder; 598 u64 quotient; 599 600 quotient = rate; 601 remainder = do_div(quotient, prate); 602 *l = quotient; 603 604 if (!remainder) { 605 *a = 0; 606 return rate; 607 } 608 609 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 610 remainder = do_div(quotient, prate); 611 612 if (remainder) 613 quotient++; 614 615 /* 616 * alpha_val should be in two’s compliment number in the range 617 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 618 * since alpha value will be subtracted in this case. 619 */ 620 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 621 *l += 1; 622 623 *a = quotient; 624 return alpha_huayra_pll_calc_rate(prate, *l, *a); 625 } 626 627 static unsigned long 628 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 629 { 630 u64 rate = parent_rate, tmp; 631 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 632 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 633 634 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 635 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 636 637 if (ctl & PLL_ALPHA_EN) { 638 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 639 /* 640 * Depending upon alpha_mode, it can be treated as M/N value or 641 * as a two’s compliment number. When alpha_mode=1, 642 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 643 * 644 * Fout=FIN*(L+(M/N)) 645 * 646 * M is a signed number (-128 to 127) and N is unsigned 647 * (0 to 255). M/N has to be within +/-0.5. 648 * 649 * When alpha_mode=0, it is a two’s compliment number in the 650 * range [-0.5, 0.5). 651 * 652 * Fout=FIN*(L+(alpha_val)/2^16) 653 * 654 * where alpha_val is two’s compliment number. 655 */ 656 if (!(ctl & PLL_ALPHA_MODE)) 657 return alpha_huayra_pll_calc_rate(rate, l, alpha); 658 659 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 660 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 661 662 rate *= l; 663 tmp = parent_rate; 664 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 665 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 666 tmp *= alpha_m; 667 do_div(tmp, alpha_n); 668 rate -= tmp; 669 } else { 670 tmp *= alpha_m; 671 do_div(tmp, alpha_n); 672 rate += tmp; 673 } 674 675 return rate; 676 } 677 678 return alpha_huayra_pll_calc_rate(rate, l, alpha); 679 } 680 681 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 682 unsigned long prate) 683 { 684 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 685 u32 l, a, ctl, cur_alpha = 0; 686 687 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 688 689 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 690 691 if (ctl & PLL_ALPHA_EN) 692 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 693 694 /* 695 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 696 * without having to go through the power on sequence. 697 */ 698 if (clk_alpha_pll_is_enabled(hw)) { 699 if (cur_alpha != a) { 700 pr_err("clock needs to be gated %s\n", 701 clk_hw_get_name(hw)); 702 return -EBUSY; 703 } 704 705 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 706 /* Ensure that the write above goes to detect L val change. */ 707 mb(); 708 return wait_for_pll_enable_lock(pll); 709 } 710 711 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 712 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 713 714 if (a == 0) 715 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 716 PLL_ALPHA_EN, 0x0); 717 else 718 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 719 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 720 721 return 0; 722 } 723 724 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 725 unsigned long *prate) 726 { 727 u32 l, a; 728 729 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 730 } 731 732 const struct clk_ops clk_alpha_pll_ops = { 733 .enable = clk_alpha_pll_enable, 734 .disable = clk_alpha_pll_disable, 735 .is_enabled = clk_alpha_pll_is_enabled, 736 .recalc_rate = clk_alpha_pll_recalc_rate, 737 .round_rate = clk_alpha_pll_round_rate, 738 .set_rate = clk_alpha_pll_set_rate, 739 }; 740 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 741 742 const struct clk_ops clk_alpha_pll_huayra_ops = { 743 .enable = clk_alpha_pll_enable, 744 .disable = clk_alpha_pll_disable, 745 .is_enabled = clk_alpha_pll_is_enabled, 746 .recalc_rate = alpha_pll_huayra_recalc_rate, 747 .round_rate = alpha_pll_huayra_round_rate, 748 .set_rate = alpha_pll_huayra_set_rate, 749 }; 750 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 751 752 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 753 .enable = clk_alpha_pll_hwfsm_enable, 754 .disable = clk_alpha_pll_hwfsm_disable, 755 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 756 .recalc_rate = clk_alpha_pll_recalc_rate, 757 .round_rate = clk_alpha_pll_round_rate, 758 .set_rate = clk_alpha_pll_hwfsm_set_rate, 759 }; 760 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 761 762 static unsigned long 763 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 764 { 765 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 766 u32 ctl; 767 768 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 769 770 ctl >>= PLL_POST_DIV_SHIFT; 771 ctl &= PLL_POST_DIV_MASK(pll); 772 773 return parent_rate >> fls(ctl); 774 } 775 776 static const struct clk_div_table clk_alpha_div_table[] = { 777 { 0x0, 1 }, 778 { 0x1, 2 }, 779 { 0x3, 4 }, 780 { 0x7, 8 }, 781 { 0xf, 16 }, 782 { } 783 }; 784 785 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 786 { 0x0, 1 }, 787 { 0x1, 2 }, 788 { 0x3, 4 }, 789 { } 790 }; 791 792 static long 793 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 794 unsigned long *prate) 795 { 796 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 797 const struct clk_div_table *table; 798 799 if (pll->width == 2) 800 table = clk_alpha_2bit_div_table; 801 else 802 table = clk_alpha_div_table; 803 804 return divider_round_rate(hw, rate, prate, table, 805 pll->width, CLK_DIVIDER_POWER_OF_TWO); 806 } 807 808 static long 809 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 810 unsigned long *prate) 811 { 812 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 813 u32 ctl, div; 814 815 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 816 817 ctl >>= PLL_POST_DIV_SHIFT; 818 ctl &= BIT(pll->width) - 1; 819 div = 1 << fls(ctl); 820 821 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 822 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 823 824 return DIV_ROUND_UP_ULL((u64)*prate, div); 825 } 826 827 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 828 unsigned long parent_rate) 829 { 830 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 831 int div; 832 833 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 834 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; 835 836 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 837 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 838 div << PLL_POST_DIV_SHIFT); 839 } 840 841 const struct clk_ops clk_alpha_pll_postdiv_ops = { 842 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 843 .round_rate = clk_alpha_pll_postdiv_round_rate, 844 .set_rate = clk_alpha_pll_postdiv_set_rate, 845 }; 846 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 847 848 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 849 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 850 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 851 }; 852 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 853 854 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 855 const struct alpha_pll_config *config) 856 { 857 u32 val, mask; 858 859 if (config->l) 860 regmap_write(regmap, PLL_L_VAL(pll), config->l); 861 862 if (config->alpha) 863 regmap_write(regmap, PLL_FRAC(pll), config->alpha); 864 865 if (config->config_ctl_val) 866 regmap_write(regmap, PLL_CONFIG_CTL(pll), 867 config->config_ctl_val); 868 869 if (config->post_div_mask) { 870 mask = config->post_div_mask; 871 val = config->post_div_val; 872 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 873 } 874 875 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 876 PLL_UPDATE_BYPASS); 877 878 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 879 } 880 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 881 882 static int alpha_pll_fabia_enable(struct clk_hw *hw) 883 { 884 int ret; 885 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 886 u32 val, opmode_val; 887 struct regmap *regmap = pll->clkr.regmap; 888 889 ret = regmap_read(regmap, PLL_MODE(pll), &val); 890 if (ret) 891 return ret; 892 893 /* If in FSM mode, just vote for it */ 894 if (val & PLL_VOTE_FSM_ENA) { 895 ret = clk_enable_regmap(hw); 896 if (ret) 897 return ret; 898 return wait_for_pll_enable_active(pll); 899 } 900 901 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 902 if (ret) 903 return ret; 904 905 /* Skip If PLL is already running */ 906 if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL)) 907 return 0; 908 909 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 910 if (ret) 911 return ret; 912 913 ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY); 914 if (ret) 915 return ret; 916 917 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 918 PLL_RESET_N); 919 if (ret) 920 return ret; 921 922 ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN); 923 if (ret) 924 return ret; 925 926 ret = wait_for_pll_enable_lock(pll); 927 if (ret) 928 return ret; 929 930 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 931 FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK); 932 if (ret) 933 return ret; 934 935 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 936 PLL_OUTCTRL); 937 } 938 939 static void alpha_pll_fabia_disable(struct clk_hw *hw) 940 { 941 int ret; 942 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 943 u32 val; 944 struct regmap *regmap = pll->clkr.regmap; 945 946 ret = regmap_read(regmap, PLL_MODE(pll), &val); 947 if (ret) 948 return; 949 950 /* If in FSM mode, just unvote it */ 951 if (val & PLL_FSM_ENA) { 952 clk_disable_regmap(hw); 953 return; 954 } 955 956 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 957 if (ret) 958 return; 959 960 /* Disable main outputs */ 961 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK, 962 0); 963 if (ret) 964 return; 965 966 /* Place the PLL in STANDBY */ 967 regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY); 968 } 969 970 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 971 unsigned long parent_rate) 972 { 973 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 974 u32 l, frac, alpha_width = pll_alpha_width(pll); 975 976 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 977 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 978 979 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 980 } 981 982 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 983 unsigned long prate) 984 { 985 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 986 u32 val, l, alpha_width = pll_alpha_width(pll); 987 u64 a; 988 unsigned long rrate; 989 int ret = 0; 990 991 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 992 if (ret) 993 return ret; 994 995 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 996 997 /* 998 * Due to limited number of bits for fractional rate programming, the 999 * rounded up rate could be marginally higher than the requested rate. 1000 */ 1001 if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) { 1002 pr_err("Call set rate on the PLL with rounded rates!\n"); 1003 return -EINVAL; 1004 } 1005 1006 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1007 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1008 1009 return __clk_alpha_pll_update_latch(pll); 1010 } 1011 1012 const struct clk_ops clk_alpha_pll_fabia_ops = { 1013 .enable = alpha_pll_fabia_enable, 1014 .disable = alpha_pll_fabia_disable, 1015 .is_enabled = clk_alpha_pll_is_enabled, 1016 .set_rate = alpha_pll_fabia_set_rate, 1017 .recalc_rate = alpha_pll_fabia_recalc_rate, 1018 .round_rate = clk_alpha_pll_round_rate, 1019 }; 1020 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1021 1022 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1023 .enable = alpha_pll_fabia_enable, 1024 .disable = alpha_pll_fabia_disable, 1025 .is_enabled = clk_alpha_pll_is_enabled, 1026 .recalc_rate = alpha_pll_fabia_recalc_rate, 1027 .round_rate = clk_alpha_pll_round_rate, 1028 }; 1029 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1030 1031 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1032 unsigned long parent_rate) 1033 { 1034 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1035 u32 i, div = 1, val; 1036 int ret; 1037 1038 if (!pll->post_div_table) { 1039 pr_err("Missing the post_div_table for the PLL\n"); 1040 return -EINVAL; 1041 } 1042 1043 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1044 if (ret) 1045 return ret; 1046 1047 val >>= pll->post_div_shift; 1048 val &= BIT(pll->width) - 1; 1049 1050 for (i = 0; i < pll->num_post_div; i++) { 1051 if (pll->post_div_table[i].val == val) { 1052 div = pll->post_div_table[i].div; 1053 break; 1054 } 1055 } 1056 1057 return (parent_rate / div); 1058 } 1059 1060 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1061 unsigned long rate, unsigned long *prate) 1062 { 1063 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1064 1065 if (!pll->post_div_table) { 1066 pr_err("Missing the post_div_table for the PLL\n"); 1067 return -EINVAL; 1068 } 1069 1070 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1071 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1072 } 1073 1074 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1075 unsigned long rate, unsigned long parent_rate) 1076 { 1077 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1078 int i, val = 0, div, ret; 1079 1080 /* 1081 * If the PLL is in FSM mode, then treat set_rate callback as a 1082 * no-operation. 1083 */ 1084 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1085 if (ret) 1086 return ret; 1087 1088 if (val & PLL_VOTE_FSM_ENA) 1089 return 0; 1090 1091 if (!pll->post_div_table) { 1092 pr_err("Missing the post_div_table for the PLL\n"); 1093 return -EINVAL; 1094 } 1095 1096 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1097 for (i = 0; i < pll->num_post_div; i++) { 1098 if (pll->post_div_table[i].div == div) { 1099 val = pll->post_div_table[i].val; 1100 break; 1101 } 1102 } 1103 1104 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1105 (BIT(pll->width) - 1) << pll->post_div_shift, 1106 val << pll->post_div_shift); 1107 } 1108 1109 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1110 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1111 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1112 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1113 }; 1114 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1115