1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,camcc-sdm845.h> 12 13 #include "common.h" 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "gdsc.h" 19 20 enum { 21 P_BI_TCXO, 22 P_CAM_CC_PLL0_OUT_EVEN, 23 P_CAM_CC_PLL1_OUT_EVEN, 24 P_CAM_CC_PLL2_OUT_EVEN, 25 P_CAM_CC_PLL3_OUT_EVEN, 26 P_CORE_BI_PLL_TEST_SE, 27 }; 28 29 static const struct parent_map cam_cc_parent_map_0[] = { 30 { P_BI_TCXO, 0 }, 31 { P_CAM_CC_PLL2_OUT_EVEN, 1 }, 32 { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 33 { P_CAM_CC_PLL3_OUT_EVEN, 5 }, 34 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 35 { P_CORE_BI_PLL_TEST_SE, 7 }, 36 }; 37 38 static const char * const cam_cc_parent_names_0[] = { 39 "bi_tcxo", 40 "cam_cc_pll2_out_even", 41 "cam_cc_pll1_out_even", 42 "cam_cc_pll3_out_even", 43 "cam_cc_pll0_out_even", 44 "core_bi_pll_test_se", 45 }; 46 47 static struct clk_alpha_pll cam_cc_pll0 = { 48 .offset = 0x0, 49 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 50 .clkr = { 51 .hw.init = &(struct clk_init_data){ 52 .name = "cam_cc_pll0", 53 .parent_names = (const char *[]){ "bi_tcxo" }, 54 .num_parents = 1, 55 .ops = &clk_alpha_pll_fabia_ops, 56 }, 57 }, 58 }; 59 60 static const struct clk_div_table post_div_table_fabia_even[] = { 61 { 0x0, 1 }, 62 { 0x1, 2 }, 63 { } 64 }; 65 66 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 67 .offset = 0x0, 68 .post_div_shift = 8, 69 .post_div_table = post_div_table_fabia_even, 70 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 71 .width = 4, 72 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 73 .clkr.hw.init = &(struct clk_init_data){ 74 .name = "cam_cc_pll0_out_even", 75 .parent_names = (const char *[]){ "cam_cc_pll0" }, 76 .num_parents = 1, 77 .ops = &clk_alpha_pll_postdiv_fabia_ops, 78 }, 79 }; 80 81 static struct clk_alpha_pll cam_cc_pll1 = { 82 .offset = 0x1000, 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 84 .clkr = { 85 .hw.init = &(struct clk_init_data){ 86 .name = "cam_cc_pll1", 87 .parent_names = (const char *[]){ "bi_tcxo" }, 88 .num_parents = 1, 89 .ops = &clk_alpha_pll_fabia_ops, 90 }, 91 }, 92 }; 93 94 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 95 .offset = 0x1000, 96 .post_div_shift = 8, 97 .post_div_table = post_div_table_fabia_even, 98 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 99 .width = 4, 100 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 101 .clkr.hw.init = &(struct clk_init_data){ 102 .name = "cam_cc_pll1_out_even", 103 .parent_names = (const char *[]){ "cam_cc_pll1" }, 104 .num_parents = 1, 105 .ops = &clk_alpha_pll_postdiv_fabia_ops, 106 }, 107 }; 108 109 static struct clk_alpha_pll cam_cc_pll2 = { 110 .offset = 0x2000, 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 112 .clkr = { 113 .hw.init = &(struct clk_init_data){ 114 .name = "cam_cc_pll2", 115 .parent_names = (const char *[]){ "bi_tcxo" }, 116 .num_parents = 1, 117 .ops = &clk_alpha_pll_fabia_ops, 118 }, 119 }, 120 }; 121 122 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { 123 .offset = 0x2000, 124 .post_div_shift = 8, 125 .post_div_table = post_div_table_fabia_even, 126 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 127 .width = 4, 128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 129 .clkr.hw.init = &(struct clk_init_data){ 130 .name = "cam_cc_pll2_out_even", 131 .parent_names = (const char *[]){ "cam_cc_pll2" }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_postdiv_fabia_ops, 134 }, 135 }; 136 137 static struct clk_alpha_pll cam_cc_pll3 = { 138 .offset = 0x3000, 139 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 140 .clkr = { 141 .hw.init = &(struct clk_init_data){ 142 .name = "cam_cc_pll3", 143 .parent_names = (const char *[]){ "bi_tcxo" }, 144 .num_parents = 1, 145 .ops = &clk_alpha_pll_fabia_ops, 146 }, 147 }, 148 }; 149 150 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 151 .offset = 0x3000, 152 .post_div_shift = 8, 153 .post_div_table = post_div_table_fabia_even, 154 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 155 .width = 4, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 157 .clkr.hw.init = &(struct clk_init_data){ 158 .name = "cam_cc_pll3_out_even", 159 .parent_names = (const char *[]){ "cam_cc_pll3" }, 160 .num_parents = 1, 161 .ops = &clk_alpha_pll_postdiv_fabia_ops, 162 }, 163 }; 164 165 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 166 F(19200000, P_BI_TCXO, 1, 0, 0), 167 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 168 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 169 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 170 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 171 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 172 { } 173 }; 174 175 /* 176 * As per HW design, some of the CAMCC RCGs needs to 177 * move to XO clock during their clock disable so using 178 * clk_rcg2_shared_ops for such RCGs. This is required 179 * to power down the camera memories gracefully. 180 * Also, use CLK_SET_RATE_PARENT flag for the RCGs which 181 * have CAM_CC_PLL2_OUT_EVEN PLL as parent in frequency 182 * table and requires reconfiguration of the PLL frequency. 183 */ 184 static struct clk_rcg2 cam_cc_bps_clk_src = { 185 .cmd_rcgr = 0x600c, 186 .mnd_width = 0, 187 .hid_width = 5, 188 .parent_map = cam_cc_parent_map_0, 189 .freq_tbl = ftbl_cam_cc_bps_clk_src, 190 .clkr.hw.init = &(struct clk_init_data){ 191 .name = "cam_cc_bps_clk_src", 192 .parent_names = cam_cc_parent_names_0, 193 .num_parents = 6, 194 .flags = CLK_SET_RATE_PARENT, 195 .ops = &clk_rcg2_shared_ops, 196 }, 197 }; 198 199 static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = { 200 F(19200000, P_BI_TCXO, 1, 0, 0), 201 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 202 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 203 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 204 { } 205 }; 206 207 static struct clk_rcg2 cam_cc_cci_clk_src = { 208 .cmd_rcgr = 0xb0d8, 209 .mnd_width = 8, 210 .hid_width = 5, 211 .parent_map = cam_cc_parent_map_0, 212 .freq_tbl = ftbl_cam_cc_cci_clk_src, 213 .clkr.hw.init = &(struct clk_init_data){ 214 .name = "cam_cc_cci_clk_src", 215 .parent_names = cam_cc_parent_names_0, 216 .num_parents = 6, 217 .ops = &clk_rcg2_ops, 218 }, 219 }; 220 221 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 222 F(19200000, P_BI_TCXO, 1, 0, 0), 223 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 224 { } 225 }; 226 227 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 228 .cmd_rcgr = 0x9060, 229 .mnd_width = 0, 230 .hid_width = 5, 231 .parent_map = cam_cc_parent_map_0, 232 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 233 .clkr.hw.init = &(struct clk_init_data){ 234 .name = "cam_cc_cphy_rx_clk_src", 235 .parent_names = cam_cc_parent_names_0, 236 .num_parents = 6, 237 .ops = &clk_rcg2_ops, 238 }, 239 }; 240 241 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 242 F(19200000, P_BI_TCXO, 1, 0, 0), 243 F(240000000, P_CAM_CC_PLL2_OUT_EVEN, 2, 0, 0), 244 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0), 245 { } 246 }; 247 248 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 249 .cmd_rcgr = 0x5004, 250 .mnd_width = 0, 251 .hid_width = 5, 252 .parent_map = cam_cc_parent_map_0, 253 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 254 .clkr.hw.init = &(struct clk_init_data){ 255 .name = "cam_cc_csi0phytimer_clk_src", 256 .parent_names = cam_cc_parent_names_0, 257 .num_parents = 6, 258 .flags = CLK_SET_RATE_PARENT, 259 .ops = &clk_rcg2_ops, 260 }, 261 }; 262 263 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 264 .cmd_rcgr = 0x5028, 265 .mnd_width = 0, 266 .hid_width = 5, 267 .parent_map = cam_cc_parent_map_0, 268 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 269 .clkr.hw.init = &(struct clk_init_data){ 270 .name = "cam_cc_csi1phytimer_clk_src", 271 .parent_names = cam_cc_parent_names_0, 272 .num_parents = 6, 273 .flags = CLK_SET_RATE_PARENT, 274 .ops = &clk_rcg2_ops, 275 }, 276 }; 277 278 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 279 .cmd_rcgr = 0x504c, 280 .mnd_width = 0, 281 .hid_width = 5, 282 .parent_map = cam_cc_parent_map_0, 283 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 284 .clkr.hw.init = &(struct clk_init_data){ 285 .name = "cam_cc_csi2phytimer_clk_src", 286 .parent_names = cam_cc_parent_names_0, 287 .num_parents = 6, 288 .flags = CLK_SET_RATE_PARENT, 289 .ops = &clk_rcg2_ops, 290 }, 291 }; 292 293 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 294 .cmd_rcgr = 0x5070, 295 .mnd_width = 0, 296 .hid_width = 5, 297 .parent_map = cam_cc_parent_map_0, 298 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 299 .clkr.hw.init = &(struct clk_init_data){ 300 .name = "cam_cc_csi3phytimer_clk_src", 301 .parent_names = cam_cc_parent_names_0, 302 .num_parents = 6, 303 .flags = CLK_SET_RATE_PARENT, 304 .ops = &clk_rcg2_ops, 305 }, 306 }; 307 308 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 309 F(19200000, P_BI_TCXO, 1, 0, 0), 310 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 311 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 312 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 313 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 314 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 315 { } 316 }; 317 318 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 319 .cmd_rcgr = 0x6038, 320 .mnd_width = 0, 321 .hid_width = 5, 322 .parent_map = cam_cc_parent_map_0, 323 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 324 .clkr.hw.init = &(struct clk_init_data){ 325 .name = "cam_cc_fast_ahb_clk_src", 326 .parent_names = cam_cc_parent_names_0, 327 .num_parents = 6, 328 .ops = &clk_rcg2_ops, 329 }, 330 }; 331 332 static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = { 333 F(19200000, P_BI_TCXO, 1, 0, 0), 334 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 335 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 336 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 337 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 338 { } 339 }; 340 341 static struct clk_rcg2 cam_cc_fd_core_clk_src = { 342 .cmd_rcgr = 0xb0b0, 343 .mnd_width = 0, 344 .hid_width = 5, 345 .parent_map = cam_cc_parent_map_0, 346 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 347 .clkr.hw.init = &(struct clk_init_data){ 348 .name = "cam_cc_fd_core_clk_src", 349 .parent_names = cam_cc_parent_names_0, 350 .num_parents = 6, 351 .ops = &clk_rcg2_shared_ops, 352 }, 353 }; 354 355 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 356 F(19200000, P_BI_TCXO, 1, 0, 0), 357 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 358 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 359 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 360 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 361 { } 362 }; 363 364 static struct clk_rcg2 cam_cc_icp_clk_src = { 365 .cmd_rcgr = 0xb088, 366 .mnd_width = 0, 367 .hid_width = 5, 368 .parent_map = cam_cc_parent_map_0, 369 .freq_tbl = ftbl_cam_cc_icp_clk_src, 370 .clkr.hw.init = &(struct clk_init_data){ 371 .name = "cam_cc_icp_clk_src", 372 .parent_names = cam_cc_parent_names_0, 373 .num_parents = 6, 374 .ops = &clk_rcg2_shared_ops, 375 }, 376 }; 377 378 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 379 F(19200000, P_BI_TCXO, 1, 0, 0), 380 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 381 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0), 382 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 383 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 384 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 385 { } 386 }; 387 388 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 389 .cmd_rcgr = 0x900c, 390 .mnd_width = 0, 391 .hid_width = 5, 392 .parent_map = cam_cc_parent_map_0, 393 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 394 .clkr.hw.init = &(struct clk_init_data){ 395 .name = "cam_cc_ife_0_clk_src", 396 .parent_names = cam_cc_parent_names_0, 397 .num_parents = 6, 398 .flags = CLK_SET_RATE_PARENT, 399 .ops = &clk_rcg2_shared_ops, 400 }, 401 }; 402 403 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 404 F(19200000, P_BI_TCXO, 1, 0, 0), 405 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 406 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 407 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 408 { } 409 }; 410 411 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 412 .cmd_rcgr = 0x9038, 413 .mnd_width = 0, 414 .hid_width = 5, 415 .parent_map = cam_cc_parent_map_0, 416 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 417 .clkr.hw.init = &(struct clk_init_data){ 418 .name = "cam_cc_ife_0_csid_clk_src", 419 .parent_names = cam_cc_parent_names_0, 420 .num_parents = 6, 421 .ops = &clk_rcg2_shared_ops, 422 }, 423 }; 424 425 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 426 .cmd_rcgr = 0xa00c, 427 .mnd_width = 0, 428 .hid_width = 5, 429 .parent_map = cam_cc_parent_map_0, 430 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 431 .clkr.hw.init = &(struct clk_init_data){ 432 .name = "cam_cc_ife_1_clk_src", 433 .parent_names = cam_cc_parent_names_0, 434 .num_parents = 6, 435 .flags = CLK_SET_RATE_PARENT, 436 .ops = &clk_rcg2_shared_ops, 437 }, 438 }; 439 440 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 441 .cmd_rcgr = 0xa030, 442 .mnd_width = 0, 443 .hid_width = 5, 444 .parent_map = cam_cc_parent_map_0, 445 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 446 .clkr.hw.init = &(struct clk_init_data){ 447 .name = "cam_cc_ife_1_csid_clk_src", 448 .parent_names = cam_cc_parent_names_0, 449 .num_parents = 6, 450 .ops = &clk_rcg2_shared_ops, 451 }, 452 }; 453 454 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 455 .cmd_rcgr = 0xb004, 456 .mnd_width = 0, 457 .hid_width = 5, 458 .parent_map = cam_cc_parent_map_0, 459 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 460 .clkr.hw.init = &(struct clk_init_data){ 461 .name = "cam_cc_ife_lite_clk_src", 462 .parent_names = cam_cc_parent_names_0, 463 .num_parents = 6, 464 .flags = CLK_SET_RATE_PARENT, 465 .ops = &clk_rcg2_shared_ops, 466 }, 467 }; 468 469 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 470 .cmd_rcgr = 0xb024, 471 .mnd_width = 0, 472 .hid_width = 5, 473 .parent_map = cam_cc_parent_map_0, 474 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 475 .clkr.hw.init = &(struct clk_init_data){ 476 .name = "cam_cc_ife_lite_csid_clk_src", 477 .parent_names = cam_cc_parent_names_0, 478 .num_parents = 6, 479 .ops = &clk_rcg2_shared_ops, 480 }, 481 }; 482 483 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 484 F(19200000, P_BI_TCXO, 1, 0, 0), 485 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 486 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 487 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 488 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 489 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 490 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 491 { } 492 }; 493 494 static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 495 .cmd_rcgr = 0x700c, 496 .mnd_width = 0, 497 .hid_width = 5, 498 .parent_map = cam_cc_parent_map_0, 499 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 500 .clkr.hw.init = &(struct clk_init_data){ 501 .name = "cam_cc_ipe_0_clk_src", 502 .parent_names = cam_cc_parent_names_0, 503 .num_parents = 6, 504 .flags = CLK_SET_RATE_PARENT, 505 .ops = &clk_rcg2_shared_ops, 506 }, 507 }; 508 509 static struct clk_rcg2 cam_cc_ipe_1_clk_src = { 510 .cmd_rcgr = 0x800c, 511 .mnd_width = 0, 512 .hid_width = 5, 513 .parent_map = cam_cc_parent_map_0, 514 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 515 .clkr.hw.init = &(struct clk_init_data){ 516 .name = "cam_cc_ipe_1_clk_src", 517 .parent_names = cam_cc_parent_names_0, 518 .num_parents = 6, 519 .flags = CLK_SET_RATE_PARENT, 520 .ops = &clk_rcg2_shared_ops, 521 }, 522 }; 523 524 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 525 .cmd_rcgr = 0xb04c, 526 .mnd_width = 0, 527 .hid_width = 5, 528 .parent_map = cam_cc_parent_map_0, 529 .freq_tbl = ftbl_cam_cc_bps_clk_src, 530 .clkr.hw.init = &(struct clk_init_data){ 531 .name = "cam_cc_jpeg_clk_src", 532 .parent_names = cam_cc_parent_names_0, 533 .num_parents = 6, 534 .flags = CLK_SET_RATE_PARENT, 535 .ops = &clk_rcg2_shared_ops, 536 }, 537 }; 538 539 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 540 F(19200000, P_BI_TCXO, 1, 0, 0), 541 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 542 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 543 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0), 544 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0), 545 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 546 { } 547 }; 548 549 static struct clk_rcg2 cam_cc_lrme_clk_src = { 550 .cmd_rcgr = 0xb0f8, 551 .mnd_width = 0, 552 .hid_width = 5, 553 .parent_map = cam_cc_parent_map_0, 554 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 555 .clkr.hw.init = &(struct clk_init_data){ 556 .name = "cam_cc_lrme_clk_src", 557 .parent_names = cam_cc_parent_names_0, 558 .num_parents = 6, 559 .flags = CLK_SET_RATE_PARENT, 560 .ops = &clk_rcg2_shared_ops, 561 }, 562 }; 563 564 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 565 F(19200000, P_BI_TCXO, 1, 0, 0), 566 F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 2), 567 F(33333333, P_CAM_CC_PLL0_OUT_EVEN, 2, 1, 9), 568 F(34285714, P_CAM_CC_PLL2_OUT_EVEN, 14, 0, 0), 569 { } 570 }; 571 572 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 573 .cmd_rcgr = 0x4004, 574 .mnd_width = 8, 575 .hid_width = 5, 576 .parent_map = cam_cc_parent_map_0, 577 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 578 .clkr.hw.init = &(struct clk_init_data){ 579 .name = "cam_cc_mclk0_clk_src", 580 .parent_names = cam_cc_parent_names_0, 581 .num_parents = 6, 582 .flags = CLK_SET_RATE_PARENT, 583 .ops = &clk_rcg2_ops, 584 }, 585 }; 586 587 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 588 .cmd_rcgr = 0x4024, 589 .mnd_width = 8, 590 .hid_width = 5, 591 .parent_map = cam_cc_parent_map_0, 592 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 593 .clkr.hw.init = &(struct clk_init_data){ 594 .name = "cam_cc_mclk1_clk_src", 595 .parent_names = cam_cc_parent_names_0, 596 .num_parents = 6, 597 .flags = CLK_SET_RATE_PARENT, 598 .ops = &clk_rcg2_ops, 599 }, 600 }; 601 602 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 603 .cmd_rcgr = 0x4044, 604 .mnd_width = 8, 605 .hid_width = 5, 606 .parent_map = cam_cc_parent_map_0, 607 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 608 .clkr.hw.init = &(struct clk_init_data){ 609 .name = "cam_cc_mclk2_clk_src", 610 .parent_names = cam_cc_parent_names_0, 611 .num_parents = 6, 612 .flags = CLK_SET_RATE_PARENT, 613 .ops = &clk_rcg2_ops, 614 }, 615 }; 616 617 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 618 .cmd_rcgr = 0x4064, 619 .mnd_width = 8, 620 .hid_width = 5, 621 .parent_map = cam_cc_parent_map_0, 622 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 623 .clkr.hw.init = &(struct clk_init_data){ 624 .name = "cam_cc_mclk3_clk_src", 625 .parent_names = cam_cc_parent_names_0, 626 .num_parents = 6, 627 .flags = CLK_SET_RATE_PARENT, 628 .ops = &clk_rcg2_ops, 629 }, 630 }; 631 632 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 633 F(19200000, P_BI_TCXO, 1, 0, 0), 634 F(60000000, P_CAM_CC_PLL0_OUT_EVEN, 10, 0, 0), 635 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0), 636 F(73846154, P_CAM_CC_PLL2_OUT_EVEN, 6.5, 0, 0), 637 F(80000000, P_CAM_CC_PLL2_OUT_EVEN, 6, 0, 0), 638 { } 639 }; 640 641 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 642 .cmd_rcgr = 0x6054, 643 .mnd_width = 0, 644 .hid_width = 5, 645 .parent_map = cam_cc_parent_map_0, 646 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 647 .clkr.hw.init = &(struct clk_init_data){ 648 .name = "cam_cc_slow_ahb_clk_src", 649 .parent_names = cam_cc_parent_names_0, 650 .num_parents = 6, 651 .flags = CLK_SET_RATE_PARENT, 652 .ops = &clk_rcg2_ops, 653 }, 654 }; 655 656 static struct clk_branch cam_cc_bps_ahb_clk = { 657 .halt_reg = 0x606c, 658 .halt_check = BRANCH_HALT, 659 .clkr = { 660 .enable_reg = 0x606c, 661 .enable_mask = BIT(0), 662 .hw.init = &(struct clk_init_data){ 663 .name = "cam_cc_bps_ahb_clk", 664 .parent_names = (const char *[]){ 665 "cam_cc_slow_ahb_clk_src", 666 }, 667 .num_parents = 1, 668 .flags = CLK_SET_RATE_PARENT, 669 .ops = &clk_branch2_ops, 670 }, 671 }, 672 }; 673 674 static struct clk_branch cam_cc_bps_areg_clk = { 675 .halt_reg = 0x6050, 676 .halt_check = BRANCH_HALT, 677 .clkr = { 678 .enable_reg = 0x6050, 679 .enable_mask = BIT(0), 680 .hw.init = &(struct clk_init_data){ 681 .name = "cam_cc_bps_areg_clk", 682 .parent_names = (const char *[]){ 683 "cam_cc_fast_ahb_clk_src", 684 }, 685 .num_parents = 1, 686 .flags = CLK_SET_RATE_PARENT, 687 .ops = &clk_branch2_ops, 688 }, 689 }, 690 }; 691 692 static struct clk_branch cam_cc_bps_axi_clk = { 693 .halt_reg = 0x6034, 694 .halt_check = BRANCH_HALT, 695 .clkr = { 696 .enable_reg = 0x6034, 697 .enable_mask = BIT(0), 698 .hw.init = &(struct clk_init_data){ 699 .name = "cam_cc_bps_axi_clk", 700 .ops = &clk_branch2_ops, 701 }, 702 }, 703 }; 704 705 static struct clk_branch cam_cc_bps_clk = { 706 .halt_reg = 0x6024, 707 .halt_check = BRANCH_HALT, 708 .clkr = { 709 .enable_reg = 0x6024, 710 .enable_mask = BIT(0), 711 .hw.init = &(struct clk_init_data){ 712 .name = "cam_cc_bps_clk", 713 .parent_names = (const char *[]){ 714 "cam_cc_bps_clk_src", 715 }, 716 .num_parents = 1, 717 .flags = CLK_SET_RATE_PARENT, 718 .ops = &clk_branch2_ops, 719 }, 720 }, 721 }; 722 723 static struct clk_branch cam_cc_camnoc_atb_clk = { 724 .halt_reg = 0xb12c, 725 .halt_check = BRANCH_HALT, 726 .clkr = { 727 .enable_reg = 0xb12c, 728 .enable_mask = BIT(0), 729 .hw.init = &(struct clk_init_data){ 730 .name = "cam_cc_camnoc_atb_clk", 731 .ops = &clk_branch2_ops, 732 }, 733 }, 734 }; 735 736 static struct clk_branch cam_cc_camnoc_axi_clk = { 737 .halt_reg = 0xb124, 738 .halt_check = BRANCH_HALT, 739 .clkr = { 740 .enable_reg = 0xb124, 741 .enable_mask = BIT(0), 742 .hw.init = &(struct clk_init_data){ 743 .name = "cam_cc_camnoc_axi_clk", 744 .ops = &clk_branch2_ops, 745 }, 746 }, 747 }; 748 749 static struct clk_branch cam_cc_cci_clk = { 750 .halt_reg = 0xb0f0, 751 .halt_check = BRANCH_HALT, 752 .clkr = { 753 .enable_reg = 0xb0f0, 754 .enable_mask = BIT(0), 755 .hw.init = &(struct clk_init_data){ 756 .name = "cam_cc_cci_clk", 757 .parent_names = (const char *[]){ 758 "cam_cc_cci_clk_src", 759 }, 760 .num_parents = 1, 761 .flags = CLK_SET_RATE_PARENT, 762 .ops = &clk_branch2_ops, 763 }, 764 }, 765 }; 766 767 static struct clk_branch cam_cc_cpas_ahb_clk = { 768 .halt_reg = 0xb11c, 769 .halt_check = BRANCH_HALT, 770 .clkr = { 771 .enable_reg = 0xb11c, 772 .enable_mask = BIT(0), 773 .hw.init = &(struct clk_init_data){ 774 .name = "cam_cc_cpas_ahb_clk", 775 .parent_names = (const char *[]){ 776 "cam_cc_slow_ahb_clk_src", 777 }, 778 .num_parents = 1, 779 .flags = CLK_SET_RATE_PARENT, 780 .ops = &clk_branch2_ops, 781 }, 782 }, 783 }; 784 785 static struct clk_branch cam_cc_csi0phytimer_clk = { 786 .halt_reg = 0x501c, 787 .halt_check = BRANCH_HALT, 788 .clkr = { 789 .enable_reg = 0x501c, 790 .enable_mask = BIT(0), 791 .hw.init = &(struct clk_init_data){ 792 .name = "cam_cc_csi0phytimer_clk", 793 .parent_names = (const char *[]){ 794 "cam_cc_csi0phytimer_clk_src", 795 }, 796 .num_parents = 1, 797 .flags = CLK_SET_RATE_PARENT, 798 .ops = &clk_branch2_ops, 799 }, 800 }, 801 }; 802 803 static struct clk_branch cam_cc_csi1phytimer_clk = { 804 .halt_reg = 0x5040, 805 .halt_check = BRANCH_HALT, 806 .clkr = { 807 .enable_reg = 0x5040, 808 .enable_mask = BIT(0), 809 .hw.init = &(struct clk_init_data){ 810 .name = "cam_cc_csi1phytimer_clk", 811 .parent_names = (const char *[]){ 812 "cam_cc_csi1phytimer_clk_src", 813 }, 814 .num_parents = 1, 815 .flags = CLK_SET_RATE_PARENT, 816 .ops = &clk_branch2_ops, 817 }, 818 }, 819 }; 820 821 static struct clk_branch cam_cc_csi2phytimer_clk = { 822 .halt_reg = 0x5064, 823 .halt_check = BRANCH_HALT, 824 .clkr = { 825 .enable_reg = 0x5064, 826 .enable_mask = BIT(0), 827 .hw.init = &(struct clk_init_data){ 828 .name = "cam_cc_csi2phytimer_clk", 829 .parent_names = (const char *[]){ 830 "cam_cc_csi2phytimer_clk_src", 831 }, 832 .num_parents = 1, 833 .flags = CLK_SET_RATE_PARENT, 834 .ops = &clk_branch2_ops, 835 }, 836 }, 837 }; 838 839 static struct clk_branch cam_cc_csi3phytimer_clk = { 840 .halt_reg = 0x5088, 841 .halt_check = BRANCH_HALT, 842 .clkr = { 843 .enable_reg = 0x5088, 844 .enable_mask = BIT(0), 845 .hw.init = &(struct clk_init_data){ 846 .name = "cam_cc_csi3phytimer_clk", 847 .parent_names = (const char *[]){ 848 "cam_cc_csi3phytimer_clk_src", 849 }, 850 .num_parents = 1, 851 .flags = CLK_SET_RATE_PARENT, 852 .ops = &clk_branch2_ops, 853 }, 854 }, 855 }; 856 857 static struct clk_branch cam_cc_csiphy0_clk = { 858 .halt_reg = 0x5020, 859 .halt_check = BRANCH_HALT, 860 .clkr = { 861 .enable_reg = 0x5020, 862 .enable_mask = BIT(0), 863 .hw.init = &(struct clk_init_data){ 864 .name = "cam_cc_csiphy0_clk", 865 .parent_names = (const char *[]){ 866 "cam_cc_cphy_rx_clk_src", 867 }, 868 .num_parents = 1, 869 .flags = CLK_SET_RATE_PARENT, 870 .ops = &clk_branch2_ops, 871 }, 872 }, 873 }; 874 875 static struct clk_branch cam_cc_csiphy1_clk = { 876 .halt_reg = 0x5044, 877 .halt_check = BRANCH_HALT, 878 .clkr = { 879 .enable_reg = 0x5044, 880 .enable_mask = BIT(0), 881 .hw.init = &(struct clk_init_data){ 882 .name = "cam_cc_csiphy1_clk", 883 .parent_names = (const char *[]){ 884 "cam_cc_cphy_rx_clk_src", 885 }, 886 .num_parents = 1, 887 .flags = CLK_SET_RATE_PARENT, 888 .ops = &clk_branch2_ops, 889 }, 890 }, 891 }; 892 893 static struct clk_branch cam_cc_csiphy2_clk = { 894 .halt_reg = 0x5068, 895 .halt_check = BRANCH_HALT, 896 .clkr = { 897 .enable_reg = 0x5068, 898 .enable_mask = BIT(0), 899 .hw.init = &(struct clk_init_data){ 900 .name = "cam_cc_csiphy2_clk", 901 .parent_names = (const char *[]){ 902 "cam_cc_cphy_rx_clk_src", 903 }, 904 .num_parents = 1, 905 .flags = CLK_SET_RATE_PARENT, 906 .ops = &clk_branch2_ops, 907 }, 908 }, 909 }; 910 911 static struct clk_branch cam_cc_csiphy3_clk = { 912 .halt_reg = 0x508c, 913 .halt_check = BRANCH_HALT, 914 .clkr = { 915 .enable_reg = 0x508c, 916 .enable_mask = BIT(0), 917 .hw.init = &(struct clk_init_data){ 918 .name = "cam_cc_csiphy3_clk", 919 .parent_names = (const char *[]){ 920 "cam_cc_cphy_rx_clk_src", 921 }, 922 .num_parents = 1, 923 .flags = CLK_SET_RATE_PARENT, 924 .ops = &clk_branch2_ops, 925 }, 926 }, 927 }; 928 929 static struct clk_branch cam_cc_fd_core_clk = { 930 .halt_reg = 0xb0c8, 931 .halt_check = BRANCH_HALT, 932 .clkr = { 933 .enable_reg = 0xb0c8, 934 .enable_mask = BIT(0), 935 .hw.init = &(struct clk_init_data){ 936 .name = "cam_cc_fd_core_clk", 937 .parent_names = (const char *[]){ 938 "cam_cc_fd_core_clk_src", 939 }, 940 .num_parents = 1, 941 .flags = CLK_SET_RATE_PARENT, 942 .ops = &clk_branch2_ops, 943 }, 944 }, 945 }; 946 947 static struct clk_branch cam_cc_fd_core_uar_clk = { 948 .halt_reg = 0xb0d0, 949 .halt_check = BRANCH_HALT, 950 .clkr = { 951 .enable_reg = 0xb0d0, 952 .enable_mask = BIT(0), 953 .hw.init = &(struct clk_init_data){ 954 .name = "cam_cc_fd_core_uar_clk", 955 .parent_names = (const char *[]){ 956 "cam_cc_fd_core_clk_src", 957 }, 958 .num_parents = 1, 959 .ops = &clk_branch2_ops, 960 }, 961 }, 962 }; 963 964 static struct clk_branch cam_cc_icp_apb_clk = { 965 .halt_reg = 0xb084, 966 .halt_check = BRANCH_HALT, 967 .clkr = { 968 .enable_reg = 0xb084, 969 .enable_mask = BIT(0), 970 .hw.init = &(struct clk_init_data){ 971 .name = "cam_cc_icp_apb_clk", 972 .ops = &clk_branch2_ops, 973 }, 974 }, 975 }; 976 977 static struct clk_branch cam_cc_icp_atb_clk = { 978 .halt_reg = 0xb078, 979 .halt_check = BRANCH_HALT, 980 .clkr = { 981 .enable_reg = 0xb078, 982 .enable_mask = BIT(0), 983 .hw.init = &(struct clk_init_data){ 984 .name = "cam_cc_icp_atb_clk", 985 .ops = &clk_branch2_ops, 986 }, 987 }, 988 }; 989 990 static struct clk_branch cam_cc_icp_clk = { 991 .halt_reg = 0xb0a0, 992 .halt_check = BRANCH_HALT, 993 .clkr = { 994 .enable_reg = 0xb0a0, 995 .enable_mask = BIT(0), 996 .hw.init = &(struct clk_init_data){ 997 .name = "cam_cc_icp_clk", 998 .parent_names = (const char *[]){ 999 "cam_cc_icp_clk_src", 1000 }, 1001 .num_parents = 1, 1002 .flags = CLK_SET_RATE_PARENT, 1003 .ops = &clk_branch2_ops, 1004 }, 1005 }, 1006 }; 1007 1008 static struct clk_branch cam_cc_icp_cti_clk = { 1009 .halt_reg = 0xb07c, 1010 .halt_check = BRANCH_HALT, 1011 .clkr = { 1012 .enable_reg = 0xb07c, 1013 .enable_mask = BIT(0), 1014 .hw.init = &(struct clk_init_data){ 1015 .name = "cam_cc_icp_cti_clk", 1016 .ops = &clk_branch2_ops, 1017 }, 1018 }, 1019 }; 1020 1021 static struct clk_branch cam_cc_icp_ts_clk = { 1022 .halt_reg = 0xb080, 1023 .halt_check = BRANCH_HALT, 1024 .clkr = { 1025 .enable_reg = 0xb080, 1026 .enable_mask = BIT(0), 1027 .hw.init = &(struct clk_init_data){ 1028 .name = "cam_cc_icp_ts_clk", 1029 .ops = &clk_branch2_ops, 1030 }, 1031 }, 1032 }; 1033 1034 static struct clk_branch cam_cc_ife_0_axi_clk = { 1035 .halt_reg = 0x907c, 1036 .halt_check = BRANCH_HALT, 1037 .clkr = { 1038 .enable_reg = 0x907c, 1039 .enable_mask = BIT(0), 1040 .hw.init = &(struct clk_init_data){ 1041 .name = "cam_cc_ife_0_axi_clk", 1042 .ops = &clk_branch2_ops, 1043 }, 1044 }, 1045 }; 1046 1047 static struct clk_branch cam_cc_ife_0_clk = { 1048 .halt_reg = 0x9024, 1049 .halt_check = BRANCH_HALT, 1050 .clkr = { 1051 .enable_reg = 0x9024, 1052 .enable_mask = BIT(0), 1053 .hw.init = &(struct clk_init_data){ 1054 .name = "cam_cc_ife_0_clk", 1055 .parent_names = (const char *[]){ 1056 "cam_cc_ife_0_clk_src", 1057 }, 1058 .num_parents = 1, 1059 .flags = CLK_SET_RATE_PARENT, 1060 .ops = &clk_branch2_ops, 1061 }, 1062 }, 1063 }; 1064 1065 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1066 .halt_reg = 0x9078, 1067 .halt_check = BRANCH_HALT, 1068 .clkr = { 1069 .enable_reg = 0x9078, 1070 .enable_mask = BIT(0), 1071 .hw.init = &(struct clk_init_data){ 1072 .name = "cam_cc_ife_0_cphy_rx_clk", 1073 .parent_names = (const char *[]){ 1074 "cam_cc_cphy_rx_clk_src", 1075 }, 1076 .num_parents = 1, 1077 .flags = CLK_SET_RATE_PARENT, 1078 .ops = &clk_branch2_ops, 1079 }, 1080 }, 1081 }; 1082 1083 static struct clk_branch cam_cc_ife_0_csid_clk = { 1084 .halt_reg = 0x9050, 1085 .halt_check = BRANCH_HALT, 1086 .clkr = { 1087 .enable_reg = 0x9050, 1088 .enable_mask = BIT(0), 1089 .hw.init = &(struct clk_init_data){ 1090 .name = "cam_cc_ife_0_csid_clk", 1091 .parent_names = (const char *[]){ 1092 "cam_cc_ife_0_csid_clk_src", 1093 }, 1094 .num_parents = 1, 1095 .flags = CLK_SET_RATE_PARENT, 1096 .ops = &clk_branch2_ops, 1097 }, 1098 }, 1099 }; 1100 1101 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1102 .halt_reg = 0x9034, 1103 .halt_check = BRANCH_HALT, 1104 .clkr = { 1105 .enable_reg = 0x9034, 1106 .enable_mask = BIT(0), 1107 .hw.init = &(struct clk_init_data){ 1108 .name = "cam_cc_ife_0_dsp_clk", 1109 .parent_names = (const char *[]){ 1110 "cam_cc_ife_0_clk_src", 1111 }, 1112 .num_parents = 1, 1113 .ops = &clk_branch2_ops, 1114 }, 1115 }, 1116 }; 1117 1118 static struct clk_branch cam_cc_ife_1_axi_clk = { 1119 .halt_reg = 0xa054, 1120 .halt_check = BRANCH_HALT, 1121 .clkr = { 1122 .enable_reg = 0xa054, 1123 .enable_mask = BIT(0), 1124 .hw.init = &(struct clk_init_data){ 1125 .name = "cam_cc_ife_1_axi_clk", 1126 .ops = &clk_branch2_ops, 1127 }, 1128 }, 1129 }; 1130 1131 static struct clk_branch cam_cc_ife_1_clk = { 1132 .halt_reg = 0xa024, 1133 .halt_check = BRANCH_HALT, 1134 .clkr = { 1135 .enable_reg = 0xa024, 1136 .enable_mask = BIT(0), 1137 .hw.init = &(struct clk_init_data){ 1138 .name = "cam_cc_ife_1_clk", 1139 .parent_names = (const char *[]){ 1140 "cam_cc_ife_1_clk_src", 1141 }, 1142 .num_parents = 1, 1143 .flags = CLK_SET_RATE_PARENT, 1144 .ops = &clk_branch2_ops, 1145 }, 1146 }, 1147 }; 1148 1149 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1150 .halt_reg = 0xa050, 1151 .halt_check = BRANCH_HALT, 1152 .clkr = { 1153 .enable_reg = 0xa050, 1154 .enable_mask = BIT(0), 1155 .hw.init = &(struct clk_init_data){ 1156 .name = "cam_cc_ife_1_cphy_rx_clk", 1157 .parent_names = (const char *[]){ 1158 "cam_cc_cphy_rx_clk_src", 1159 }, 1160 .num_parents = 1, 1161 .flags = CLK_SET_RATE_PARENT, 1162 .ops = &clk_branch2_ops, 1163 }, 1164 }, 1165 }; 1166 1167 static struct clk_branch cam_cc_ife_1_csid_clk = { 1168 .halt_reg = 0xa048, 1169 .halt_check = BRANCH_HALT, 1170 .clkr = { 1171 .enable_reg = 0xa048, 1172 .enable_mask = BIT(0), 1173 .hw.init = &(struct clk_init_data){ 1174 .name = "cam_cc_ife_1_csid_clk", 1175 .parent_names = (const char *[]){ 1176 "cam_cc_ife_1_csid_clk_src", 1177 }, 1178 .num_parents = 1, 1179 .flags = CLK_SET_RATE_PARENT, 1180 .ops = &clk_branch2_ops, 1181 }, 1182 }, 1183 }; 1184 1185 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1186 .halt_reg = 0xa02c, 1187 .halt_check = BRANCH_HALT, 1188 .clkr = { 1189 .enable_reg = 0xa02c, 1190 .enable_mask = BIT(0), 1191 .hw.init = &(struct clk_init_data){ 1192 .name = "cam_cc_ife_1_dsp_clk", 1193 .parent_names = (const char *[]){ 1194 "cam_cc_ife_1_clk_src", 1195 }, 1196 .num_parents = 1, 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200 }; 1201 1202 static struct clk_branch cam_cc_ife_lite_clk = { 1203 .halt_reg = 0xb01c, 1204 .halt_check = BRANCH_HALT, 1205 .clkr = { 1206 .enable_reg = 0xb01c, 1207 .enable_mask = BIT(0), 1208 .hw.init = &(struct clk_init_data){ 1209 .name = "cam_cc_ife_lite_clk", 1210 .parent_names = (const char *[]){ 1211 "cam_cc_ife_lite_clk_src", 1212 }, 1213 .num_parents = 1, 1214 .flags = CLK_SET_RATE_PARENT, 1215 .ops = &clk_branch2_ops, 1216 }, 1217 }, 1218 }; 1219 1220 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1221 .halt_reg = 0xb044, 1222 .halt_check = BRANCH_HALT, 1223 .clkr = { 1224 .enable_reg = 0xb044, 1225 .enable_mask = BIT(0), 1226 .hw.init = &(struct clk_init_data){ 1227 .name = "cam_cc_ife_lite_cphy_rx_clk", 1228 .parent_names = (const char *[]){ 1229 "cam_cc_cphy_rx_clk_src", 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1239 .halt_reg = 0xb03c, 1240 .halt_check = BRANCH_HALT, 1241 .clkr = { 1242 .enable_reg = 0xb03c, 1243 .enable_mask = BIT(0), 1244 .hw.init = &(struct clk_init_data){ 1245 .name = "cam_cc_ife_lite_csid_clk", 1246 .parent_names = (const char *[]){ 1247 "cam_cc_ife_lite_csid_clk_src", 1248 }, 1249 .num_parents = 1, 1250 .flags = CLK_SET_RATE_PARENT, 1251 .ops = &clk_branch2_ops, 1252 }, 1253 }, 1254 }; 1255 1256 static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1257 .halt_reg = 0x703c, 1258 .halt_check = BRANCH_HALT, 1259 .clkr = { 1260 .enable_reg = 0x703c, 1261 .enable_mask = BIT(0), 1262 .hw.init = &(struct clk_init_data){ 1263 .name = "cam_cc_ipe_0_ahb_clk", 1264 .parent_names = (const char *[]){ 1265 "cam_cc_slow_ahb_clk_src", 1266 }, 1267 .num_parents = 1, 1268 .flags = CLK_SET_RATE_PARENT, 1269 .ops = &clk_branch2_ops, 1270 }, 1271 }, 1272 }; 1273 1274 static struct clk_branch cam_cc_ipe_0_areg_clk = { 1275 .halt_reg = 0x7038, 1276 .halt_check = BRANCH_HALT, 1277 .clkr = { 1278 .enable_reg = 0x7038, 1279 .enable_mask = BIT(0), 1280 .hw.init = &(struct clk_init_data){ 1281 .name = "cam_cc_ipe_0_areg_clk", 1282 .parent_names = (const char *[]){ 1283 "cam_cc_fast_ahb_clk_src", 1284 }, 1285 .num_parents = 1, 1286 .flags = CLK_SET_RATE_PARENT, 1287 .ops = &clk_branch2_ops, 1288 }, 1289 }, 1290 }; 1291 1292 static struct clk_branch cam_cc_ipe_0_axi_clk = { 1293 .halt_reg = 0x7034, 1294 .halt_check = BRANCH_HALT, 1295 .clkr = { 1296 .enable_reg = 0x7034, 1297 .enable_mask = BIT(0), 1298 .hw.init = &(struct clk_init_data){ 1299 .name = "cam_cc_ipe_0_axi_clk", 1300 .ops = &clk_branch2_ops, 1301 }, 1302 }, 1303 }; 1304 1305 static struct clk_branch cam_cc_ipe_0_clk = { 1306 .halt_reg = 0x7024, 1307 .halt_check = BRANCH_HALT, 1308 .clkr = { 1309 .enable_reg = 0x7024, 1310 .enable_mask = BIT(0), 1311 .hw.init = &(struct clk_init_data){ 1312 .name = "cam_cc_ipe_0_clk", 1313 .parent_names = (const char *[]){ 1314 "cam_cc_ipe_0_clk_src", 1315 }, 1316 .num_parents = 1, 1317 .flags = CLK_SET_RATE_PARENT, 1318 .ops = &clk_branch2_ops, 1319 }, 1320 }, 1321 }; 1322 1323 static struct clk_branch cam_cc_ipe_1_ahb_clk = { 1324 .halt_reg = 0x803c, 1325 .halt_check = BRANCH_HALT, 1326 .clkr = { 1327 .enable_reg = 0x803c, 1328 .enable_mask = BIT(0), 1329 .hw.init = &(struct clk_init_data){ 1330 .name = "cam_cc_ipe_1_ahb_clk", 1331 .parent_names = (const char *[]){ 1332 "cam_cc_slow_ahb_clk_src", 1333 }, 1334 .num_parents = 1, 1335 .flags = CLK_SET_RATE_PARENT, 1336 .ops = &clk_branch2_ops, 1337 }, 1338 }, 1339 }; 1340 1341 static struct clk_branch cam_cc_ipe_1_areg_clk = { 1342 .halt_reg = 0x8038, 1343 .halt_check = BRANCH_HALT, 1344 .clkr = { 1345 .enable_reg = 0x8038, 1346 .enable_mask = BIT(0), 1347 .hw.init = &(struct clk_init_data){ 1348 .name = "cam_cc_ipe_1_areg_clk", 1349 .parent_names = (const char *[]){ 1350 "cam_cc_fast_ahb_clk_src", 1351 }, 1352 .num_parents = 1, 1353 .flags = CLK_SET_RATE_PARENT, 1354 .ops = &clk_branch2_ops, 1355 }, 1356 }, 1357 }; 1358 1359 static struct clk_branch cam_cc_ipe_1_axi_clk = { 1360 .halt_reg = 0x8034, 1361 .halt_check = BRANCH_HALT, 1362 .clkr = { 1363 .enable_reg = 0x8034, 1364 .enable_mask = BIT(0), 1365 .hw.init = &(struct clk_init_data){ 1366 .name = "cam_cc_ipe_1_axi_clk", 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch cam_cc_ipe_1_clk = { 1373 .halt_reg = 0x8024, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x8024, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "cam_cc_ipe_1_clk", 1380 .parent_names = (const char *[]){ 1381 "cam_cc_ipe_1_clk_src", 1382 }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch cam_cc_jpeg_clk = { 1391 .halt_reg = 0xb064, 1392 .halt_check = BRANCH_HALT, 1393 .clkr = { 1394 .enable_reg = 0xb064, 1395 .enable_mask = BIT(0), 1396 .hw.init = &(struct clk_init_data){ 1397 .name = "cam_cc_jpeg_clk", 1398 .parent_names = (const char *[]){ 1399 "cam_cc_jpeg_clk_src", 1400 }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch cam_cc_lrme_clk = { 1409 .halt_reg = 0xb110, 1410 .halt_check = BRANCH_HALT, 1411 .clkr = { 1412 .enable_reg = 0xb110, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(struct clk_init_data){ 1415 .name = "cam_cc_lrme_clk", 1416 .parent_names = (const char *[]){ 1417 "cam_cc_lrme_clk_src", 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch cam_cc_mclk0_clk = { 1427 .halt_reg = 0x401c, 1428 .halt_check = BRANCH_HALT, 1429 .clkr = { 1430 .enable_reg = 0x401c, 1431 .enable_mask = BIT(0), 1432 .hw.init = &(struct clk_init_data){ 1433 .name = "cam_cc_mclk0_clk", 1434 .parent_names = (const char *[]){ 1435 "cam_cc_mclk0_clk_src", 1436 }, 1437 .num_parents = 1, 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_branch cam_cc_mclk1_clk = { 1445 .halt_reg = 0x403c, 1446 .halt_check = BRANCH_HALT, 1447 .clkr = { 1448 .enable_reg = 0x403c, 1449 .enable_mask = BIT(0), 1450 .hw.init = &(struct clk_init_data){ 1451 .name = "cam_cc_mclk1_clk", 1452 .parent_names = (const char *[]){ 1453 "cam_cc_mclk1_clk_src", 1454 }, 1455 .num_parents = 1, 1456 .flags = CLK_SET_RATE_PARENT, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch cam_cc_mclk2_clk = { 1463 .halt_reg = 0x405c, 1464 .halt_check = BRANCH_HALT, 1465 .clkr = { 1466 .enable_reg = 0x405c, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(struct clk_init_data){ 1469 .name = "cam_cc_mclk2_clk", 1470 .parent_names = (const char *[]){ 1471 "cam_cc_mclk2_clk_src", 1472 }, 1473 .num_parents = 1, 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch cam_cc_mclk3_clk = { 1481 .halt_reg = 0x407c, 1482 .halt_check = BRANCH_HALT, 1483 .clkr = { 1484 .enable_reg = 0x407c, 1485 .enable_mask = BIT(0), 1486 .hw.init = &(struct clk_init_data){ 1487 .name = "cam_cc_mclk3_clk", 1488 .parent_names = (const char *[]){ 1489 "cam_cc_mclk3_clk_src", 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch cam_cc_soc_ahb_clk = { 1499 .halt_reg = 0xb13c, 1500 .halt_check = BRANCH_HALT, 1501 .clkr = { 1502 .enable_reg = 0xb13c, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "cam_cc_soc_ahb_clk", 1506 .ops = &clk_branch2_ops, 1507 }, 1508 }, 1509 }; 1510 1511 static struct clk_branch cam_cc_sys_tmr_clk = { 1512 .halt_reg = 0xb0a8, 1513 .halt_check = BRANCH_HALT, 1514 .clkr = { 1515 .enable_reg = 0xb0a8, 1516 .enable_mask = BIT(0), 1517 .hw.init = &(struct clk_init_data){ 1518 .name = "cam_cc_sys_tmr_clk", 1519 .ops = &clk_branch2_ops, 1520 }, 1521 }, 1522 }; 1523 1524 static struct gdsc bps_gdsc = { 1525 .gdscr = 0x6004, 1526 .pd = { 1527 .name = "bps_gdsc", 1528 }, 1529 .flags = HW_CTRL | POLL_CFG_GDSCR, 1530 .pwrsts = PWRSTS_OFF_ON, 1531 }; 1532 1533 static struct gdsc ipe_0_gdsc = { 1534 .gdscr = 0x7004, 1535 .pd = { 1536 .name = "ipe_0_gdsc", 1537 }, 1538 .flags = HW_CTRL | POLL_CFG_GDSCR, 1539 .pwrsts = PWRSTS_OFF_ON, 1540 }; 1541 1542 static struct gdsc ipe_1_gdsc = { 1543 .gdscr = 0x8004, 1544 .pd = { 1545 .name = "ipe_1_gdsc", 1546 }, 1547 .flags = HW_CTRL | POLL_CFG_GDSCR, 1548 .pwrsts = PWRSTS_OFF_ON, 1549 }; 1550 1551 static struct gdsc ife_0_gdsc = { 1552 .gdscr = 0x9004, 1553 .pd = { 1554 .name = "ife_0_gdsc", 1555 }, 1556 .flags = POLL_CFG_GDSCR, 1557 .pwrsts = PWRSTS_OFF_ON, 1558 }; 1559 1560 static struct gdsc ife_1_gdsc = { 1561 .gdscr = 0xa004, 1562 .pd = { 1563 .name = "ife_1_gdsc", 1564 }, 1565 .flags = POLL_CFG_GDSCR, 1566 .pwrsts = PWRSTS_OFF_ON, 1567 }; 1568 1569 static struct gdsc titan_top_gdsc = { 1570 .gdscr = 0xb134, 1571 .pd = { 1572 .name = "titan_top_gdsc", 1573 }, 1574 .flags = POLL_CFG_GDSCR, 1575 .pwrsts = PWRSTS_OFF_ON, 1576 }; 1577 1578 static struct clk_regmap *cam_cc_sdm845_clocks[] = { 1579 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1580 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1581 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 1582 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1583 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1584 [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr, 1585 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1586 [CAM_CC_CCI_CLK] = &cam_cc_cci_clk.clkr, 1587 [CAM_CC_CCI_CLK_SRC] = &cam_cc_cci_clk_src.clkr, 1588 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1589 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1590 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1591 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1592 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1593 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1594 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1595 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1596 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 1597 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 1598 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1599 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1600 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1601 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 1602 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1603 [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr, 1604 [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr, 1605 [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr, 1606 [CAM_CC_ICP_APB_CLK] = &cam_cc_icp_apb_clk.clkr, 1607 [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr, 1608 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1609 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1610 [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr, 1611 [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr, 1612 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 1613 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1614 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1615 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 1616 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 1617 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 1618 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 1619 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 1620 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1621 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1622 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 1623 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 1624 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 1625 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 1626 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1627 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1628 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1629 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1630 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1631 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 1632 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 1633 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 1634 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 1635 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 1636 [CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr, 1637 [CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr, 1638 [CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr, 1639 [CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr, 1640 [CAM_CC_IPE_1_CLK_SRC] = &cam_cc_ipe_1_clk_src.clkr, 1641 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 1642 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 1643 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 1644 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 1645 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1646 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1647 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1648 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1649 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1650 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1651 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1652 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1653 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1654 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 1655 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1656 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 1657 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1658 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, 1659 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1660 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 1661 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1662 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 1663 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 1664 }; 1665 1666 static struct gdsc *cam_cc_sdm845_gdscs[] = { 1667 [BPS_GDSC] = &bps_gdsc, 1668 [IPE_0_GDSC] = &ipe_0_gdsc, 1669 [IPE_1_GDSC] = &ipe_1_gdsc, 1670 [IFE_0_GDSC] = &ife_0_gdsc, 1671 [IFE_1_GDSC] = &ife_1_gdsc, 1672 [TITAN_TOP_GDSC] = &titan_top_gdsc, 1673 }; 1674 1675 static const struct regmap_config cam_cc_sdm845_regmap_config = { 1676 .reg_bits = 32, 1677 .reg_stride = 4, 1678 .val_bits = 32, 1679 .max_register = 0xd004, 1680 .fast_io = true, 1681 }; 1682 1683 static const struct qcom_cc_desc cam_cc_sdm845_desc = { 1684 .config = &cam_cc_sdm845_regmap_config, 1685 .clks = cam_cc_sdm845_clocks, 1686 .num_clks = ARRAY_SIZE(cam_cc_sdm845_clocks), 1687 .gdscs = cam_cc_sdm845_gdscs, 1688 .num_gdscs = ARRAY_SIZE(cam_cc_sdm845_gdscs), 1689 }; 1690 1691 static const struct of_device_id cam_cc_sdm845_match_table[] = { 1692 { .compatible = "qcom,sdm845-camcc" }, 1693 { } 1694 }; 1695 MODULE_DEVICE_TABLE(of, cam_cc_sdm845_match_table); 1696 1697 static int cam_cc_sdm845_probe(struct platform_device *pdev) 1698 { 1699 struct regmap *regmap; 1700 struct alpha_pll_config cam_cc_pll_config = { }; 1701 1702 regmap = qcom_cc_map(pdev, &cam_cc_sdm845_desc); 1703 if (IS_ERR(regmap)) 1704 return PTR_ERR(regmap); 1705 1706 cam_cc_pll_config.l = 0x1f; 1707 cam_cc_pll_config.alpha = 0x4000; 1708 clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll_config); 1709 1710 cam_cc_pll_config.l = 0x2a; 1711 cam_cc_pll_config.alpha = 0x1556; 1712 clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll_config); 1713 1714 cam_cc_pll_config.l = 0x32; 1715 cam_cc_pll_config.alpha = 0x0; 1716 clk_fabia_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll_config); 1717 1718 cam_cc_pll_config.l = 0x14; 1719 clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config); 1720 1721 return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap); 1722 } 1723 1724 static struct platform_driver cam_cc_sdm845_driver = { 1725 .probe = cam_cc_sdm845_probe, 1726 .driver = { 1727 .name = "sdm845-camcc", 1728 .of_match_table = cam_cc_sdm845_match_table, 1729 }, 1730 }; 1731 1732 static int __init cam_cc_sdm845_init(void) 1733 { 1734 return platform_driver_register(&cam_cc_sdm845_driver); 1735 } 1736 subsys_initcall(cam_cc_sdm845_init); 1737 1738 static void __exit cam_cc_sdm845_exit(void) 1739 { 1740 platform_driver_unregister(&cam_cc_sdm845_driver); 1741 } 1742 module_exit(cam_cc_sdm845_exit); 1743 1744 MODULE_DESCRIPTION("QTI CAM_CC SDM845 Driver"); 1745 MODULE_LICENSE("GPL v2"); 1746