1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_device.h> 11 #include <linux/pm_clock.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,camcc-sc7180.h> 16 17 #include "clk-alpha-pll.h" 18 #include "clk-branch.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 P_BI_TCXO, 27 P_CAM_CC_PLL0_OUT_EVEN, 28 P_CAM_CC_PLL1_OUT_EVEN, 29 P_CAM_CC_PLL2_OUT_AUX, 30 P_CAM_CC_PLL2_OUT_EARLY, 31 P_CAM_CC_PLL3_OUT_MAIN, 32 }; 33 34 static const struct pll_vco agera_vco[] = { 35 { 600000000, 3300000000UL, 0 }, 36 }; 37 38 static const struct pll_vco fabia_vco[] = { 39 { 249600000, 2000000000UL, 0 }, 40 }; 41 42 /* 600MHz configuration */ 43 static const struct alpha_pll_config cam_cc_pll0_config = { 44 .l = 0x1f, 45 .alpha = 0x4000, 46 .config_ctl_val = 0x20485699, 47 .config_ctl_hi_val = 0x00002067, 48 .test_ctl_val = 0x40000000, 49 .user_ctl_hi_val = 0x00004805, 50 .user_ctl_val = 0x00000001, 51 }; 52 53 static struct clk_alpha_pll cam_cc_pll0 = { 54 .offset = 0x0, 55 .vco_table = fabia_vco, 56 .num_vco = ARRAY_SIZE(fabia_vco), 57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 58 .clkr = { 59 .hw.init = &(struct clk_init_data){ 60 .name = "cam_cc_pll0", 61 .parent_data = &(const struct clk_parent_data){ 62 .fw_name = "bi_tcxo", 63 }, 64 .num_parents = 1, 65 .ops = &clk_alpha_pll_fabia_ops, 66 }, 67 }, 68 }; 69 70 /* 860MHz configuration */ 71 static const struct alpha_pll_config cam_cc_pll1_config = { 72 .l = 0x2a, 73 .alpha = 0x1555, 74 .config_ctl_val = 0x20485699, 75 .config_ctl_hi_val = 0x00002067, 76 .test_ctl_val = 0x40000000, 77 .user_ctl_hi_val = 0x00004805, 78 }; 79 80 static struct clk_alpha_pll cam_cc_pll1 = { 81 .offset = 0x1000, 82 .vco_table = fabia_vco, 83 .num_vco = ARRAY_SIZE(fabia_vco), 84 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 85 .clkr = { 86 .hw.init = &(struct clk_init_data){ 87 .name = "cam_cc_pll1", 88 .parent_data = &(const struct clk_parent_data){ 89 .fw_name = "bi_tcxo", 90 }, 91 .num_parents = 1, 92 .ops = &clk_alpha_pll_fabia_ops, 93 }, 94 }, 95 }; 96 97 /* 1920MHz configuration */ 98 static const struct alpha_pll_config cam_cc_pll2_config = { 99 .l = 0x64, 100 .config_ctl_val = 0x20000800, 101 .config_ctl_hi_val = 0x400003D2, 102 .test_ctl_val = 0x04000400, 103 .test_ctl_hi_val = 0x00004000, 104 .user_ctl_val = 0x0000030F, 105 }; 106 107 static struct clk_alpha_pll cam_cc_pll2 = { 108 .offset = 0x2000, 109 .vco_table = agera_vco, 110 .num_vco = ARRAY_SIZE(agera_vco), 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 112 .clkr = { 113 .hw.init = &(struct clk_init_data){ 114 .name = "cam_cc_pll2", 115 .parent_data = &(const struct clk_parent_data){ 116 .fw_name = "bi_tcxo", 117 }, 118 .num_parents = 1, 119 .ops = &clk_alpha_pll_agera_ops, 120 }, 121 }, 122 }; 123 124 static struct clk_fixed_factor cam_cc_pll2_out_early = { 125 .mult = 1, 126 .div = 2, 127 .hw.init = &(struct clk_init_data){ 128 .name = "cam_cc_pll2_out_early", 129 .parent_names = (const char *[]){ "cam_cc_pll2" }, 130 .num_parents = 1, 131 .ops = &clk_fixed_factor_ops, 132 }, 133 }; 134 135 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = { 136 { 0x3, 4 }, 137 { } 138 }; 139 140 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { 141 .offset = 0x2000, 142 .post_div_shift = 8, 143 .post_div_table = post_div_table_cam_cc_pll2_out_aux, 144 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux), 145 .width = 2, 146 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 147 .clkr.hw.init = &(struct clk_init_data){ 148 .name = "cam_cc_pll2_out_aux", 149 .parent_data = &(const struct clk_parent_data){ 150 .hw = &cam_cc_pll2.clkr.hw, 151 }, 152 .num_parents = 1, 153 .flags = CLK_SET_RATE_PARENT, 154 .ops = &clk_alpha_pll_postdiv_ops, 155 }, 156 }; 157 158 /* 1080MHz configuration */ 159 static const struct alpha_pll_config cam_cc_pll3_config = { 160 .l = 0x38, 161 .alpha = 0x4000, 162 .config_ctl_val = 0x20485699, 163 .config_ctl_hi_val = 0x00002067, 164 .test_ctl_val = 0x40000000, 165 .user_ctl_hi_val = 0x00004805, 166 }; 167 168 static struct clk_alpha_pll cam_cc_pll3 = { 169 .offset = 0x3000, 170 .vco_table = fabia_vco, 171 .num_vco = ARRAY_SIZE(fabia_vco), 172 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 173 .clkr = { 174 .hw.init = &(struct clk_init_data){ 175 .name = "cam_cc_pll3", 176 .parent_data = &(const struct clk_parent_data){ 177 .fw_name = "bi_tcxo", 178 }, 179 .num_parents = 1, 180 .ops = &clk_alpha_pll_fabia_ops, 181 }, 182 }, 183 }; 184 185 static const struct parent_map cam_cc_parent_map_0[] = { 186 { P_BI_TCXO, 0 }, 187 { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 188 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 189 }; 190 191 static const struct clk_parent_data cam_cc_parent_data_0[] = { 192 { .fw_name = "bi_tcxo" }, 193 { .hw = &cam_cc_pll1.clkr.hw }, 194 { .hw = &cam_cc_pll0.clkr.hw }, 195 }; 196 197 static const struct parent_map cam_cc_parent_map_1[] = { 198 { P_BI_TCXO, 0 }, 199 { P_CAM_CC_PLL2_OUT_AUX, 1 }, 200 }; 201 202 static const struct clk_parent_data cam_cc_parent_data_1[] = { 203 { .fw_name = "bi_tcxo" }, 204 { .hw = &cam_cc_pll2_out_aux.clkr.hw }, 205 }; 206 207 static const struct parent_map cam_cc_parent_map_2[] = { 208 { P_BI_TCXO, 0 }, 209 { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 210 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 211 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 212 }; 213 214 static const struct clk_parent_data cam_cc_parent_data_2[] = { 215 { .fw_name = "bi_tcxo" }, 216 { .hw = &cam_cc_pll2_out_early.hw }, 217 { .hw = &cam_cc_pll3.clkr.hw }, 218 { .hw = &cam_cc_pll0.clkr.hw }, 219 }; 220 221 static const struct parent_map cam_cc_parent_map_3[] = { 222 { P_BI_TCXO, 0 }, 223 { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 224 { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 225 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 226 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 227 }; 228 229 static const struct clk_parent_data cam_cc_parent_data_3[] = { 230 { .fw_name = "bi_tcxo" }, 231 { .hw = &cam_cc_pll1.clkr.hw }, 232 { .hw = &cam_cc_pll2_out_early.hw }, 233 { .hw = &cam_cc_pll3.clkr.hw }, 234 { .hw = &cam_cc_pll0.clkr.hw }, 235 }; 236 237 static const struct parent_map cam_cc_parent_map_4[] = { 238 { P_BI_TCXO, 0 }, 239 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 240 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 241 }; 242 243 static const struct clk_parent_data cam_cc_parent_data_4[] = { 244 { .fw_name = "bi_tcxo" }, 245 { .hw = &cam_cc_pll3.clkr.hw }, 246 { .hw = &cam_cc_pll0.clkr.hw }, 247 }; 248 249 static const struct parent_map cam_cc_parent_map_5[] = { 250 { P_BI_TCXO, 0 }, 251 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 252 }; 253 254 static const struct clk_parent_data cam_cc_parent_data_5[] = { 255 { .fw_name = "bi_tcxo" }, 256 { .hw = &cam_cc_pll0.clkr.hw }, 257 }; 258 259 static const struct parent_map cam_cc_parent_map_6[] = { 260 { P_BI_TCXO, 0 }, 261 { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 262 { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 263 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 264 }; 265 266 static const struct clk_parent_data cam_cc_parent_data_6[] = { 267 { .fw_name = "bi_tcxo" }, 268 { .hw = &cam_cc_pll1.clkr.hw }, 269 { .hw = &cam_cc_pll3.clkr.hw }, 270 { .hw = &cam_cc_pll0.clkr.hw }, 271 }; 272 273 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 274 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 275 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 276 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 277 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 278 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 279 { } 280 }; 281 282 static struct clk_rcg2 cam_cc_bps_clk_src = { 283 .cmd_rcgr = 0x6010, 284 .mnd_width = 0, 285 .hid_width = 5, 286 .parent_map = cam_cc_parent_map_2, 287 .freq_tbl = ftbl_cam_cc_bps_clk_src, 288 .clkr.hw.init = &(struct clk_init_data){ 289 .name = "cam_cc_bps_clk_src", 290 .parent_data = cam_cc_parent_data_2, 291 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 292 .ops = &clk_rcg2_shared_ops, 293 }, 294 }; 295 296 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 297 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 298 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 299 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 300 { } 301 }; 302 303 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 304 .cmd_rcgr = 0xb0d8, 305 .mnd_width = 8, 306 .hid_width = 5, 307 .parent_map = cam_cc_parent_map_5, 308 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 309 .clkr.hw.init = &(struct clk_init_data){ 310 .name = "cam_cc_cci_0_clk_src", 311 .parent_data = cam_cc_parent_data_5, 312 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 313 .ops = &clk_rcg2_shared_ops, 314 }, 315 }; 316 317 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 318 .cmd_rcgr = 0xb14c, 319 .mnd_width = 8, 320 .hid_width = 5, 321 .parent_map = cam_cc_parent_map_5, 322 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 323 .clkr.hw.init = &(struct clk_init_data){ 324 .name = "cam_cc_cci_1_clk_src", 325 .parent_data = cam_cc_parent_data_5, 326 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 327 .ops = &clk_rcg2_shared_ops, 328 }, 329 }; 330 331 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 332 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 333 F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), 334 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 335 { } 336 }; 337 338 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 339 .cmd_rcgr = 0x9064, 340 .mnd_width = 0, 341 .hid_width = 5, 342 .parent_map = cam_cc_parent_map_3, 343 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 344 .clkr.hw.init = &(struct clk_init_data){ 345 .name = "cam_cc_cphy_rx_clk_src", 346 .parent_data = cam_cc_parent_data_3, 347 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 348 .ops = &clk_rcg2_shared_ops, 349 }, 350 }; 351 352 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 353 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 354 { } 355 }; 356 357 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 358 .cmd_rcgr = 0x5004, 359 .mnd_width = 0, 360 .hid_width = 5, 361 .parent_map = cam_cc_parent_map_0, 362 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 363 .clkr.hw.init = &(struct clk_init_data){ 364 .name = "cam_cc_csi0phytimer_clk_src", 365 .parent_data = cam_cc_parent_data_0, 366 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 367 .ops = &clk_rcg2_shared_ops, 368 }, 369 }; 370 371 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 372 .cmd_rcgr = 0x5028, 373 .mnd_width = 0, 374 .hid_width = 5, 375 .parent_map = cam_cc_parent_map_0, 376 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 377 .clkr.hw.init = &(struct clk_init_data){ 378 .name = "cam_cc_csi1phytimer_clk_src", 379 .parent_data = cam_cc_parent_data_0, 380 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 381 .ops = &clk_rcg2_shared_ops, 382 }, 383 }; 384 385 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 386 .cmd_rcgr = 0x504c, 387 .mnd_width = 0, 388 .hid_width = 5, 389 .parent_map = cam_cc_parent_map_0, 390 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 391 .clkr.hw.init = &(struct clk_init_data){ 392 .name = "cam_cc_csi2phytimer_clk_src", 393 .parent_data = cam_cc_parent_data_0, 394 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 395 .ops = &clk_rcg2_shared_ops, 396 }, 397 }; 398 399 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 400 .cmd_rcgr = 0x5070, 401 .mnd_width = 0, 402 .hid_width = 5, 403 .parent_map = cam_cc_parent_map_0, 404 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 405 .clkr.hw.init = &(struct clk_init_data){ 406 .name = "cam_cc_csi3phytimer_clk_src", 407 .parent_data = cam_cc_parent_data_0, 408 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 409 .ops = &clk_rcg2_shared_ops, 410 }, 411 }; 412 413 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 414 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 415 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 416 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 417 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 418 { } 419 }; 420 421 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 422 .cmd_rcgr = 0x603c, 423 .mnd_width = 0, 424 .hid_width = 5, 425 .parent_map = cam_cc_parent_map_0, 426 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 427 .clkr.hw.init = &(struct clk_init_data){ 428 .name = "cam_cc_fast_ahb_clk_src", 429 .parent_data = cam_cc_parent_data_0, 430 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 431 .ops = &clk_rcg2_shared_ops, 432 }, 433 }; 434 435 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 436 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 437 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 438 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 439 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 440 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 441 { } 442 }; 443 444 static struct clk_rcg2 cam_cc_icp_clk_src = { 445 .cmd_rcgr = 0xb088, 446 .mnd_width = 0, 447 .hid_width = 5, 448 .parent_map = cam_cc_parent_map_2, 449 .freq_tbl = ftbl_cam_cc_icp_clk_src, 450 .clkr.hw.init = &(struct clk_init_data){ 451 .name = "cam_cc_icp_clk_src", 452 .parent_data = cam_cc_parent_data_2, 453 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 454 .ops = &clk_rcg2_shared_ops, 455 }, 456 }; 457 458 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 459 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 460 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 461 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 462 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 463 { } 464 }; 465 466 static struct clk_rcg2 cam_cc_ife_0_clk_src = { 467 .cmd_rcgr = 0x9010, 468 .mnd_width = 0, 469 .hid_width = 5, 470 .parent_map = cam_cc_parent_map_4, 471 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 472 .clkr.hw.init = &(struct clk_init_data){ 473 .name = "cam_cc_ife_0_clk_src", 474 .parent_data = cam_cc_parent_data_4, 475 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 476 .ops = &clk_rcg2_shared_ops, 477 }, 478 }; 479 480 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 481 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 482 F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), 483 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 484 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 485 { } 486 }; 487 488 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 489 .cmd_rcgr = 0x903c, 490 .mnd_width = 0, 491 .hid_width = 5, 492 .parent_map = cam_cc_parent_map_3, 493 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 494 .clkr.hw.init = &(struct clk_init_data){ 495 .name = "cam_cc_ife_0_csid_clk_src", 496 .parent_data = cam_cc_parent_data_3, 497 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 498 .ops = &clk_rcg2_shared_ops, 499 }, 500 }; 501 502 static struct clk_rcg2 cam_cc_ife_1_clk_src = { 503 .cmd_rcgr = 0xa010, 504 .mnd_width = 0, 505 .hid_width = 5, 506 .parent_map = cam_cc_parent_map_4, 507 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 508 .clkr.hw.init = &(struct clk_init_data){ 509 .name = "cam_cc_ife_1_clk_src", 510 .parent_data = cam_cc_parent_data_4, 511 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 512 .ops = &clk_rcg2_shared_ops, 513 }, 514 }; 515 516 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 517 .cmd_rcgr = 0xa034, 518 .mnd_width = 0, 519 .hid_width = 5, 520 .parent_map = cam_cc_parent_map_3, 521 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 522 .clkr.hw.init = &(struct clk_init_data){ 523 .name = "cam_cc_ife_1_csid_clk_src", 524 .parent_data = cam_cc_parent_data_3, 525 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 526 .ops = &clk_rcg2_shared_ops, 527 }, 528 }; 529 530 static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 531 .cmd_rcgr = 0xb004, 532 .mnd_width = 0, 533 .hid_width = 5, 534 .parent_map = cam_cc_parent_map_4, 535 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 536 .clkr.hw.init = &(struct clk_init_data){ 537 .name = "cam_cc_ife_lite_clk_src", 538 .parent_data = cam_cc_parent_data_4, 539 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 540 .flags = CLK_SET_RATE_PARENT, 541 .ops = &clk_rcg2_shared_ops, 542 }, 543 }; 544 545 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 546 .cmd_rcgr = 0xb024, 547 .mnd_width = 0, 548 .hid_width = 5, 549 .parent_map = cam_cc_parent_map_3, 550 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 551 .clkr.hw.init = &(struct clk_init_data){ 552 .name = "cam_cc_ife_lite_csid_clk_src", 553 .parent_data = cam_cc_parent_data_3, 554 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 555 .ops = &clk_rcg2_shared_ops, 556 }, 557 }; 558 559 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 560 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 561 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 562 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 563 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 564 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 565 { } 566 }; 567 568 static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 569 .cmd_rcgr = 0x7010, 570 .mnd_width = 0, 571 .hid_width = 5, 572 .parent_map = cam_cc_parent_map_2, 573 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 574 .clkr.hw.init = &(struct clk_init_data){ 575 .name = "cam_cc_ipe_0_clk_src", 576 .parent_data = cam_cc_parent_data_2, 577 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 578 .ops = &clk_rcg2_shared_ops, 579 }, 580 }; 581 582 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 583 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0), 584 F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0), 585 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 586 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 587 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 588 { } 589 }; 590 591 static struct clk_rcg2 cam_cc_jpeg_clk_src = { 592 .cmd_rcgr = 0xb04c, 593 .mnd_width = 0, 594 .hid_width = 5, 595 .parent_map = cam_cc_parent_map_2, 596 .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 597 .clkr.hw.init = &(struct clk_init_data){ 598 .name = "cam_cc_jpeg_clk_src", 599 .parent_data = cam_cc_parent_data_2, 600 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 601 .ops = &clk_rcg2_shared_ops, 602 }, 603 }; 604 605 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 606 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 607 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 608 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 609 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 610 { } 611 }; 612 613 static struct clk_rcg2 cam_cc_lrme_clk_src = { 614 .cmd_rcgr = 0xb0f8, 615 .mnd_width = 0, 616 .hid_width = 5, 617 .parent_map = cam_cc_parent_map_6, 618 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 619 .clkr.hw.init = &(struct clk_init_data){ 620 .name = "cam_cc_lrme_clk_src", 621 .parent_data = cam_cc_parent_data_6, 622 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 623 .ops = &clk_rcg2_shared_ops, 624 }, 625 }; 626 627 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 628 F(19200000, P_BI_TCXO, 1, 0, 0), 629 F(24000000, P_CAM_CC_PLL2_OUT_AUX, 10, 1, 2), 630 F(64000000, P_CAM_CC_PLL2_OUT_AUX, 7.5, 0, 0), 631 { } 632 }; 633 634 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 635 .cmd_rcgr = 0x4004, 636 .mnd_width = 8, 637 .hid_width = 5, 638 .parent_map = cam_cc_parent_map_1, 639 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 640 .clkr.hw.init = &(struct clk_init_data){ 641 .name = "cam_cc_mclk0_clk_src", 642 .parent_data = cam_cc_parent_data_1, 643 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 644 .ops = &clk_rcg2_shared_ops, 645 }, 646 }; 647 648 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 649 .cmd_rcgr = 0x4024, 650 .mnd_width = 8, 651 .hid_width = 5, 652 .parent_map = cam_cc_parent_map_1, 653 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 654 .clkr.hw.init = &(struct clk_init_data){ 655 .name = "cam_cc_mclk1_clk_src", 656 .parent_data = cam_cc_parent_data_1, 657 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 658 .ops = &clk_rcg2_shared_ops, 659 }, 660 }; 661 662 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 663 .cmd_rcgr = 0x4044, 664 .mnd_width = 8, 665 .hid_width = 5, 666 .parent_map = cam_cc_parent_map_1, 667 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 668 .clkr.hw.init = &(struct clk_init_data){ 669 .name = "cam_cc_mclk2_clk_src", 670 .parent_data = cam_cc_parent_data_1, 671 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 672 .ops = &clk_rcg2_shared_ops, 673 }, 674 }; 675 676 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 677 .cmd_rcgr = 0x4064, 678 .mnd_width = 8, 679 .hid_width = 5, 680 .parent_map = cam_cc_parent_map_1, 681 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 682 .clkr.hw.init = &(struct clk_init_data){ 683 .name = "cam_cc_mclk3_clk_src", 684 .parent_data = cam_cc_parent_data_1, 685 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 686 .ops = &clk_rcg2_shared_ops, 687 }, 688 }; 689 690 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 691 .cmd_rcgr = 0x4084, 692 .mnd_width = 8, 693 .hid_width = 5, 694 .parent_map = cam_cc_parent_map_1, 695 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 696 .clkr.hw.init = &(struct clk_init_data){ 697 .name = "cam_cc_mclk4_clk_src", 698 .parent_data = cam_cc_parent_data_1, 699 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 700 .ops = &clk_rcg2_shared_ops, 701 }, 702 }; 703 704 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 705 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 706 { } 707 }; 708 709 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 710 .cmd_rcgr = 0x6058, 711 .mnd_width = 0, 712 .hid_width = 5, 713 .parent_map = cam_cc_parent_map_0, 714 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 715 .clkr.hw.init = &(struct clk_init_data){ 716 .name = "cam_cc_slow_ahb_clk_src", 717 .parent_data = cam_cc_parent_data_0, 718 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 719 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 720 .ops = &clk_rcg2_shared_ops, 721 }, 722 }; 723 724 static struct clk_branch cam_cc_bps_ahb_clk = { 725 .halt_reg = 0x6070, 726 .halt_check = BRANCH_HALT, 727 .clkr = { 728 .enable_reg = 0x6070, 729 .enable_mask = BIT(0), 730 .hw.init = &(struct clk_init_data){ 731 .name = "cam_cc_bps_ahb_clk", 732 .parent_data = &(const struct clk_parent_data){ 733 .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 734 }, 735 .num_parents = 1, 736 .flags = CLK_SET_RATE_PARENT, 737 .ops = &clk_branch2_ops, 738 }, 739 }, 740 }; 741 742 static struct clk_branch cam_cc_bps_areg_clk = { 743 .halt_reg = 0x6054, 744 .halt_check = BRANCH_HALT, 745 .clkr = { 746 .enable_reg = 0x6054, 747 .enable_mask = BIT(0), 748 .hw.init = &(struct clk_init_data){ 749 .name = "cam_cc_bps_areg_clk", 750 .parent_data = &(const struct clk_parent_data){ 751 .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, 752 }, 753 .num_parents = 1, 754 .flags = CLK_SET_RATE_PARENT, 755 .ops = &clk_branch2_ops, 756 }, 757 }, 758 }; 759 760 static struct clk_branch cam_cc_bps_axi_clk = { 761 .halt_reg = 0x6038, 762 .halt_check = BRANCH_HALT, 763 .clkr = { 764 .enable_reg = 0x6038, 765 .enable_mask = BIT(0), 766 .hw.init = &(struct clk_init_data){ 767 .name = "cam_cc_bps_axi_clk", 768 .ops = &clk_branch2_ops, 769 }, 770 }, 771 }; 772 773 static struct clk_branch cam_cc_bps_clk = { 774 .halt_reg = 0x6028, 775 .halt_check = BRANCH_HALT, 776 .clkr = { 777 .enable_reg = 0x6028, 778 .enable_mask = BIT(0), 779 .hw.init = &(struct clk_init_data){ 780 .name = "cam_cc_bps_clk", 781 .parent_data = &(const struct clk_parent_data){ 782 .hw = &cam_cc_bps_clk_src.clkr.hw, 783 }, 784 .num_parents = 1, 785 .flags = CLK_SET_RATE_PARENT, 786 .ops = &clk_branch2_ops, 787 }, 788 }, 789 }; 790 791 static struct clk_branch cam_cc_camnoc_axi_clk = { 792 .halt_reg = 0xb124, 793 .halt_check = BRANCH_HALT, 794 .clkr = { 795 .enable_reg = 0xb124, 796 .enable_mask = BIT(0), 797 .hw.init = &(struct clk_init_data){ 798 .name = "cam_cc_camnoc_axi_clk", 799 .ops = &clk_branch2_ops, 800 }, 801 }, 802 }; 803 804 static struct clk_branch cam_cc_cci_0_clk = { 805 .halt_reg = 0xb0f0, 806 .halt_check = BRANCH_HALT, 807 .clkr = { 808 .enable_reg = 0xb0f0, 809 .enable_mask = BIT(0), 810 .hw.init = &(struct clk_init_data){ 811 .name = "cam_cc_cci_0_clk", 812 .parent_data = &(const struct clk_parent_data){ 813 .hw = &cam_cc_cci_0_clk_src.clkr.hw, 814 }, 815 .num_parents = 1, 816 .flags = CLK_SET_RATE_PARENT, 817 .ops = &clk_branch2_ops, 818 }, 819 }, 820 }; 821 822 static struct clk_branch cam_cc_cci_1_clk = { 823 .halt_reg = 0xb164, 824 .halt_check = BRANCH_HALT, 825 .clkr = { 826 .enable_reg = 0xb164, 827 .enable_mask = BIT(0), 828 .hw.init = &(struct clk_init_data){ 829 .name = "cam_cc_cci_1_clk", 830 .parent_data = &(const struct clk_parent_data){ 831 .hw = &cam_cc_cci_1_clk_src.clkr.hw, 832 }, 833 .num_parents = 1, 834 .flags = CLK_SET_RATE_PARENT, 835 .ops = &clk_branch2_ops, 836 }, 837 }, 838 }; 839 840 static struct clk_branch cam_cc_core_ahb_clk = { 841 .halt_reg = 0xb144, 842 .halt_check = BRANCH_HALT_DELAY, 843 .clkr = { 844 .enable_reg = 0xb144, 845 .enable_mask = BIT(0), 846 .hw.init = &(struct clk_init_data){ 847 .name = "cam_cc_core_ahb_clk", 848 .parent_data = &(const struct clk_parent_data){ 849 .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 850 }, 851 .num_parents = 1, 852 .flags = CLK_SET_RATE_PARENT, 853 .ops = &clk_branch2_ops, 854 }, 855 }, 856 }; 857 858 static struct clk_branch cam_cc_cpas_ahb_clk = { 859 .halt_reg = 0xb11c, 860 .halt_check = BRANCH_HALT, 861 .clkr = { 862 .enable_reg = 0xb11c, 863 .enable_mask = BIT(0), 864 .hw.init = &(struct clk_init_data){ 865 .name = "cam_cc_cpas_ahb_clk", 866 .parent_data = &(const struct clk_parent_data){ 867 .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 868 }, 869 .num_parents = 1, 870 .flags = CLK_SET_RATE_PARENT, 871 .ops = &clk_branch2_ops, 872 }, 873 }, 874 }; 875 876 static struct clk_branch cam_cc_csi0phytimer_clk = { 877 .halt_reg = 0x501c, 878 .halt_check = BRANCH_HALT, 879 .clkr = { 880 .enable_reg = 0x501c, 881 .enable_mask = BIT(0), 882 .hw.init = &(struct clk_init_data){ 883 .name = "cam_cc_csi0phytimer_clk", 884 .parent_data = &(const struct clk_parent_data){ 885 .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, 886 }, 887 .num_parents = 1, 888 .flags = CLK_SET_RATE_PARENT, 889 .ops = &clk_branch2_ops, 890 }, 891 }, 892 }; 893 894 static struct clk_branch cam_cc_csi1phytimer_clk = { 895 .halt_reg = 0x5040, 896 .halt_check = BRANCH_HALT, 897 .clkr = { 898 .enable_reg = 0x5040, 899 .enable_mask = BIT(0), 900 .hw.init = &(struct clk_init_data){ 901 .name = "cam_cc_csi1phytimer_clk", 902 .parent_data = &(const struct clk_parent_data){ 903 .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, 904 }, 905 .num_parents = 1, 906 .flags = CLK_SET_RATE_PARENT, 907 .ops = &clk_branch2_ops, 908 }, 909 }, 910 }; 911 912 static struct clk_branch cam_cc_csi2phytimer_clk = { 913 .halt_reg = 0x5064, 914 .halt_check = BRANCH_HALT, 915 .clkr = { 916 .enable_reg = 0x5064, 917 .enable_mask = BIT(0), 918 .hw.init = &(struct clk_init_data){ 919 .name = "cam_cc_csi2phytimer_clk", 920 .parent_data = &(const struct clk_parent_data){ 921 .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, 922 }, 923 .num_parents = 1, 924 .flags = CLK_SET_RATE_PARENT, 925 .ops = &clk_branch2_ops, 926 }, 927 }, 928 }; 929 930 static struct clk_branch cam_cc_csi3phytimer_clk = { 931 .halt_reg = 0x5088, 932 .halt_check = BRANCH_HALT, 933 .clkr = { 934 .enable_reg = 0x5088, 935 .enable_mask = BIT(0), 936 .hw.init = &(struct clk_init_data){ 937 .name = "cam_cc_csi3phytimer_clk", 938 .parent_data = &(const struct clk_parent_data){ 939 .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, 940 }, 941 .num_parents = 1, 942 .flags = CLK_SET_RATE_PARENT, 943 .ops = &clk_branch2_ops, 944 }, 945 }, 946 }; 947 948 static struct clk_branch cam_cc_csiphy0_clk = { 949 .halt_reg = 0x5020, 950 .halt_check = BRANCH_HALT, 951 .clkr = { 952 .enable_reg = 0x5020, 953 .enable_mask = BIT(0), 954 .hw.init = &(struct clk_init_data){ 955 .name = "cam_cc_csiphy0_clk", 956 .parent_data = &(const struct clk_parent_data){ 957 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 958 }, 959 .num_parents = 1, 960 .flags = CLK_SET_RATE_PARENT, 961 .ops = &clk_branch2_ops, 962 }, 963 }, 964 }; 965 966 static struct clk_branch cam_cc_csiphy1_clk = { 967 .halt_reg = 0x5044, 968 .halt_check = BRANCH_HALT, 969 .clkr = { 970 .enable_reg = 0x5044, 971 .enable_mask = BIT(0), 972 .hw.init = &(struct clk_init_data){ 973 .name = "cam_cc_csiphy1_clk", 974 .parent_data = &(const struct clk_parent_data){ 975 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 976 }, 977 .num_parents = 1, 978 .flags = CLK_SET_RATE_PARENT, 979 .ops = &clk_branch2_ops, 980 }, 981 }, 982 }; 983 984 static struct clk_branch cam_cc_csiphy2_clk = { 985 .halt_reg = 0x5068, 986 .halt_check = BRANCH_HALT, 987 .clkr = { 988 .enable_reg = 0x5068, 989 .enable_mask = BIT(0), 990 .hw.init = &(struct clk_init_data){ 991 .name = "cam_cc_csiphy2_clk", 992 .parent_data = &(const struct clk_parent_data){ 993 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 994 }, 995 .num_parents = 1, 996 .flags = CLK_SET_RATE_PARENT, 997 .ops = &clk_branch2_ops, 998 }, 999 }, 1000 }; 1001 1002 static struct clk_branch cam_cc_csiphy3_clk = { 1003 .halt_reg = 0x508c, 1004 .halt_check = BRANCH_HALT, 1005 .clkr = { 1006 .enable_reg = 0x508c, 1007 .enable_mask = BIT(0), 1008 .hw.init = &(struct clk_init_data){ 1009 .name = "cam_cc_csiphy3_clk", 1010 .parent_data = &(const struct clk_parent_data){ 1011 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 1012 }, 1013 .num_parents = 1, 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_branch2_ops, 1016 }, 1017 }, 1018 }; 1019 1020 static struct clk_branch cam_cc_icp_clk = { 1021 .halt_reg = 0xb0a0, 1022 .halt_check = BRANCH_HALT, 1023 .clkr = { 1024 .enable_reg = 0xb0a0, 1025 .enable_mask = BIT(0), 1026 .hw.init = &(struct clk_init_data){ 1027 .name = "cam_cc_icp_clk", 1028 .parent_data = &(const struct clk_parent_data){ 1029 .hw = &cam_cc_icp_clk_src.clkr.hw, 1030 }, 1031 .num_parents = 1, 1032 .flags = CLK_SET_RATE_PARENT, 1033 .ops = &clk_branch2_ops, 1034 }, 1035 }, 1036 }; 1037 1038 static struct clk_branch cam_cc_ife_0_axi_clk = { 1039 .halt_reg = 0x9080, 1040 .halt_check = BRANCH_HALT, 1041 .clkr = { 1042 .enable_reg = 0x9080, 1043 .enable_mask = BIT(0), 1044 .hw.init = &(struct clk_init_data){ 1045 .name = "cam_cc_ife_0_axi_clk", 1046 .ops = &clk_branch2_ops, 1047 }, 1048 }, 1049 }; 1050 1051 static struct clk_branch cam_cc_ife_0_clk = { 1052 .halt_reg = 0x9028, 1053 .halt_check = BRANCH_HALT, 1054 .clkr = { 1055 .enable_reg = 0x9028, 1056 .enable_mask = BIT(0), 1057 .hw.init = &(struct clk_init_data){ 1058 .name = "cam_cc_ife_0_clk", 1059 .parent_data = &(const struct clk_parent_data){ 1060 .hw = &cam_cc_ife_0_clk_src.clkr.hw, 1061 }, 1062 .num_parents = 1, 1063 .flags = CLK_SET_RATE_PARENT, 1064 .ops = &clk_branch2_ops, 1065 }, 1066 }, 1067 }; 1068 1069 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1070 .halt_reg = 0x907c, 1071 .halt_check = BRANCH_HALT, 1072 .clkr = { 1073 .enable_reg = 0x907c, 1074 .enable_mask = BIT(0), 1075 .hw.init = &(struct clk_init_data){ 1076 .name = "cam_cc_ife_0_cphy_rx_clk", 1077 .parent_data = &(const struct clk_parent_data){ 1078 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 1079 }, 1080 .num_parents = 1, 1081 .flags = CLK_SET_RATE_PARENT, 1082 .ops = &clk_branch2_ops, 1083 }, 1084 }, 1085 }; 1086 1087 static struct clk_branch cam_cc_ife_0_csid_clk = { 1088 .halt_reg = 0x9054, 1089 .halt_check = BRANCH_HALT, 1090 .clkr = { 1091 .enable_reg = 0x9054, 1092 .enable_mask = BIT(0), 1093 .hw.init = &(struct clk_init_data){ 1094 .name = "cam_cc_ife_0_csid_clk", 1095 .parent_data = &(const struct clk_parent_data){ 1096 .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw, 1097 }, 1098 .num_parents = 1, 1099 .flags = CLK_SET_RATE_PARENT, 1100 .ops = &clk_branch2_ops, 1101 }, 1102 }, 1103 }; 1104 1105 static struct clk_branch cam_cc_ife_0_dsp_clk = { 1106 .halt_reg = 0x9038, 1107 .halt_check = BRANCH_HALT, 1108 .clkr = { 1109 .enable_reg = 0x9038, 1110 .enable_mask = BIT(0), 1111 .hw.init = &(struct clk_init_data){ 1112 .name = "cam_cc_ife_0_dsp_clk", 1113 .parent_data = &(const struct clk_parent_data){ 1114 .hw = &cam_cc_ife_0_clk_src.clkr.hw, 1115 }, 1116 .num_parents = 1, 1117 .flags = CLK_SET_RATE_PARENT, 1118 .ops = &clk_branch2_ops, 1119 }, 1120 }, 1121 }; 1122 1123 static struct clk_branch cam_cc_ife_1_axi_clk = { 1124 .halt_reg = 0xa058, 1125 .halt_check = BRANCH_HALT, 1126 .clkr = { 1127 .enable_reg = 0xa058, 1128 .enable_mask = BIT(0), 1129 .hw.init = &(struct clk_init_data){ 1130 .name = "cam_cc_ife_1_axi_clk", 1131 .ops = &clk_branch2_ops, 1132 }, 1133 }, 1134 }; 1135 1136 static struct clk_branch cam_cc_ife_1_clk = { 1137 .halt_reg = 0xa028, 1138 .halt_check = BRANCH_HALT, 1139 .clkr = { 1140 .enable_reg = 0xa028, 1141 .enable_mask = BIT(0), 1142 .hw.init = &(struct clk_init_data){ 1143 .name = "cam_cc_ife_1_clk", 1144 .parent_data = &(const struct clk_parent_data){ 1145 .hw = &cam_cc_ife_1_clk_src.clkr.hw, 1146 }, 1147 .num_parents = 1, 1148 .flags = CLK_SET_RATE_PARENT, 1149 .ops = &clk_branch2_ops, 1150 }, 1151 }, 1152 }; 1153 1154 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1155 .halt_reg = 0xa054, 1156 .halt_check = BRANCH_HALT, 1157 .clkr = { 1158 .enable_reg = 0xa054, 1159 .enable_mask = BIT(0), 1160 .hw.init = &(struct clk_init_data){ 1161 .name = "cam_cc_ife_1_cphy_rx_clk", 1162 .parent_data = &(const struct clk_parent_data){ 1163 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 1164 }, 1165 .num_parents = 1, 1166 .flags = CLK_SET_RATE_PARENT, 1167 .ops = &clk_branch2_ops, 1168 }, 1169 }, 1170 }; 1171 1172 static struct clk_branch cam_cc_ife_1_csid_clk = { 1173 .halt_reg = 0xa04c, 1174 .halt_check = BRANCH_HALT, 1175 .clkr = { 1176 .enable_reg = 0xa04c, 1177 .enable_mask = BIT(0), 1178 .hw.init = &(struct clk_init_data){ 1179 .name = "cam_cc_ife_1_csid_clk", 1180 .parent_data = &(const struct clk_parent_data){ 1181 .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw, 1182 }, 1183 .num_parents = 1, 1184 .flags = CLK_SET_RATE_PARENT, 1185 .ops = &clk_branch2_ops, 1186 }, 1187 }, 1188 }; 1189 1190 static struct clk_branch cam_cc_ife_1_dsp_clk = { 1191 .halt_reg = 0xa030, 1192 .halt_check = BRANCH_HALT, 1193 .clkr = { 1194 .enable_reg = 0xa030, 1195 .enable_mask = BIT(0), 1196 .hw.init = &(struct clk_init_data){ 1197 .name = "cam_cc_ife_1_dsp_clk", 1198 .parent_data = &(const struct clk_parent_data){ 1199 .hw = &cam_cc_ife_1_clk_src.clkr.hw, 1200 }, 1201 .num_parents = 1, 1202 .flags = CLK_SET_RATE_PARENT, 1203 .ops = &clk_branch2_ops, 1204 }, 1205 }, 1206 }; 1207 1208 static struct clk_branch cam_cc_ife_lite_clk = { 1209 .halt_reg = 0xb01c, 1210 .halt_check = BRANCH_HALT, 1211 .clkr = { 1212 .enable_reg = 0xb01c, 1213 .enable_mask = BIT(0), 1214 .hw.init = &(struct clk_init_data){ 1215 .name = "cam_cc_ife_lite_clk", 1216 .parent_data = &(const struct clk_parent_data){ 1217 .hw = &cam_cc_ife_lite_clk_src.clkr.hw, 1218 }, 1219 .num_parents = 1, 1220 .flags = CLK_SET_RATE_PARENT, 1221 .ops = &clk_branch2_ops, 1222 }, 1223 }, 1224 }; 1225 1226 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1227 .halt_reg = 0xb044, 1228 .halt_check = BRANCH_HALT, 1229 .clkr = { 1230 .enable_reg = 0xb044, 1231 .enable_mask = BIT(0), 1232 .hw.init = &(struct clk_init_data){ 1233 .name = "cam_cc_ife_lite_cphy_rx_clk", 1234 .parent_data = &(const struct clk_parent_data){ 1235 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 1236 }, 1237 .num_parents = 1, 1238 .flags = CLK_SET_RATE_PARENT, 1239 .ops = &clk_branch2_ops, 1240 }, 1241 }, 1242 }; 1243 1244 static struct clk_branch cam_cc_ife_lite_csid_clk = { 1245 .halt_reg = 0xb03c, 1246 .halt_check = BRANCH_HALT, 1247 .clkr = { 1248 .enable_reg = 0xb03c, 1249 .enable_mask = BIT(0), 1250 .hw.init = &(struct clk_init_data){ 1251 .name = "cam_cc_ife_lite_csid_clk", 1252 .parent_data = &(const struct clk_parent_data){ 1253 .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1254 }, 1255 .num_parents = 1, 1256 .flags = CLK_SET_RATE_PARENT, 1257 .ops = &clk_branch2_ops, 1258 }, 1259 }, 1260 }; 1261 1262 static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1263 .halt_reg = 0x7040, 1264 .halt_check = BRANCH_HALT, 1265 .clkr = { 1266 .enable_reg = 0x7040, 1267 .enable_mask = BIT(0), 1268 .hw.init = &(struct clk_init_data){ 1269 .name = "cam_cc_ipe_0_ahb_clk", 1270 .parent_data = &(const struct clk_parent_data){ 1271 .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 1272 }, 1273 .num_parents = 1, 1274 .flags = CLK_SET_RATE_PARENT, 1275 .ops = &clk_branch2_ops, 1276 }, 1277 }, 1278 }; 1279 1280 static struct clk_branch cam_cc_ipe_0_areg_clk = { 1281 .halt_reg = 0x703c, 1282 .halt_check = BRANCH_HALT, 1283 .clkr = { 1284 .enable_reg = 0x703c, 1285 .enable_mask = BIT(0), 1286 .hw.init = &(struct clk_init_data){ 1287 .name = "cam_cc_ipe_0_areg_clk", 1288 .parent_data = &(const struct clk_parent_data){ 1289 .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, 1290 }, 1291 .num_parents = 1, 1292 .flags = CLK_SET_RATE_PARENT, 1293 .ops = &clk_branch2_ops, 1294 }, 1295 }, 1296 }; 1297 1298 static struct clk_branch cam_cc_ipe_0_axi_clk = { 1299 .halt_reg = 0x7038, 1300 .halt_check = BRANCH_HALT, 1301 .clkr = { 1302 .enable_reg = 0x7038, 1303 .enable_mask = BIT(0), 1304 .hw.init = &(struct clk_init_data){ 1305 .name = "cam_cc_ipe_0_axi_clk", 1306 .ops = &clk_branch2_ops, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch cam_cc_ipe_0_clk = { 1312 .halt_reg = 0x7028, 1313 .halt_check = BRANCH_HALT, 1314 .clkr = { 1315 .enable_reg = 0x7028, 1316 .enable_mask = BIT(0), 1317 .hw.init = &(struct clk_init_data){ 1318 .name = "cam_cc_ipe_0_clk", 1319 .parent_data = &(const struct clk_parent_data){ 1320 .hw = &cam_cc_ipe_0_clk_src.clkr.hw, 1321 }, 1322 .num_parents = 1, 1323 .flags = CLK_SET_RATE_PARENT, 1324 .ops = &clk_branch2_ops, 1325 }, 1326 }, 1327 }; 1328 1329 static struct clk_branch cam_cc_jpeg_clk = { 1330 .halt_reg = 0xb064, 1331 .halt_check = BRANCH_HALT, 1332 .clkr = { 1333 .enable_reg = 0xb064, 1334 .enable_mask = BIT(0), 1335 .hw.init = &(struct clk_init_data){ 1336 .name = "cam_cc_jpeg_clk", 1337 .parent_data = &(const struct clk_parent_data){ 1338 .hw = &cam_cc_jpeg_clk_src.clkr.hw, 1339 }, 1340 .num_parents = 1, 1341 .flags = CLK_SET_RATE_PARENT, 1342 .ops = &clk_branch2_ops, 1343 }, 1344 }, 1345 }; 1346 1347 static struct clk_branch cam_cc_lrme_clk = { 1348 .halt_reg = 0xb110, 1349 .halt_check = BRANCH_HALT, 1350 .clkr = { 1351 .enable_reg = 0xb110, 1352 .enable_mask = BIT(0), 1353 .hw.init = &(struct clk_init_data){ 1354 .name = "cam_cc_lrme_clk", 1355 .parent_data = &(const struct clk_parent_data){ 1356 .hw = &cam_cc_lrme_clk_src.clkr.hw, 1357 }, 1358 .num_parents = 1, 1359 .flags = CLK_SET_RATE_PARENT, 1360 .ops = &clk_branch2_ops, 1361 }, 1362 }, 1363 }; 1364 1365 static struct clk_branch cam_cc_mclk0_clk = { 1366 .halt_reg = 0x401c, 1367 .halt_check = BRANCH_HALT, 1368 .clkr = { 1369 .enable_reg = 0x401c, 1370 .enable_mask = BIT(0), 1371 .hw.init = &(struct clk_init_data){ 1372 .name = "cam_cc_mclk0_clk", 1373 .parent_data = &(const struct clk_parent_data){ 1374 .hw = &cam_cc_mclk0_clk_src.clkr.hw, 1375 }, 1376 .num_parents = 1, 1377 .flags = CLK_SET_RATE_PARENT, 1378 .ops = &clk_branch2_ops, 1379 }, 1380 }, 1381 }; 1382 1383 static struct clk_branch cam_cc_mclk1_clk = { 1384 .halt_reg = 0x403c, 1385 .halt_check = BRANCH_HALT, 1386 .clkr = { 1387 .enable_reg = 0x403c, 1388 .enable_mask = BIT(0), 1389 .hw.init = &(struct clk_init_data){ 1390 .name = "cam_cc_mclk1_clk", 1391 .parent_data = &(const struct clk_parent_data){ 1392 .hw = &cam_cc_mclk1_clk_src.clkr.hw, 1393 }, 1394 .num_parents = 1, 1395 .flags = CLK_SET_RATE_PARENT, 1396 .ops = &clk_branch2_ops, 1397 }, 1398 }, 1399 }; 1400 1401 static struct clk_branch cam_cc_mclk2_clk = { 1402 .halt_reg = 0x405c, 1403 .halt_check = BRANCH_HALT, 1404 .clkr = { 1405 .enable_reg = 0x405c, 1406 .enable_mask = BIT(0), 1407 .hw.init = &(struct clk_init_data){ 1408 .name = "cam_cc_mclk2_clk", 1409 .parent_data = &(const struct clk_parent_data){ 1410 .hw = &cam_cc_mclk2_clk_src.clkr.hw, 1411 }, 1412 .num_parents = 1, 1413 .flags = CLK_SET_RATE_PARENT, 1414 .ops = &clk_branch2_ops, 1415 }, 1416 }, 1417 }; 1418 1419 static struct clk_branch cam_cc_mclk3_clk = { 1420 .halt_reg = 0x407c, 1421 .halt_check = BRANCH_HALT, 1422 .clkr = { 1423 .enable_reg = 0x407c, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(struct clk_init_data){ 1426 .name = "cam_cc_mclk3_clk", 1427 .parent_data = &(const struct clk_parent_data){ 1428 .hw = &cam_cc_mclk3_clk_src.clkr.hw, 1429 }, 1430 .num_parents = 1, 1431 .flags = CLK_SET_RATE_PARENT, 1432 .ops = &clk_branch2_ops, 1433 }, 1434 }, 1435 }; 1436 1437 static struct clk_branch cam_cc_mclk4_clk = { 1438 .halt_reg = 0x409c, 1439 .halt_check = BRANCH_HALT, 1440 .clkr = { 1441 .enable_reg = 0x409c, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(struct clk_init_data){ 1444 .name = "cam_cc_mclk4_clk", 1445 .parent_data = &(const struct clk_parent_data){ 1446 .hw = &cam_cc_mclk4_clk_src.clkr.hw, 1447 }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT, 1450 .ops = &clk_branch2_ops, 1451 }, 1452 }, 1453 }; 1454 1455 static struct clk_branch cam_cc_soc_ahb_clk = { 1456 .halt_reg = 0xb140, 1457 .halt_check = BRANCH_HALT, 1458 .clkr = { 1459 .enable_reg = 0xb140, 1460 .enable_mask = BIT(0), 1461 .hw.init = &(struct clk_init_data){ 1462 .name = "cam_cc_soc_ahb_clk", 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch cam_cc_sys_tmr_clk = { 1469 .halt_reg = 0xb0a8, 1470 .halt_check = BRANCH_HALT, 1471 .clkr = { 1472 .enable_reg = 0xb0a8, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(struct clk_init_data){ 1475 .name = "cam_cc_sys_tmr_clk", 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct gdsc bps_gdsc = { 1482 .gdscr = 0x6004, 1483 .pd = { 1484 .name = "bps_gdsc", 1485 }, 1486 .pwrsts = PWRSTS_OFF_ON, 1487 .flags = HW_CTRL, 1488 }; 1489 1490 static struct gdsc ife_0_gdsc = { 1491 .gdscr = 0x9004, 1492 .pd = { 1493 .name = "ife_0_gdsc", 1494 }, 1495 .pwrsts = PWRSTS_OFF_ON, 1496 }; 1497 1498 static struct gdsc ife_1_gdsc = { 1499 .gdscr = 0xa004, 1500 .pd = { 1501 .name = "ife_1_gdsc", 1502 }, 1503 .pwrsts = PWRSTS_OFF_ON, 1504 }; 1505 1506 static struct gdsc ipe_0_gdsc = { 1507 .gdscr = 0x7004, 1508 .pd = { 1509 .name = "ipe_0_gdsc", 1510 }, 1511 .pwrsts = PWRSTS_OFF_ON, 1512 .flags = HW_CTRL, 1513 }; 1514 1515 static struct gdsc titan_top_gdsc = { 1516 .gdscr = 0xb134, 1517 .pd = { 1518 .name = "titan_top_gdsc", 1519 }, 1520 .pwrsts = PWRSTS_OFF_ON, 1521 }; 1522 1523 static struct clk_hw *cam_cc_sc7180_hws[] = { 1524 [CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw, 1525 }; 1526 1527 static struct clk_regmap *cam_cc_sc7180_clocks[] = { 1528 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1529 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1530 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 1531 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1532 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1533 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1534 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1535 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1536 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1537 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1538 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1539 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1540 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1541 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1542 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1543 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1544 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1545 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1546 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1547 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 1548 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 1549 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1550 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1551 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1552 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 1553 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1554 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1555 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1556 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 1557 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1558 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1559 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 1560 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 1561 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 1562 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 1563 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 1564 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1565 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1566 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 1567 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 1568 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 1569 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 1570 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1571 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1572 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1573 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1574 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1575 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 1576 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 1577 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 1578 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 1579 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 1580 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 1581 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 1582 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 1583 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 1584 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1585 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1586 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1587 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1588 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1589 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1590 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1591 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1592 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 1593 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 1594 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1595 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1596 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1597 [CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr, 1598 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1599 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1600 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 1601 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 1602 }; 1603 static struct gdsc *cam_cc_sc7180_gdscs[] = { 1604 [BPS_GDSC] = &bps_gdsc, 1605 [IFE_0_GDSC] = &ife_0_gdsc, 1606 [IFE_1_GDSC] = &ife_1_gdsc, 1607 [IPE_0_GDSC] = &ipe_0_gdsc, 1608 [TITAN_TOP_GDSC] = &titan_top_gdsc, 1609 }; 1610 1611 static const struct regmap_config cam_cc_sc7180_regmap_config = { 1612 .reg_bits = 32, 1613 .reg_stride = 4, 1614 .val_bits = 32, 1615 .max_register = 0xd028, 1616 .fast_io = true, 1617 }; 1618 1619 static const struct qcom_cc_desc cam_cc_sc7180_desc = { 1620 .config = &cam_cc_sc7180_regmap_config, 1621 .clk_hws = cam_cc_sc7180_hws, 1622 .num_clk_hws = ARRAY_SIZE(cam_cc_sc7180_hws), 1623 .clks = cam_cc_sc7180_clocks, 1624 .num_clks = ARRAY_SIZE(cam_cc_sc7180_clocks), 1625 .gdscs = cam_cc_sc7180_gdscs, 1626 .num_gdscs = ARRAY_SIZE(cam_cc_sc7180_gdscs), 1627 }; 1628 1629 static const struct of_device_id cam_cc_sc7180_match_table[] = { 1630 { .compatible = "qcom,sc7180-camcc" }, 1631 { } 1632 }; 1633 MODULE_DEVICE_TABLE(of, cam_cc_sc7180_match_table); 1634 1635 static int cam_cc_sc7180_probe(struct platform_device *pdev) 1636 { 1637 struct regmap *regmap; 1638 int ret; 1639 1640 ret = devm_pm_runtime_enable(&pdev->dev); 1641 if (ret < 0) 1642 return ret; 1643 1644 ret = devm_pm_clk_create(&pdev->dev); 1645 if (ret < 0) 1646 return ret; 1647 1648 ret = pm_clk_add(&pdev->dev, "xo"); 1649 if (ret < 0) { 1650 dev_err(&pdev->dev, "Failed to acquire XO clock\n"); 1651 return ret; 1652 } 1653 1654 ret = pm_clk_add(&pdev->dev, "iface"); 1655 if (ret < 0) { 1656 dev_err(&pdev->dev, "Failed to acquire iface clock\n"); 1657 return ret; 1658 } 1659 1660 ret = pm_runtime_get(&pdev->dev); 1661 if (ret) 1662 return ret; 1663 1664 regmap = qcom_cc_map(pdev, &cam_cc_sc7180_desc); 1665 if (IS_ERR(regmap)) { 1666 ret = PTR_ERR(regmap); 1667 pm_runtime_put(&pdev->dev); 1668 return ret; 1669 } 1670 1671 clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 1672 clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 1673 clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 1674 clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 1675 1676 ret = qcom_cc_really_probe(pdev, &cam_cc_sc7180_desc, regmap); 1677 pm_runtime_put(&pdev->dev); 1678 if (ret < 0) { 1679 dev_err(&pdev->dev, "Failed to register CAM CC clocks\n"); 1680 return ret; 1681 } 1682 1683 return 0; 1684 } 1685 1686 static const struct dev_pm_ops cam_cc_pm_ops = { 1687 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 1688 }; 1689 1690 static struct platform_driver cam_cc_sc7180_driver = { 1691 .probe = cam_cc_sc7180_probe, 1692 .driver = { 1693 .name = "cam_cc-sc7180", 1694 .of_match_table = cam_cc_sc7180_match_table, 1695 .pm = &cam_cc_pm_ops, 1696 }, 1697 }; 1698 1699 static int __init cam_cc_sc7180_init(void) 1700 { 1701 return platform_driver_register(&cam_cc_sc7180_driver); 1702 } 1703 subsys_initcall(cam_cc_sc7180_init); 1704 1705 static void __exit cam_cc_sc7180_exit(void) 1706 { 1707 platform_driver_unregister(&cam_cc_sc7180_driver); 1708 } 1709 module_exit(cam_cc_sc7180_exit); 1710 1711 MODULE_DESCRIPTION("QTI CAM_CC SC7180 Driver"); 1712 MODULE_LICENSE("GPL v2"); 1713