115d09e83STaniya Das // SPDX-License-Identifier: GPL-2.0-only 215d09e83STaniya Das /* 315d09e83STaniya Das * Copyright (c) 2020, The Linux Foundation. All rights reserved. 415d09e83STaniya Das */ 515d09e83STaniya Das 615d09e83STaniya Das #include <linux/clk-provider.h> 715d09e83STaniya Das #include <linux/err.h> 815d09e83STaniya Das #include <linux/module.h> 915d09e83STaniya Das #include <linux/of.h> 1015d09e83STaniya Das #include <linux/of_device.h> 1115d09e83STaniya Das #include <linux/pm_clock.h> 1215d09e83STaniya Das #include <linux/pm_runtime.h> 1315d09e83STaniya Das #include <linux/regmap.h> 1415d09e83STaniya Das 1515d09e83STaniya Das #include <dt-bindings/clock/qcom,camcc-sc7180.h> 1615d09e83STaniya Das 1715d09e83STaniya Das #include "clk-alpha-pll.h" 1815d09e83STaniya Das #include "clk-branch.h" 1915d09e83STaniya Das #include "clk-rcg.h" 2015d09e83STaniya Das #include "clk-regmap.h" 2115d09e83STaniya Das #include "common.h" 2215d09e83STaniya Das #include "gdsc.h" 2315d09e83STaniya Das #include "reset.h" 2415d09e83STaniya Das 2515d09e83STaniya Das enum { 2615d09e83STaniya Das P_BI_TCXO, 2715d09e83STaniya Das P_CAM_CC_PLL0_OUT_EVEN, 2815d09e83STaniya Das P_CAM_CC_PLL1_OUT_EVEN, 2915d09e83STaniya Das P_CAM_CC_PLL2_OUT_AUX, 3015d09e83STaniya Das P_CAM_CC_PLL2_OUT_EARLY, 3115d09e83STaniya Das P_CAM_CC_PLL3_OUT_MAIN, 3215d09e83STaniya Das P_CORE_BI_PLL_TEST_SE, 3315d09e83STaniya Das }; 3415d09e83STaniya Das 3515d09e83STaniya Das static const struct pll_vco agera_vco[] = { 3615d09e83STaniya Das { 600000000, 3300000000UL, 0 }, 3715d09e83STaniya Das }; 3815d09e83STaniya Das 3915d09e83STaniya Das static const struct pll_vco fabia_vco[] = { 4015d09e83STaniya Das { 249600000, 2000000000UL, 0 }, 4115d09e83STaniya Das }; 4215d09e83STaniya Das 4315d09e83STaniya Das /* 600MHz configuration */ 4415d09e83STaniya Das static const struct alpha_pll_config cam_cc_pll0_config = { 4515d09e83STaniya Das .l = 0x1f, 4615d09e83STaniya Das .alpha = 0x4000, 4715d09e83STaniya Das .config_ctl_val = 0x20485699, 4815d09e83STaniya Das .config_ctl_hi_val = 0x00002067, 4915d09e83STaniya Das .test_ctl_val = 0x40000000, 5015d09e83STaniya Das .user_ctl_hi_val = 0x00004805, 5115d09e83STaniya Das .user_ctl_val = 0x00000001, 5215d09e83STaniya Das }; 5315d09e83STaniya Das 5415d09e83STaniya Das static struct clk_alpha_pll cam_cc_pll0 = { 5515d09e83STaniya Das .offset = 0x0, 5615d09e83STaniya Das .vco_table = fabia_vco, 5715d09e83STaniya Das .num_vco = ARRAY_SIZE(fabia_vco), 5815d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 5915d09e83STaniya Das .clkr = { 6015d09e83STaniya Das .hw.init = &(struct clk_init_data){ 6115d09e83STaniya Das .name = "cam_cc_pll0", 6215d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 6315d09e83STaniya Das .fw_name = "bi_tcxo", 6415d09e83STaniya Das }, 6515d09e83STaniya Das .num_parents = 1, 6615d09e83STaniya Das .ops = &clk_alpha_pll_fabia_ops, 6715d09e83STaniya Das }, 6815d09e83STaniya Das }, 6915d09e83STaniya Das }; 7015d09e83STaniya Das 7115d09e83STaniya Das /* 860MHz configuration */ 7215d09e83STaniya Das static const struct alpha_pll_config cam_cc_pll1_config = { 7315d09e83STaniya Das .l = 0x2a, 7415d09e83STaniya Das .alpha = 0x1555, 7515d09e83STaniya Das .config_ctl_val = 0x20485699, 7615d09e83STaniya Das .config_ctl_hi_val = 0x00002067, 7715d09e83STaniya Das .test_ctl_val = 0x40000000, 7815d09e83STaniya Das .user_ctl_hi_val = 0x00004805, 7915d09e83STaniya Das }; 8015d09e83STaniya Das 8115d09e83STaniya Das static struct clk_alpha_pll cam_cc_pll1 = { 8215d09e83STaniya Das .offset = 0x1000, 8315d09e83STaniya Das .vco_table = fabia_vco, 8415d09e83STaniya Das .num_vco = ARRAY_SIZE(fabia_vco), 8515d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 8615d09e83STaniya Das .clkr = { 8715d09e83STaniya Das .hw.init = &(struct clk_init_data){ 8815d09e83STaniya Das .name = "cam_cc_pll1", 8915d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 9015d09e83STaniya Das .fw_name = "bi_tcxo", 9115d09e83STaniya Das }, 9215d09e83STaniya Das .num_parents = 1, 9315d09e83STaniya Das .ops = &clk_alpha_pll_fabia_ops, 9415d09e83STaniya Das }, 9515d09e83STaniya Das }, 9615d09e83STaniya Das }; 9715d09e83STaniya Das 9815d09e83STaniya Das /* 1920MHz configuration */ 9915d09e83STaniya Das static const struct alpha_pll_config cam_cc_pll2_config = { 10015d09e83STaniya Das .l = 0x64, 10115d09e83STaniya Das .config_ctl_val = 0x20000800, 10215d09e83STaniya Das .config_ctl_hi_val = 0x400003D2, 10315d09e83STaniya Das .test_ctl_val = 0x04000400, 10415d09e83STaniya Das .test_ctl_hi_val = 0x00004000, 10515d09e83STaniya Das .user_ctl_val = 0x0000030F, 10615d09e83STaniya Das }; 10715d09e83STaniya Das 10815d09e83STaniya Das static struct clk_alpha_pll cam_cc_pll2 = { 10915d09e83STaniya Das .offset = 0x2000, 11015d09e83STaniya Das .vco_table = agera_vco, 11115d09e83STaniya Das .num_vco = ARRAY_SIZE(agera_vco), 11215d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 11315d09e83STaniya Das .clkr = { 11415d09e83STaniya Das .hw.init = &(struct clk_init_data){ 11515d09e83STaniya Das .name = "cam_cc_pll2", 11615d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 11715d09e83STaniya Das .fw_name = "bi_tcxo", 11815d09e83STaniya Das }, 11915d09e83STaniya Das .num_parents = 1, 12015d09e83STaniya Das .ops = &clk_alpha_pll_agera_ops, 12115d09e83STaniya Das }, 12215d09e83STaniya Das }, 12315d09e83STaniya Das }; 12415d09e83STaniya Das 12515d09e83STaniya Das static struct clk_fixed_factor cam_cc_pll2_out_early = { 12615d09e83STaniya Das .mult = 1, 12715d09e83STaniya Das .div = 2, 12815d09e83STaniya Das .hw.init = &(struct clk_init_data){ 12915d09e83STaniya Das .name = "cam_cc_pll2_out_early", 13015d09e83STaniya Das .parent_names = (const char *[]){ "cam_cc_pll2" }, 13115d09e83STaniya Das .num_parents = 1, 13215d09e83STaniya Das .ops = &clk_fixed_factor_ops, 13315d09e83STaniya Das }, 13415d09e83STaniya Das }; 13515d09e83STaniya Das 13615d09e83STaniya Das static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = { 13715d09e83STaniya Das { 0x3, 4 }, 13815d09e83STaniya Das { } 13915d09e83STaniya Das }; 14015d09e83STaniya Das 14115d09e83STaniya Das static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { 14215d09e83STaniya Das .offset = 0x2000, 14315d09e83STaniya Das .post_div_shift = 8, 14415d09e83STaniya Das .post_div_table = post_div_table_cam_cc_pll2_out_aux, 14515d09e83STaniya Das .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux), 14615d09e83STaniya Das .width = 2, 14715d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 14815d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 14915d09e83STaniya Das .name = "cam_cc_pll2_out_aux", 15015d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 15115d09e83STaniya Das .hw = &cam_cc_pll2.clkr.hw, 15215d09e83STaniya Das }, 15315d09e83STaniya Das .num_parents = 1, 15415d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 15515d09e83STaniya Das .ops = &clk_alpha_pll_postdiv_ops, 15615d09e83STaniya Das }, 15715d09e83STaniya Das }; 15815d09e83STaniya Das 15915d09e83STaniya Das /* 1080MHz configuration */ 16015d09e83STaniya Das static const struct alpha_pll_config cam_cc_pll3_config = { 16115d09e83STaniya Das .l = 0x38, 16215d09e83STaniya Das .alpha = 0x4000, 16315d09e83STaniya Das .config_ctl_val = 0x20485699, 16415d09e83STaniya Das .config_ctl_hi_val = 0x00002067, 16515d09e83STaniya Das .test_ctl_val = 0x40000000, 16615d09e83STaniya Das .user_ctl_hi_val = 0x00004805, 16715d09e83STaniya Das }; 16815d09e83STaniya Das 16915d09e83STaniya Das static struct clk_alpha_pll cam_cc_pll3 = { 17015d09e83STaniya Das .offset = 0x3000, 17115d09e83STaniya Das .vco_table = fabia_vco, 17215d09e83STaniya Das .num_vco = ARRAY_SIZE(fabia_vco), 17315d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 17415d09e83STaniya Das .clkr = { 17515d09e83STaniya Das .hw.init = &(struct clk_init_data){ 17615d09e83STaniya Das .name = "cam_cc_pll3", 17715d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 17815d09e83STaniya Das .fw_name = "bi_tcxo", 17915d09e83STaniya Das }, 18015d09e83STaniya Das .num_parents = 1, 18115d09e83STaniya Das .ops = &clk_alpha_pll_fabia_ops, 18215d09e83STaniya Das }, 18315d09e83STaniya Das }, 18415d09e83STaniya Das }; 18515d09e83STaniya Das 18615d09e83STaniya Das static const struct parent_map cam_cc_parent_map_0[] = { 18715d09e83STaniya Das { P_BI_TCXO, 0 }, 18815d09e83STaniya Das { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 18915d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 19015d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 19115d09e83STaniya Das }; 19215d09e83STaniya Das 19315d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_0[] = { 19415d09e83STaniya Das { .fw_name = "bi_tcxo" }, 19515d09e83STaniya Das { .hw = &cam_cc_pll1.clkr.hw }, 19615d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 19715d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 19815d09e83STaniya Das }; 19915d09e83STaniya Das 20015d09e83STaniya Das static const struct parent_map cam_cc_parent_map_1[] = { 20115d09e83STaniya Das { P_BI_TCXO, 0 }, 20215d09e83STaniya Das { P_CAM_CC_PLL2_OUT_AUX, 1 }, 20315d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 20415d09e83STaniya Das }; 20515d09e83STaniya Das 20615d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_1[] = { 20715d09e83STaniya Das { .fw_name = "bi_tcxo" }, 20815d09e83STaniya Das { .hw = &cam_cc_pll2_out_aux.clkr.hw }, 20915d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 21015d09e83STaniya Das }; 21115d09e83STaniya Das 21215d09e83STaniya Das static const struct parent_map cam_cc_parent_map_2[] = { 21315d09e83STaniya Das { P_BI_TCXO, 0 }, 21415d09e83STaniya Das { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 21515d09e83STaniya Das { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 21615d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 21715d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 21815d09e83STaniya Das }; 21915d09e83STaniya Das 22015d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_2[] = { 22115d09e83STaniya Das { .fw_name = "bi_tcxo" }, 22215d09e83STaniya Das { .hw = &cam_cc_pll2_out_early.hw }, 22315d09e83STaniya Das { .hw = &cam_cc_pll3.clkr.hw }, 22415d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 22515d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 22615d09e83STaniya Das }; 22715d09e83STaniya Das 22815d09e83STaniya Das static const struct parent_map cam_cc_parent_map_3[] = { 22915d09e83STaniya Das { P_BI_TCXO, 0 }, 23015d09e83STaniya Das { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 23115d09e83STaniya Das { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 23215d09e83STaniya Das { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 23315d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 23415d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 23515d09e83STaniya Das }; 23615d09e83STaniya Das 23715d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_3[] = { 23815d09e83STaniya Das { .fw_name = "bi_tcxo" }, 23915d09e83STaniya Das { .hw = &cam_cc_pll1.clkr.hw }, 24015d09e83STaniya Das { .hw = &cam_cc_pll2_out_early.hw }, 24115d09e83STaniya Das { .hw = &cam_cc_pll3.clkr.hw }, 24215d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 24315d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 24415d09e83STaniya Das }; 24515d09e83STaniya Das 24615d09e83STaniya Das static const struct parent_map cam_cc_parent_map_4[] = { 24715d09e83STaniya Das { P_BI_TCXO, 0 }, 24815d09e83STaniya Das { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 24915d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 25015d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 25115d09e83STaniya Das }; 25215d09e83STaniya Das 25315d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_4[] = { 25415d09e83STaniya Das { .fw_name = "bi_tcxo" }, 25515d09e83STaniya Das { .hw = &cam_cc_pll3.clkr.hw }, 25615d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 25715d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 25815d09e83STaniya Das }; 25915d09e83STaniya Das 26015d09e83STaniya Das static const struct parent_map cam_cc_parent_map_5[] = { 26115d09e83STaniya Das { P_BI_TCXO, 0 }, 26215d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 26315d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 26415d09e83STaniya Das }; 26515d09e83STaniya Das 26615d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_5[] = { 26715d09e83STaniya Das { .fw_name = "bi_tcxo" }, 26815d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 26915d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 27015d09e83STaniya Das }; 27115d09e83STaniya Das 27215d09e83STaniya Das static const struct parent_map cam_cc_parent_map_6[] = { 27315d09e83STaniya Das { P_BI_TCXO, 0 }, 27415d09e83STaniya Das { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 27515d09e83STaniya Das { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 27615d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 27715d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 27815d09e83STaniya Das }; 27915d09e83STaniya Das 28015d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_6[] = { 28115d09e83STaniya Das { .fw_name = "bi_tcxo" }, 28215d09e83STaniya Das { .hw = &cam_cc_pll1.clkr.hw }, 28315d09e83STaniya Das { .hw = &cam_cc_pll3.clkr.hw }, 28415d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 28515d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 28615d09e83STaniya Das }; 28715d09e83STaniya Das 28815d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 28915d09e83STaniya Das F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 29015d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 29115d09e83STaniya Das F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 29215d09e83STaniya Das F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 29315d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 29415d09e83STaniya Das { } 29515d09e83STaniya Das }; 29615d09e83STaniya Das 29715d09e83STaniya Das static struct clk_rcg2 cam_cc_bps_clk_src = { 29815d09e83STaniya Das .cmd_rcgr = 0x6010, 29915d09e83STaniya Das .mnd_width = 0, 30015d09e83STaniya Das .hid_width = 5, 30115d09e83STaniya Das .parent_map = cam_cc_parent_map_2, 30215d09e83STaniya Das .freq_tbl = ftbl_cam_cc_bps_clk_src, 30315d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 30415d09e83STaniya Das .name = "cam_cc_bps_clk_src", 30515d09e83STaniya Das .parent_data = cam_cc_parent_data_2, 306*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 307e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 30815d09e83STaniya Das }, 30915d09e83STaniya Das }; 31015d09e83STaniya Das 31115d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 31215d09e83STaniya Das F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 31315d09e83STaniya Das F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 31415d09e83STaniya Das F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 31515d09e83STaniya Das { } 31615d09e83STaniya Das }; 31715d09e83STaniya Das 31815d09e83STaniya Das static struct clk_rcg2 cam_cc_cci_0_clk_src = { 31915d09e83STaniya Das .cmd_rcgr = 0xb0d8, 32015d09e83STaniya Das .mnd_width = 8, 32115d09e83STaniya Das .hid_width = 5, 32215d09e83STaniya Das .parent_map = cam_cc_parent_map_5, 32315d09e83STaniya Das .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 32415d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 32515d09e83STaniya Das .name = "cam_cc_cci_0_clk_src", 32615d09e83STaniya Das .parent_data = cam_cc_parent_data_5, 327*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 328e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 32915d09e83STaniya Das }, 33015d09e83STaniya Das }; 33115d09e83STaniya Das 33215d09e83STaniya Das static struct clk_rcg2 cam_cc_cci_1_clk_src = { 33315d09e83STaniya Das .cmd_rcgr = 0xb14c, 33415d09e83STaniya Das .mnd_width = 8, 33515d09e83STaniya Das .hid_width = 5, 33615d09e83STaniya Das .parent_map = cam_cc_parent_map_5, 33715d09e83STaniya Das .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 33815d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 33915d09e83STaniya Das .name = "cam_cc_cci_1_clk_src", 34015d09e83STaniya Das .parent_data = cam_cc_parent_data_5, 341*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 342e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 34315d09e83STaniya Das }, 34415d09e83STaniya Das }; 34515d09e83STaniya Das 34615d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 34715d09e83STaniya Das F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 34815d09e83STaniya Das F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), 34915d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 35015d09e83STaniya Das { } 35115d09e83STaniya Das }; 35215d09e83STaniya Das 35315d09e83STaniya Das static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 35415d09e83STaniya Das .cmd_rcgr = 0x9064, 35515d09e83STaniya Das .mnd_width = 0, 35615d09e83STaniya Das .hid_width = 5, 35715d09e83STaniya Das .parent_map = cam_cc_parent_map_3, 35815d09e83STaniya Das .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 35915d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 36015d09e83STaniya Das .name = "cam_cc_cphy_rx_clk_src", 36115d09e83STaniya Das .parent_data = cam_cc_parent_data_3, 362*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 363e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 36415d09e83STaniya Das }, 36515d09e83STaniya Das }; 36615d09e83STaniya Das 36715d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 36815d09e83STaniya Das F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 36915d09e83STaniya Das { } 37015d09e83STaniya Das }; 37115d09e83STaniya Das 37215d09e83STaniya Das static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 37315d09e83STaniya Das .cmd_rcgr = 0x5004, 37415d09e83STaniya Das .mnd_width = 0, 37515d09e83STaniya Das .hid_width = 5, 37615d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 37715d09e83STaniya Das .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 37815d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 37915d09e83STaniya Das .name = "cam_cc_csi0phytimer_clk_src", 38015d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 381*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 382e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 38315d09e83STaniya Das }, 38415d09e83STaniya Das }; 38515d09e83STaniya Das 38615d09e83STaniya Das static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 38715d09e83STaniya Das .cmd_rcgr = 0x5028, 38815d09e83STaniya Das .mnd_width = 0, 38915d09e83STaniya Das .hid_width = 5, 39015d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 39115d09e83STaniya Das .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 39215d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 39315d09e83STaniya Das .name = "cam_cc_csi1phytimer_clk_src", 39415d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 395*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 396e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 39715d09e83STaniya Das }, 39815d09e83STaniya Das }; 39915d09e83STaniya Das 40015d09e83STaniya Das static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 40115d09e83STaniya Das .cmd_rcgr = 0x504c, 40215d09e83STaniya Das .mnd_width = 0, 40315d09e83STaniya Das .hid_width = 5, 40415d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 40515d09e83STaniya Das .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 40615d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 40715d09e83STaniya Das .name = "cam_cc_csi2phytimer_clk_src", 40815d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 409*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 410e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 41115d09e83STaniya Das }, 41215d09e83STaniya Das }; 41315d09e83STaniya Das 41415d09e83STaniya Das static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 41515d09e83STaniya Das .cmd_rcgr = 0x5070, 41615d09e83STaniya Das .mnd_width = 0, 41715d09e83STaniya Das .hid_width = 5, 41815d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 41915d09e83STaniya Das .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 42015d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 42115d09e83STaniya Das .name = "cam_cc_csi3phytimer_clk_src", 42215d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 423*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 424e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 42515d09e83STaniya Das }, 42615d09e83STaniya Das }; 42715d09e83STaniya Das 42815d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 42915d09e83STaniya Das F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 43015d09e83STaniya Das F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 43115d09e83STaniya Das F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 43215d09e83STaniya Das F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 43315d09e83STaniya Das { } 43415d09e83STaniya Das }; 43515d09e83STaniya Das 43615d09e83STaniya Das static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 43715d09e83STaniya Das .cmd_rcgr = 0x603c, 43815d09e83STaniya Das .mnd_width = 0, 43915d09e83STaniya Das .hid_width = 5, 44015d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 44115d09e83STaniya Das .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 44215d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 44315d09e83STaniya Das .name = "cam_cc_fast_ahb_clk_src", 44415d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 445*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 446e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 44715d09e83STaniya Das }, 44815d09e83STaniya Das }; 44915d09e83STaniya Das 45015d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 45115d09e83STaniya Das F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 45215d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 45315d09e83STaniya Das F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 45415d09e83STaniya Das F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 45515d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 45615d09e83STaniya Das { } 45715d09e83STaniya Das }; 45815d09e83STaniya Das 45915d09e83STaniya Das static struct clk_rcg2 cam_cc_icp_clk_src = { 46015d09e83STaniya Das .cmd_rcgr = 0xb088, 46115d09e83STaniya Das .mnd_width = 0, 46215d09e83STaniya Das .hid_width = 5, 46315d09e83STaniya Das .parent_map = cam_cc_parent_map_2, 46415d09e83STaniya Das .freq_tbl = ftbl_cam_cc_icp_clk_src, 46515d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 46615d09e83STaniya Das .name = "cam_cc_icp_clk_src", 46715d09e83STaniya Das .parent_data = cam_cc_parent_data_2, 468*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 469e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 47015d09e83STaniya Das }, 47115d09e83STaniya Das }; 47215d09e83STaniya Das 47315d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 47415d09e83STaniya Das F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 47515d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 47615d09e83STaniya Das F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 47715d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 47815d09e83STaniya Das { } 47915d09e83STaniya Das }; 48015d09e83STaniya Das 48115d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_0_clk_src = { 48215d09e83STaniya Das .cmd_rcgr = 0x9010, 48315d09e83STaniya Das .mnd_width = 0, 48415d09e83STaniya Das .hid_width = 5, 48515d09e83STaniya Das .parent_map = cam_cc_parent_map_4, 48615d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 48715d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 48815d09e83STaniya Das .name = "cam_cc_ife_0_clk_src", 48915d09e83STaniya Das .parent_data = cam_cc_parent_data_4, 490*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 491e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 49215d09e83STaniya Das }, 49315d09e83STaniya Das }; 49415d09e83STaniya Das 49515d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 49615d09e83STaniya Das F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 49715d09e83STaniya Das F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), 49815d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 49915d09e83STaniya Das F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 50015d09e83STaniya Das { } 50115d09e83STaniya Das }; 50215d09e83STaniya Das 50315d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 50415d09e83STaniya Das .cmd_rcgr = 0x903c, 50515d09e83STaniya Das .mnd_width = 0, 50615d09e83STaniya Das .hid_width = 5, 50715d09e83STaniya Das .parent_map = cam_cc_parent_map_3, 50815d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 50915d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 51015d09e83STaniya Das .name = "cam_cc_ife_0_csid_clk_src", 51115d09e83STaniya Das .parent_data = cam_cc_parent_data_3, 512*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 513e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 51415d09e83STaniya Das }, 51515d09e83STaniya Das }; 51615d09e83STaniya Das 51715d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_1_clk_src = { 51815d09e83STaniya Das .cmd_rcgr = 0xa010, 51915d09e83STaniya Das .mnd_width = 0, 52015d09e83STaniya Das .hid_width = 5, 52115d09e83STaniya Das .parent_map = cam_cc_parent_map_4, 52215d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 52315d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 52415d09e83STaniya Das .name = "cam_cc_ife_1_clk_src", 52515d09e83STaniya Das .parent_data = cam_cc_parent_data_4, 526*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 527e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 52815d09e83STaniya Das }, 52915d09e83STaniya Das }; 53015d09e83STaniya Das 53115d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 53215d09e83STaniya Das .cmd_rcgr = 0xa034, 53315d09e83STaniya Das .mnd_width = 0, 53415d09e83STaniya Das .hid_width = 5, 53515d09e83STaniya Das .parent_map = cam_cc_parent_map_3, 53615d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 53715d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 53815d09e83STaniya Das .name = "cam_cc_ife_1_csid_clk_src", 53915d09e83STaniya Das .parent_data = cam_cc_parent_data_3, 540*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 541e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 54215d09e83STaniya Das }, 54315d09e83STaniya Das }; 54415d09e83STaniya Das 54515d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 54615d09e83STaniya Das .cmd_rcgr = 0xb004, 54715d09e83STaniya Das .mnd_width = 0, 54815d09e83STaniya Das .hid_width = 5, 54915d09e83STaniya Das .parent_map = cam_cc_parent_map_4, 55015d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 55115d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 55215d09e83STaniya Das .name = "cam_cc_ife_lite_clk_src", 55315d09e83STaniya Das .parent_data = cam_cc_parent_data_4, 554*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 55515d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 556e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 55715d09e83STaniya Das }, 55815d09e83STaniya Das }; 55915d09e83STaniya Das 56015d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 56115d09e83STaniya Das .cmd_rcgr = 0xb024, 56215d09e83STaniya Das .mnd_width = 0, 56315d09e83STaniya Das .hid_width = 5, 56415d09e83STaniya Das .parent_map = cam_cc_parent_map_3, 56515d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 56615d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 56715d09e83STaniya Das .name = "cam_cc_ife_lite_csid_clk_src", 56815d09e83STaniya Das .parent_data = cam_cc_parent_data_3, 569*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 570e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 57115d09e83STaniya Das }, 57215d09e83STaniya Das }; 57315d09e83STaniya Das 57415d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 57515d09e83STaniya Das F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 57615d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 57715d09e83STaniya Das F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 57815d09e83STaniya Das F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 57915d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 58015d09e83STaniya Das { } 58115d09e83STaniya Das }; 58215d09e83STaniya Das 58315d09e83STaniya Das static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 58415d09e83STaniya Das .cmd_rcgr = 0x7010, 58515d09e83STaniya Das .mnd_width = 0, 58615d09e83STaniya Das .hid_width = 5, 58715d09e83STaniya Das .parent_map = cam_cc_parent_map_2, 58815d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 58915d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 59015d09e83STaniya Das .name = "cam_cc_ipe_0_clk_src", 59115d09e83STaniya Das .parent_data = cam_cc_parent_data_2, 592*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 593e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 59415d09e83STaniya Das }, 59515d09e83STaniya Das }; 59615d09e83STaniya Das 59715d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 59815d09e83STaniya Das F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0), 59915d09e83STaniya Das F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0), 60015d09e83STaniya Das F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 60115d09e83STaniya Das F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 60215d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 60315d09e83STaniya Das { } 60415d09e83STaniya Das }; 60515d09e83STaniya Das 60615d09e83STaniya Das static struct clk_rcg2 cam_cc_jpeg_clk_src = { 60715d09e83STaniya Das .cmd_rcgr = 0xb04c, 60815d09e83STaniya Das .mnd_width = 0, 60915d09e83STaniya Das .hid_width = 5, 61015d09e83STaniya Das .parent_map = cam_cc_parent_map_2, 61115d09e83STaniya Das .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 61215d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 61315d09e83STaniya Das .name = "cam_cc_jpeg_clk_src", 61415d09e83STaniya Das .parent_data = cam_cc_parent_data_2, 615*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 616e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 61715d09e83STaniya Das }, 61815d09e83STaniya Das }; 61915d09e83STaniya Das 62015d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 62115d09e83STaniya Das F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 62215d09e83STaniya Das F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 62315d09e83STaniya Das F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 62415d09e83STaniya Das F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 62515d09e83STaniya Das { } 62615d09e83STaniya Das }; 62715d09e83STaniya Das 62815d09e83STaniya Das static struct clk_rcg2 cam_cc_lrme_clk_src = { 62915d09e83STaniya Das .cmd_rcgr = 0xb0f8, 63015d09e83STaniya Das .mnd_width = 0, 63115d09e83STaniya Das .hid_width = 5, 63215d09e83STaniya Das .parent_map = cam_cc_parent_map_6, 63315d09e83STaniya Das .freq_tbl = ftbl_cam_cc_lrme_clk_src, 63415d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 63515d09e83STaniya Das .name = "cam_cc_lrme_clk_src", 63615d09e83STaniya Das .parent_data = cam_cc_parent_data_6, 637*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), 638e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 63915d09e83STaniya Das }, 64015d09e83STaniya Das }; 64115d09e83STaniya Das 64215d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 64315d09e83STaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 64415d09e83STaniya Das F(24000000, P_CAM_CC_PLL2_OUT_AUX, 10, 1, 2), 64515d09e83STaniya Das F(64000000, P_CAM_CC_PLL2_OUT_AUX, 7.5, 0, 0), 64615d09e83STaniya Das { } 64715d09e83STaniya Das }; 64815d09e83STaniya Das 64915d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk0_clk_src = { 65015d09e83STaniya Das .cmd_rcgr = 0x4004, 65115d09e83STaniya Das .mnd_width = 8, 65215d09e83STaniya Das .hid_width = 5, 65315d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 65415d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 65515d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 65615d09e83STaniya Das .name = "cam_cc_mclk0_clk_src", 65715d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 658*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 659e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 66015d09e83STaniya Das }, 66115d09e83STaniya Das }; 66215d09e83STaniya Das 66315d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk1_clk_src = { 66415d09e83STaniya Das .cmd_rcgr = 0x4024, 66515d09e83STaniya Das .mnd_width = 8, 66615d09e83STaniya Das .hid_width = 5, 66715d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 66815d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 66915d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 67015d09e83STaniya Das .name = "cam_cc_mclk1_clk_src", 67115d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 672*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 673e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 67415d09e83STaniya Das }, 67515d09e83STaniya Das }; 67615d09e83STaniya Das 67715d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk2_clk_src = { 67815d09e83STaniya Das .cmd_rcgr = 0x4044, 67915d09e83STaniya Das .mnd_width = 8, 68015d09e83STaniya Das .hid_width = 5, 68115d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 68215d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 68315d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 68415d09e83STaniya Das .name = "cam_cc_mclk2_clk_src", 68515d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 686*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 687e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 68815d09e83STaniya Das }, 68915d09e83STaniya Das }; 69015d09e83STaniya Das 69115d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk3_clk_src = { 69215d09e83STaniya Das .cmd_rcgr = 0x4064, 69315d09e83STaniya Das .mnd_width = 8, 69415d09e83STaniya Das .hid_width = 5, 69515d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 69615d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 69715d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 69815d09e83STaniya Das .name = "cam_cc_mclk3_clk_src", 69915d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 700*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 701e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 70215d09e83STaniya Das }, 70315d09e83STaniya Das }; 70415d09e83STaniya Das 70515d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk4_clk_src = { 70615d09e83STaniya Das .cmd_rcgr = 0x4084, 70715d09e83STaniya Das .mnd_width = 8, 70815d09e83STaniya Das .hid_width = 5, 70915d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 71015d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 71115d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 71215d09e83STaniya Das .name = "cam_cc_mclk4_clk_src", 71315d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 714*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 715e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 71615d09e83STaniya Das }, 71715d09e83STaniya Das }; 71815d09e83STaniya Das 71915d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 72015d09e83STaniya Das F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 72115d09e83STaniya Das { } 72215d09e83STaniya Das }; 72315d09e83STaniya Das 72415d09e83STaniya Das static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 72515d09e83STaniya Das .cmd_rcgr = 0x6058, 72615d09e83STaniya Das .mnd_width = 0, 72715d09e83STaniya Das .hid_width = 5, 72815d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 72915d09e83STaniya Das .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 73015d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 73115d09e83STaniya Das .name = "cam_cc_slow_ahb_clk_src", 73215d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 733*3ca90171SDmitry Baryshkov .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 73415d09e83STaniya Das .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 735e5c359f7STaniya Das .ops = &clk_rcg2_shared_ops, 73615d09e83STaniya Das }, 73715d09e83STaniya Das }; 73815d09e83STaniya Das 73915d09e83STaniya Das static struct clk_branch cam_cc_bps_ahb_clk = { 74015d09e83STaniya Das .halt_reg = 0x6070, 74115d09e83STaniya Das .halt_check = BRANCH_HALT, 74215d09e83STaniya Das .clkr = { 74315d09e83STaniya Das .enable_reg = 0x6070, 74415d09e83STaniya Das .enable_mask = BIT(0), 74515d09e83STaniya Das .hw.init = &(struct clk_init_data){ 74615d09e83STaniya Das .name = "cam_cc_bps_ahb_clk", 74715d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 74815d09e83STaniya Das .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 74915d09e83STaniya Das }, 75015d09e83STaniya Das .num_parents = 1, 75115d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 75215d09e83STaniya Das .ops = &clk_branch2_ops, 75315d09e83STaniya Das }, 75415d09e83STaniya Das }, 75515d09e83STaniya Das }; 75615d09e83STaniya Das 75715d09e83STaniya Das static struct clk_branch cam_cc_bps_areg_clk = { 75815d09e83STaniya Das .halt_reg = 0x6054, 75915d09e83STaniya Das .halt_check = BRANCH_HALT, 76015d09e83STaniya Das .clkr = { 76115d09e83STaniya Das .enable_reg = 0x6054, 76215d09e83STaniya Das .enable_mask = BIT(0), 76315d09e83STaniya Das .hw.init = &(struct clk_init_data){ 76415d09e83STaniya Das .name = "cam_cc_bps_areg_clk", 76515d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 76615d09e83STaniya Das .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, 76715d09e83STaniya Das }, 76815d09e83STaniya Das .num_parents = 1, 76915d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 77015d09e83STaniya Das .ops = &clk_branch2_ops, 77115d09e83STaniya Das }, 77215d09e83STaniya Das }, 77315d09e83STaniya Das }; 77415d09e83STaniya Das 77515d09e83STaniya Das static struct clk_branch cam_cc_bps_axi_clk = { 77615d09e83STaniya Das .halt_reg = 0x6038, 77715d09e83STaniya Das .halt_check = BRANCH_HALT, 77815d09e83STaniya Das .clkr = { 77915d09e83STaniya Das .enable_reg = 0x6038, 78015d09e83STaniya Das .enable_mask = BIT(0), 78115d09e83STaniya Das .hw.init = &(struct clk_init_data){ 78215d09e83STaniya Das .name = "cam_cc_bps_axi_clk", 78315d09e83STaniya Das .ops = &clk_branch2_ops, 78415d09e83STaniya Das }, 78515d09e83STaniya Das }, 78615d09e83STaniya Das }; 78715d09e83STaniya Das 78815d09e83STaniya Das static struct clk_branch cam_cc_bps_clk = { 78915d09e83STaniya Das .halt_reg = 0x6028, 79015d09e83STaniya Das .halt_check = BRANCH_HALT, 79115d09e83STaniya Das .clkr = { 79215d09e83STaniya Das .enable_reg = 0x6028, 79315d09e83STaniya Das .enable_mask = BIT(0), 79415d09e83STaniya Das .hw.init = &(struct clk_init_data){ 79515d09e83STaniya Das .name = "cam_cc_bps_clk", 79615d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 79715d09e83STaniya Das .hw = &cam_cc_bps_clk_src.clkr.hw, 79815d09e83STaniya Das }, 79915d09e83STaniya Das .num_parents = 1, 80015d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 80115d09e83STaniya Das .ops = &clk_branch2_ops, 80215d09e83STaniya Das }, 80315d09e83STaniya Das }, 80415d09e83STaniya Das }; 80515d09e83STaniya Das 80615d09e83STaniya Das static struct clk_branch cam_cc_camnoc_axi_clk = { 80715d09e83STaniya Das .halt_reg = 0xb124, 80815d09e83STaniya Das .halt_check = BRANCH_HALT, 80915d09e83STaniya Das .clkr = { 81015d09e83STaniya Das .enable_reg = 0xb124, 81115d09e83STaniya Das .enable_mask = BIT(0), 81215d09e83STaniya Das .hw.init = &(struct clk_init_data){ 81315d09e83STaniya Das .name = "cam_cc_camnoc_axi_clk", 81415d09e83STaniya Das .ops = &clk_branch2_ops, 81515d09e83STaniya Das }, 81615d09e83STaniya Das }, 81715d09e83STaniya Das }; 81815d09e83STaniya Das 81915d09e83STaniya Das static struct clk_branch cam_cc_cci_0_clk = { 82015d09e83STaniya Das .halt_reg = 0xb0f0, 82115d09e83STaniya Das .halt_check = BRANCH_HALT, 82215d09e83STaniya Das .clkr = { 82315d09e83STaniya Das .enable_reg = 0xb0f0, 82415d09e83STaniya Das .enable_mask = BIT(0), 82515d09e83STaniya Das .hw.init = &(struct clk_init_data){ 82615d09e83STaniya Das .name = "cam_cc_cci_0_clk", 82715d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 82815d09e83STaniya Das .hw = &cam_cc_cci_0_clk_src.clkr.hw, 82915d09e83STaniya Das }, 83015d09e83STaniya Das .num_parents = 1, 83115d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 83215d09e83STaniya Das .ops = &clk_branch2_ops, 83315d09e83STaniya Das }, 83415d09e83STaniya Das }, 83515d09e83STaniya Das }; 83615d09e83STaniya Das 83715d09e83STaniya Das static struct clk_branch cam_cc_cci_1_clk = { 83815d09e83STaniya Das .halt_reg = 0xb164, 83915d09e83STaniya Das .halt_check = BRANCH_HALT, 84015d09e83STaniya Das .clkr = { 84115d09e83STaniya Das .enable_reg = 0xb164, 84215d09e83STaniya Das .enable_mask = BIT(0), 84315d09e83STaniya Das .hw.init = &(struct clk_init_data){ 84415d09e83STaniya Das .name = "cam_cc_cci_1_clk", 84515d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 84615d09e83STaniya Das .hw = &cam_cc_cci_1_clk_src.clkr.hw, 84715d09e83STaniya Das }, 84815d09e83STaniya Das .num_parents = 1, 84915d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 85015d09e83STaniya Das .ops = &clk_branch2_ops, 85115d09e83STaniya Das }, 85215d09e83STaniya Das }, 85315d09e83STaniya Das }; 85415d09e83STaniya Das 85515d09e83STaniya Das static struct clk_branch cam_cc_core_ahb_clk = { 85615d09e83STaniya Das .halt_reg = 0xb144, 85715d09e83STaniya Das .halt_check = BRANCH_HALT_DELAY, 85815d09e83STaniya Das .clkr = { 85915d09e83STaniya Das .enable_reg = 0xb144, 86015d09e83STaniya Das .enable_mask = BIT(0), 86115d09e83STaniya Das .hw.init = &(struct clk_init_data){ 86215d09e83STaniya Das .name = "cam_cc_core_ahb_clk", 86315d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 86415d09e83STaniya Das .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 86515d09e83STaniya Das }, 86615d09e83STaniya Das .num_parents = 1, 86715d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 86815d09e83STaniya Das .ops = &clk_branch2_ops, 86915d09e83STaniya Das }, 87015d09e83STaniya Das }, 87115d09e83STaniya Das }; 87215d09e83STaniya Das 87315d09e83STaniya Das static struct clk_branch cam_cc_cpas_ahb_clk = { 87415d09e83STaniya Das .halt_reg = 0xb11c, 87515d09e83STaniya Das .halt_check = BRANCH_HALT, 87615d09e83STaniya Das .clkr = { 87715d09e83STaniya Das .enable_reg = 0xb11c, 87815d09e83STaniya Das .enable_mask = BIT(0), 87915d09e83STaniya Das .hw.init = &(struct clk_init_data){ 88015d09e83STaniya Das .name = "cam_cc_cpas_ahb_clk", 88115d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 88215d09e83STaniya Das .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 88315d09e83STaniya Das }, 88415d09e83STaniya Das .num_parents = 1, 88515d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 88615d09e83STaniya Das .ops = &clk_branch2_ops, 88715d09e83STaniya Das }, 88815d09e83STaniya Das }, 88915d09e83STaniya Das }; 89015d09e83STaniya Das 89115d09e83STaniya Das static struct clk_branch cam_cc_csi0phytimer_clk = { 89215d09e83STaniya Das .halt_reg = 0x501c, 89315d09e83STaniya Das .halt_check = BRANCH_HALT, 89415d09e83STaniya Das .clkr = { 89515d09e83STaniya Das .enable_reg = 0x501c, 89615d09e83STaniya Das .enable_mask = BIT(0), 89715d09e83STaniya Das .hw.init = &(struct clk_init_data){ 89815d09e83STaniya Das .name = "cam_cc_csi0phytimer_clk", 89915d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 90015d09e83STaniya Das .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, 90115d09e83STaniya Das }, 90215d09e83STaniya Das .num_parents = 1, 90315d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 90415d09e83STaniya Das .ops = &clk_branch2_ops, 90515d09e83STaniya Das }, 90615d09e83STaniya Das }, 90715d09e83STaniya Das }; 90815d09e83STaniya Das 90915d09e83STaniya Das static struct clk_branch cam_cc_csi1phytimer_clk = { 91015d09e83STaniya Das .halt_reg = 0x5040, 91115d09e83STaniya Das .halt_check = BRANCH_HALT, 91215d09e83STaniya Das .clkr = { 91315d09e83STaniya Das .enable_reg = 0x5040, 91415d09e83STaniya Das .enable_mask = BIT(0), 91515d09e83STaniya Das .hw.init = &(struct clk_init_data){ 91615d09e83STaniya Das .name = "cam_cc_csi1phytimer_clk", 91715d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 91815d09e83STaniya Das .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, 91915d09e83STaniya Das }, 92015d09e83STaniya Das .num_parents = 1, 92115d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 92215d09e83STaniya Das .ops = &clk_branch2_ops, 92315d09e83STaniya Das }, 92415d09e83STaniya Das }, 92515d09e83STaniya Das }; 92615d09e83STaniya Das 92715d09e83STaniya Das static struct clk_branch cam_cc_csi2phytimer_clk = { 92815d09e83STaniya Das .halt_reg = 0x5064, 92915d09e83STaniya Das .halt_check = BRANCH_HALT, 93015d09e83STaniya Das .clkr = { 93115d09e83STaniya Das .enable_reg = 0x5064, 93215d09e83STaniya Das .enable_mask = BIT(0), 93315d09e83STaniya Das .hw.init = &(struct clk_init_data){ 93415d09e83STaniya Das .name = "cam_cc_csi2phytimer_clk", 93515d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 93615d09e83STaniya Das .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, 93715d09e83STaniya Das }, 93815d09e83STaniya Das .num_parents = 1, 93915d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 94015d09e83STaniya Das .ops = &clk_branch2_ops, 94115d09e83STaniya Das }, 94215d09e83STaniya Das }, 94315d09e83STaniya Das }; 94415d09e83STaniya Das 94515d09e83STaniya Das static struct clk_branch cam_cc_csi3phytimer_clk = { 94615d09e83STaniya Das .halt_reg = 0x5088, 94715d09e83STaniya Das .halt_check = BRANCH_HALT, 94815d09e83STaniya Das .clkr = { 94915d09e83STaniya Das .enable_reg = 0x5088, 95015d09e83STaniya Das .enable_mask = BIT(0), 95115d09e83STaniya Das .hw.init = &(struct clk_init_data){ 95215d09e83STaniya Das .name = "cam_cc_csi3phytimer_clk", 95315d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 95415d09e83STaniya Das .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, 95515d09e83STaniya Das }, 95615d09e83STaniya Das .num_parents = 1, 95715d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 95815d09e83STaniya Das .ops = &clk_branch2_ops, 95915d09e83STaniya Das }, 96015d09e83STaniya Das }, 96115d09e83STaniya Das }; 96215d09e83STaniya Das 96315d09e83STaniya Das static struct clk_branch cam_cc_csiphy0_clk = { 96415d09e83STaniya Das .halt_reg = 0x5020, 96515d09e83STaniya Das .halt_check = BRANCH_HALT, 96615d09e83STaniya Das .clkr = { 96715d09e83STaniya Das .enable_reg = 0x5020, 96815d09e83STaniya Das .enable_mask = BIT(0), 96915d09e83STaniya Das .hw.init = &(struct clk_init_data){ 97015d09e83STaniya Das .name = "cam_cc_csiphy0_clk", 97115d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 97215d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 97315d09e83STaniya Das }, 97415d09e83STaniya Das .num_parents = 1, 97515d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 97615d09e83STaniya Das .ops = &clk_branch2_ops, 97715d09e83STaniya Das }, 97815d09e83STaniya Das }, 97915d09e83STaniya Das }; 98015d09e83STaniya Das 98115d09e83STaniya Das static struct clk_branch cam_cc_csiphy1_clk = { 98215d09e83STaniya Das .halt_reg = 0x5044, 98315d09e83STaniya Das .halt_check = BRANCH_HALT, 98415d09e83STaniya Das .clkr = { 98515d09e83STaniya Das .enable_reg = 0x5044, 98615d09e83STaniya Das .enable_mask = BIT(0), 98715d09e83STaniya Das .hw.init = &(struct clk_init_data){ 98815d09e83STaniya Das .name = "cam_cc_csiphy1_clk", 98915d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 99015d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 99115d09e83STaniya Das }, 99215d09e83STaniya Das .num_parents = 1, 99315d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 99415d09e83STaniya Das .ops = &clk_branch2_ops, 99515d09e83STaniya Das }, 99615d09e83STaniya Das }, 99715d09e83STaniya Das }; 99815d09e83STaniya Das 99915d09e83STaniya Das static struct clk_branch cam_cc_csiphy2_clk = { 100015d09e83STaniya Das .halt_reg = 0x5068, 100115d09e83STaniya Das .halt_check = BRANCH_HALT, 100215d09e83STaniya Das .clkr = { 100315d09e83STaniya Das .enable_reg = 0x5068, 100415d09e83STaniya Das .enable_mask = BIT(0), 100515d09e83STaniya Das .hw.init = &(struct clk_init_data){ 100615d09e83STaniya Das .name = "cam_cc_csiphy2_clk", 100715d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 100815d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 100915d09e83STaniya Das }, 101015d09e83STaniya Das .num_parents = 1, 101115d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 101215d09e83STaniya Das .ops = &clk_branch2_ops, 101315d09e83STaniya Das }, 101415d09e83STaniya Das }, 101515d09e83STaniya Das }; 101615d09e83STaniya Das 101715d09e83STaniya Das static struct clk_branch cam_cc_csiphy3_clk = { 101815d09e83STaniya Das .halt_reg = 0x508c, 101915d09e83STaniya Das .halt_check = BRANCH_HALT, 102015d09e83STaniya Das .clkr = { 102115d09e83STaniya Das .enable_reg = 0x508c, 102215d09e83STaniya Das .enable_mask = BIT(0), 102315d09e83STaniya Das .hw.init = &(struct clk_init_data){ 102415d09e83STaniya Das .name = "cam_cc_csiphy3_clk", 102515d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 102615d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 102715d09e83STaniya Das }, 102815d09e83STaniya Das .num_parents = 1, 102915d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 103015d09e83STaniya Das .ops = &clk_branch2_ops, 103115d09e83STaniya Das }, 103215d09e83STaniya Das }, 103315d09e83STaniya Das }; 103415d09e83STaniya Das 103515d09e83STaniya Das static struct clk_branch cam_cc_icp_clk = { 103615d09e83STaniya Das .halt_reg = 0xb0a0, 103715d09e83STaniya Das .halt_check = BRANCH_HALT, 103815d09e83STaniya Das .clkr = { 103915d09e83STaniya Das .enable_reg = 0xb0a0, 104015d09e83STaniya Das .enable_mask = BIT(0), 104115d09e83STaniya Das .hw.init = &(struct clk_init_data){ 104215d09e83STaniya Das .name = "cam_cc_icp_clk", 104315d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 104415d09e83STaniya Das .hw = &cam_cc_icp_clk_src.clkr.hw, 104515d09e83STaniya Das }, 104615d09e83STaniya Das .num_parents = 1, 104715d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 104815d09e83STaniya Das .ops = &clk_branch2_ops, 104915d09e83STaniya Das }, 105015d09e83STaniya Das }, 105115d09e83STaniya Das }; 105215d09e83STaniya Das 105315d09e83STaniya Das static struct clk_branch cam_cc_ife_0_axi_clk = { 105415d09e83STaniya Das .halt_reg = 0x9080, 105515d09e83STaniya Das .halt_check = BRANCH_HALT, 105615d09e83STaniya Das .clkr = { 105715d09e83STaniya Das .enable_reg = 0x9080, 105815d09e83STaniya Das .enable_mask = BIT(0), 105915d09e83STaniya Das .hw.init = &(struct clk_init_data){ 106015d09e83STaniya Das .name = "cam_cc_ife_0_axi_clk", 106115d09e83STaniya Das .ops = &clk_branch2_ops, 106215d09e83STaniya Das }, 106315d09e83STaniya Das }, 106415d09e83STaniya Das }; 106515d09e83STaniya Das 106615d09e83STaniya Das static struct clk_branch cam_cc_ife_0_clk = { 106715d09e83STaniya Das .halt_reg = 0x9028, 106815d09e83STaniya Das .halt_check = BRANCH_HALT, 106915d09e83STaniya Das .clkr = { 107015d09e83STaniya Das .enable_reg = 0x9028, 107115d09e83STaniya Das .enable_mask = BIT(0), 107215d09e83STaniya Das .hw.init = &(struct clk_init_data){ 107315d09e83STaniya Das .name = "cam_cc_ife_0_clk", 107415d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 107515d09e83STaniya Das .hw = &cam_cc_ife_0_clk_src.clkr.hw, 107615d09e83STaniya Das }, 107715d09e83STaniya Das .num_parents = 1, 107815d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 107915d09e83STaniya Das .ops = &clk_branch2_ops, 108015d09e83STaniya Das }, 108115d09e83STaniya Das }, 108215d09e83STaniya Das }; 108315d09e83STaniya Das 108415d09e83STaniya Das static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 108515d09e83STaniya Das .halt_reg = 0x907c, 108615d09e83STaniya Das .halt_check = BRANCH_HALT, 108715d09e83STaniya Das .clkr = { 108815d09e83STaniya Das .enable_reg = 0x907c, 108915d09e83STaniya Das .enable_mask = BIT(0), 109015d09e83STaniya Das .hw.init = &(struct clk_init_data){ 109115d09e83STaniya Das .name = "cam_cc_ife_0_cphy_rx_clk", 109215d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 109315d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 109415d09e83STaniya Das }, 109515d09e83STaniya Das .num_parents = 1, 109615d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 109715d09e83STaniya Das .ops = &clk_branch2_ops, 109815d09e83STaniya Das }, 109915d09e83STaniya Das }, 110015d09e83STaniya Das }; 110115d09e83STaniya Das 110215d09e83STaniya Das static struct clk_branch cam_cc_ife_0_csid_clk = { 110315d09e83STaniya Das .halt_reg = 0x9054, 110415d09e83STaniya Das .halt_check = BRANCH_HALT, 110515d09e83STaniya Das .clkr = { 110615d09e83STaniya Das .enable_reg = 0x9054, 110715d09e83STaniya Das .enable_mask = BIT(0), 110815d09e83STaniya Das .hw.init = &(struct clk_init_data){ 110915d09e83STaniya Das .name = "cam_cc_ife_0_csid_clk", 111015d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 111115d09e83STaniya Das .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw, 111215d09e83STaniya Das }, 111315d09e83STaniya Das .num_parents = 1, 111415d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 111515d09e83STaniya Das .ops = &clk_branch2_ops, 111615d09e83STaniya Das }, 111715d09e83STaniya Das }, 111815d09e83STaniya Das }; 111915d09e83STaniya Das 112015d09e83STaniya Das static struct clk_branch cam_cc_ife_0_dsp_clk = { 112115d09e83STaniya Das .halt_reg = 0x9038, 112215d09e83STaniya Das .halt_check = BRANCH_HALT, 112315d09e83STaniya Das .clkr = { 112415d09e83STaniya Das .enable_reg = 0x9038, 112515d09e83STaniya Das .enable_mask = BIT(0), 112615d09e83STaniya Das .hw.init = &(struct clk_init_data){ 112715d09e83STaniya Das .name = "cam_cc_ife_0_dsp_clk", 112815d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 112915d09e83STaniya Das .hw = &cam_cc_ife_0_clk_src.clkr.hw, 113015d09e83STaniya Das }, 113115d09e83STaniya Das .num_parents = 1, 113215d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 113315d09e83STaniya Das .ops = &clk_branch2_ops, 113415d09e83STaniya Das }, 113515d09e83STaniya Das }, 113615d09e83STaniya Das }; 113715d09e83STaniya Das 113815d09e83STaniya Das static struct clk_branch cam_cc_ife_1_axi_clk = { 113915d09e83STaniya Das .halt_reg = 0xa058, 114015d09e83STaniya Das .halt_check = BRANCH_HALT, 114115d09e83STaniya Das .clkr = { 114215d09e83STaniya Das .enable_reg = 0xa058, 114315d09e83STaniya Das .enable_mask = BIT(0), 114415d09e83STaniya Das .hw.init = &(struct clk_init_data){ 114515d09e83STaniya Das .name = "cam_cc_ife_1_axi_clk", 114615d09e83STaniya Das .ops = &clk_branch2_ops, 114715d09e83STaniya Das }, 114815d09e83STaniya Das }, 114915d09e83STaniya Das }; 115015d09e83STaniya Das 115115d09e83STaniya Das static struct clk_branch cam_cc_ife_1_clk = { 115215d09e83STaniya Das .halt_reg = 0xa028, 115315d09e83STaniya Das .halt_check = BRANCH_HALT, 115415d09e83STaniya Das .clkr = { 115515d09e83STaniya Das .enable_reg = 0xa028, 115615d09e83STaniya Das .enable_mask = BIT(0), 115715d09e83STaniya Das .hw.init = &(struct clk_init_data){ 115815d09e83STaniya Das .name = "cam_cc_ife_1_clk", 115915d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 116015d09e83STaniya Das .hw = &cam_cc_ife_1_clk_src.clkr.hw, 116115d09e83STaniya Das }, 116215d09e83STaniya Das .num_parents = 1, 116315d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 116415d09e83STaniya Das .ops = &clk_branch2_ops, 116515d09e83STaniya Das }, 116615d09e83STaniya Das }, 116715d09e83STaniya Das }; 116815d09e83STaniya Das 116915d09e83STaniya Das static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 117015d09e83STaniya Das .halt_reg = 0xa054, 117115d09e83STaniya Das .halt_check = BRANCH_HALT, 117215d09e83STaniya Das .clkr = { 117315d09e83STaniya Das .enable_reg = 0xa054, 117415d09e83STaniya Das .enable_mask = BIT(0), 117515d09e83STaniya Das .hw.init = &(struct clk_init_data){ 117615d09e83STaniya Das .name = "cam_cc_ife_1_cphy_rx_clk", 117715d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 117815d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 117915d09e83STaniya Das }, 118015d09e83STaniya Das .num_parents = 1, 118115d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 118215d09e83STaniya Das .ops = &clk_branch2_ops, 118315d09e83STaniya Das }, 118415d09e83STaniya Das }, 118515d09e83STaniya Das }; 118615d09e83STaniya Das 118715d09e83STaniya Das static struct clk_branch cam_cc_ife_1_csid_clk = { 118815d09e83STaniya Das .halt_reg = 0xa04c, 118915d09e83STaniya Das .halt_check = BRANCH_HALT, 119015d09e83STaniya Das .clkr = { 119115d09e83STaniya Das .enable_reg = 0xa04c, 119215d09e83STaniya Das .enable_mask = BIT(0), 119315d09e83STaniya Das .hw.init = &(struct clk_init_data){ 119415d09e83STaniya Das .name = "cam_cc_ife_1_csid_clk", 119515d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 119615d09e83STaniya Das .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw, 119715d09e83STaniya Das }, 119815d09e83STaniya Das .num_parents = 1, 119915d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 120015d09e83STaniya Das .ops = &clk_branch2_ops, 120115d09e83STaniya Das }, 120215d09e83STaniya Das }, 120315d09e83STaniya Das }; 120415d09e83STaniya Das 120515d09e83STaniya Das static struct clk_branch cam_cc_ife_1_dsp_clk = { 120615d09e83STaniya Das .halt_reg = 0xa030, 120715d09e83STaniya Das .halt_check = BRANCH_HALT, 120815d09e83STaniya Das .clkr = { 120915d09e83STaniya Das .enable_reg = 0xa030, 121015d09e83STaniya Das .enable_mask = BIT(0), 121115d09e83STaniya Das .hw.init = &(struct clk_init_data){ 121215d09e83STaniya Das .name = "cam_cc_ife_1_dsp_clk", 121315d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 121415d09e83STaniya Das .hw = &cam_cc_ife_1_clk_src.clkr.hw, 121515d09e83STaniya Das }, 121615d09e83STaniya Das .num_parents = 1, 121715d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 121815d09e83STaniya Das .ops = &clk_branch2_ops, 121915d09e83STaniya Das }, 122015d09e83STaniya Das }, 122115d09e83STaniya Das }; 122215d09e83STaniya Das 122315d09e83STaniya Das static struct clk_branch cam_cc_ife_lite_clk = { 122415d09e83STaniya Das .halt_reg = 0xb01c, 122515d09e83STaniya Das .halt_check = BRANCH_HALT, 122615d09e83STaniya Das .clkr = { 122715d09e83STaniya Das .enable_reg = 0xb01c, 122815d09e83STaniya Das .enable_mask = BIT(0), 122915d09e83STaniya Das .hw.init = &(struct clk_init_data){ 123015d09e83STaniya Das .name = "cam_cc_ife_lite_clk", 123115d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 123215d09e83STaniya Das .hw = &cam_cc_ife_lite_clk_src.clkr.hw, 123315d09e83STaniya Das }, 123415d09e83STaniya Das .num_parents = 1, 123515d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 123615d09e83STaniya Das .ops = &clk_branch2_ops, 123715d09e83STaniya Das }, 123815d09e83STaniya Das }, 123915d09e83STaniya Das }; 124015d09e83STaniya Das 124115d09e83STaniya Das static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 124215d09e83STaniya Das .halt_reg = 0xb044, 124315d09e83STaniya Das .halt_check = BRANCH_HALT, 124415d09e83STaniya Das .clkr = { 124515d09e83STaniya Das .enable_reg = 0xb044, 124615d09e83STaniya Das .enable_mask = BIT(0), 124715d09e83STaniya Das .hw.init = &(struct clk_init_data){ 124815d09e83STaniya Das .name = "cam_cc_ife_lite_cphy_rx_clk", 124915d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 125015d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 125115d09e83STaniya Das }, 125215d09e83STaniya Das .num_parents = 1, 125315d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 125415d09e83STaniya Das .ops = &clk_branch2_ops, 125515d09e83STaniya Das }, 125615d09e83STaniya Das }, 125715d09e83STaniya Das }; 125815d09e83STaniya Das 125915d09e83STaniya Das static struct clk_branch cam_cc_ife_lite_csid_clk = { 126015d09e83STaniya Das .halt_reg = 0xb03c, 126115d09e83STaniya Das .halt_check = BRANCH_HALT, 126215d09e83STaniya Das .clkr = { 126315d09e83STaniya Das .enable_reg = 0xb03c, 126415d09e83STaniya Das .enable_mask = BIT(0), 126515d09e83STaniya Das .hw.init = &(struct clk_init_data){ 126615d09e83STaniya Das .name = "cam_cc_ife_lite_csid_clk", 126715d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 126815d09e83STaniya Das .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw, 126915d09e83STaniya Das }, 127015d09e83STaniya Das .num_parents = 1, 127115d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 127215d09e83STaniya Das .ops = &clk_branch2_ops, 127315d09e83STaniya Das }, 127415d09e83STaniya Das }, 127515d09e83STaniya Das }; 127615d09e83STaniya Das 127715d09e83STaniya Das static struct clk_branch cam_cc_ipe_0_ahb_clk = { 127815d09e83STaniya Das .halt_reg = 0x7040, 127915d09e83STaniya Das .halt_check = BRANCH_HALT, 128015d09e83STaniya Das .clkr = { 128115d09e83STaniya Das .enable_reg = 0x7040, 128215d09e83STaniya Das .enable_mask = BIT(0), 128315d09e83STaniya Das .hw.init = &(struct clk_init_data){ 128415d09e83STaniya Das .name = "cam_cc_ipe_0_ahb_clk", 128515d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 128615d09e83STaniya Das .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 128715d09e83STaniya Das }, 128815d09e83STaniya Das .num_parents = 1, 128915d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 129015d09e83STaniya Das .ops = &clk_branch2_ops, 129115d09e83STaniya Das }, 129215d09e83STaniya Das }, 129315d09e83STaniya Das }; 129415d09e83STaniya Das 129515d09e83STaniya Das static struct clk_branch cam_cc_ipe_0_areg_clk = { 129615d09e83STaniya Das .halt_reg = 0x703c, 129715d09e83STaniya Das .halt_check = BRANCH_HALT, 129815d09e83STaniya Das .clkr = { 129915d09e83STaniya Das .enable_reg = 0x703c, 130015d09e83STaniya Das .enable_mask = BIT(0), 130115d09e83STaniya Das .hw.init = &(struct clk_init_data){ 130215d09e83STaniya Das .name = "cam_cc_ipe_0_areg_clk", 130315d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 130415d09e83STaniya Das .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, 130515d09e83STaniya Das }, 130615d09e83STaniya Das .num_parents = 1, 130715d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 130815d09e83STaniya Das .ops = &clk_branch2_ops, 130915d09e83STaniya Das }, 131015d09e83STaniya Das }, 131115d09e83STaniya Das }; 131215d09e83STaniya Das 131315d09e83STaniya Das static struct clk_branch cam_cc_ipe_0_axi_clk = { 131415d09e83STaniya Das .halt_reg = 0x7038, 131515d09e83STaniya Das .halt_check = BRANCH_HALT, 131615d09e83STaniya Das .clkr = { 131715d09e83STaniya Das .enable_reg = 0x7038, 131815d09e83STaniya Das .enable_mask = BIT(0), 131915d09e83STaniya Das .hw.init = &(struct clk_init_data){ 132015d09e83STaniya Das .name = "cam_cc_ipe_0_axi_clk", 132115d09e83STaniya Das .ops = &clk_branch2_ops, 132215d09e83STaniya Das }, 132315d09e83STaniya Das }, 132415d09e83STaniya Das }; 132515d09e83STaniya Das 132615d09e83STaniya Das static struct clk_branch cam_cc_ipe_0_clk = { 132715d09e83STaniya Das .halt_reg = 0x7028, 132815d09e83STaniya Das .halt_check = BRANCH_HALT, 132915d09e83STaniya Das .clkr = { 133015d09e83STaniya Das .enable_reg = 0x7028, 133115d09e83STaniya Das .enable_mask = BIT(0), 133215d09e83STaniya Das .hw.init = &(struct clk_init_data){ 133315d09e83STaniya Das .name = "cam_cc_ipe_0_clk", 133415d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 133515d09e83STaniya Das .hw = &cam_cc_ipe_0_clk_src.clkr.hw, 133615d09e83STaniya Das }, 133715d09e83STaniya Das .num_parents = 1, 133815d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 133915d09e83STaniya Das .ops = &clk_branch2_ops, 134015d09e83STaniya Das }, 134115d09e83STaniya Das }, 134215d09e83STaniya Das }; 134315d09e83STaniya Das 134415d09e83STaniya Das static struct clk_branch cam_cc_jpeg_clk = { 134515d09e83STaniya Das .halt_reg = 0xb064, 134615d09e83STaniya Das .halt_check = BRANCH_HALT, 134715d09e83STaniya Das .clkr = { 134815d09e83STaniya Das .enable_reg = 0xb064, 134915d09e83STaniya Das .enable_mask = BIT(0), 135015d09e83STaniya Das .hw.init = &(struct clk_init_data){ 135115d09e83STaniya Das .name = "cam_cc_jpeg_clk", 135215d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 135315d09e83STaniya Das .hw = &cam_cc_jpeg_clk_src.clkr.hw, 135415d09e83STaniya Das }, 135515d09e83STaniya Das .num_parents = 1, 135615d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 135715d09e83STaniya Das .ops = &clk_branch2_ops, 135815d09e83STaniya Das }, 135915d09e83STaniya Das }, 136015d09e83STaniya Das }; 136115d09e83STaniya Das 136215d09e83STaniya Das static struct clk_branch cam_cc_lrme_clk = { 136315d09e83STaniya Das .halt_reg = 0xb110, 136415d09e83STaniya Das .halt_check = BRANCH_HALT, 136515d09e83STaniya Das .clkr = { 136615d09e83STaniya Das .enable_reg = 0xb110, 136715d09e83STaniya Das .enable_mask = BIT(0), 136815d09e83STaniya Das .hw.init = &(struct clk_init_data){ 136915d09e83STaniya Das .name = "cam_cc_lrme_clk", 137015d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 137115d09e83STaniya Das .hw = &cam_cc_lrme_clk_src.clkr.hw, 137215d09e83STaniya Das }, 137315d09e83STaniya Das .num_parents = 1, 137415d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 137515d09e83STaniya Das .ops = &clk_branch2_ops, 137615d09e83STaniya Das }, 137715d09e83STaniya Das }, 137815d09e83STaniya Das }; 137915d09e83STaniya Das 138015d09e83STaniya Das static struct clk_branch cam_cc_mclk0_clk = { 138115d09e83STaniya Das .halt_reg = 0x401c, 138215d09e83STaniya Das .halt_check = BRANCH_HALT, 138315d09e83STaniya Das .clkr = { 138415d09e83STaniya Das .enable_reg = 0x401c, 138515d09e83STaniya Das .enable_mask = BIT(0), 138615d09e83STaniya Das .hw.init = &(struct clk_init_data){ 138715d09e83STaniya Das .name = "cam_cc_mclk0_clk", 138815d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 138915d09e83STaniya Das .hw = &cam_cc_mclk0_clk_src.clkr.hw, 139015d09e83STaniya Das }, 139115d09e83STaniya Das .num_parents = 1, 139215d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 139315d09e83STaniya Das .ops = &clk_branch2_ops, 139415d09e83STaniya Das }, 139515d09e83STaniya Das }, 139615d09e83STaniya Das }; 139715d09e83STaniya Das 139815d09e83STaniya Das static struct clk_branch cam_cc_mclk1_clk = { 139915d09e83STaniya Das .halt_reg = 0x403c, 140015d09e83STaniya Das .halt_check = BRANCH_HALT, 140115d09e83STaniya Das .clkr = { 140215d09e83STaniya Das .enable_reg = 0x403c, 140315d09e83STaniya Das .enable_mask = BIT(0), 140415d09e83STaniya Das .hw.init = &(struct clk_init_data){ 140515d09e83STaniya Das .name = "cam_cc_mclk1_clk", 140615d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 140715d09e83STaniya Das .hw = &cam_cc_mclk1_clk_src.clkr.hw, 140815d09e83STaniya Das }, 140915d09e83STaniya Das .num_parents = 1, 141015d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 141115d09e83STaniya Das .ops = &clk_branch2_ops, 141215d09e83STaniya Das }, 141315d09e83STaniya Das }, 141415d09e83STaniya Das }; 141515d09e83STaniya Das 141615d09e83STaniya Das static struct clk_branch cam_cc_mclk2_clk = { 141715d09e83STaniya Das .halt_reg = 0x405c, 141815d09e83STaniya Das .halt_check = BRANCH_HALT, 141915d09e83STaniya Das .clkr = { 142015d09e83STaniya Das .enable_reg = 0x405c, 142115d09e83STaniya Das .enable_mask = BIT(0), 142215d09e83STaniya Das .hw.init = &(struct clk_init_data){ 142315d09e83STaniya Das .name = "cam_cc_mclk2_clk", 142415d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 142515d09e83STaniya Das .hw = &cam_cc_mclk2_clk_src.clkr.hw, 142615d09e83STaniya Das }, 142715d09e83STaniya Das .num_parents = 1, 142815d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 142915d09e83STaniya Das .ops = &clk_branch2_ops, 143015d09e83STaniya Das }, 143115d09e83STaniya Das }, 143215d09e83STaniya Das }; 143315d09e83STaniya Das 143415d09e83STaniya Das static struct clk_branch cam_cc_mclk3_clk = { 143515d09e83STaniya Das .halt_reg = 0x407c, 143615d09e83STaniya Das .halt_check = BRANCH_HALT, 143715d09e83STaniya Das .clkr = { 143815d09e83STaniya Das .enable_reg = 0x407c, 143915d09e83STaniya Das .enable_mask = BIT(0), 144015d09e83STaniya Das .hw.init = &(struct clk_init_data){ 144115d09e83STaniya Das .name = "cam_cc_mclk3_clk", 144215d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 144315d09e83STaniya Das .hw = &cam_cc_mclk3_clk_src.clkr.hw, 144415d09e83STaniya Das }, 144515d09e83STaniya Das .num_parents = 1, 144615d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 144715d09e83STaniya Das .ops = &clk_branch2_ops, 144815d09e83STaniya Das }, 144915d09e83STaniya Das }, 145015d09e83STaniya Das }; 145115d09e83STaniya Das 145215d09e83STaniya Das static struct clk_branch cam_cc_mclk4_clk = { 145315d09e83STaniya Das .halt_reg = 0x409c, 145415d09e83STaniya Das .halt_check = BRANCH_HALT, 145515d09e83STaniya Das .clkr = { 145615d09e83STaniya Das .enable_reg = 0x409c, 145715d09e83STaniya Das .enable_mask = BIT(0), 145815d09e83STaniya Das .hw.init = &(struct clk_init_data){ 145915d09e83STaniya Das .name = "cam_cc_mclk4_clk", 146015d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 146115d09e83STaniya Das .hw = &cam_cc_mclk4_clk_src.clkr.hw, 146215d09e83STaniya Das }, 146315d09e83STaniya Das .num_parents = 1, 146415d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 146515d09e83STaniya Das .ops = &clk_branch2_ops, 146615d09e83STaniya Das }, 146715d09e83STaniya Das }, 146815d09e83STaniya Das }; 146915d09e83STaniya Das 147015d09e83STaniya Das static struct clk_branch cam_cc_soc_ahb_clk = { 147115d09e83STaniya Das .halt_reg = 0xb140, 147215d09e83STaniya Das .halt_check = BRANCH_HALT, 147315d09e83STaniya Das .clkr = { 147415d09e83STaniya Das .enable_reg = 0xb140, 147515d09e83STaniya Das .enable_mask = BIT(0), 147615d09e83STaniya Das .hw.init = &(struct clk_init_data){ 147715d09e83STaniya Das .name = "cam_cc_soc_ahb_clk", 147815d09e83STaniya Das .ops = &clk_branch2_ops, 147915d09e83STaniya Das }, 148015d09e83STaniya Das }, 148115d09e83STaniya Das }; 148215d09e83STaniya Das 148315d09e83STaniya Das static struct clk_branch cam_cc_sys_tmr_clk = { 148415d09e83STaniya Das .halt_reg = 0xb0a8, 148515d09e83STaniya Das .halt_check = BRANCH_HALT, 148615d09e83STaniya Das .clkr = { 148715d09e83STaniya Das .enable_reg = 0xb0a8, 148815d09e83STaniya Das .enable_mask = BIT(0), 148915d09e83STaniya Das .hw.init = &(struct clk_init_data){ 149015d09e83STaniya Das .name = "cam_cc_sys_tmr_clk", 149115d09e83STaniya Das .ops = &clk_branch2_ops, 149215d09e83STaniya Das }, 149315d09e83STaniya Das }, 149415d09e83STaniya Das }; 149515d09e83STaniya Das 149615d09e83STaniya Das static struct gdsc bps_gdsc = { 149715d09e83STaniya Das .gdscr = 0x6004, 149815d09e83STaniya Das .pd = { 149915d09e83STaniya Das .name = "bps_gdsc", 150015d09e83STaniya Das }, 150115d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 150215d09e83STaniya Das .flags = HW_CTRL, 150315d09e83STaniya Das }; 150415d09e83STaniya Das 150515d09e83STaniya Das static struct gdsc ife_0_gdsc = { 150615d09e83STaniya Das .gdscr = 0x9004, 150715d09e83STaniya Das .pd = { 150815d09e83STaniya Das .name = "ife_0_gdsc", 150915d09e83STaniya Das }, 151015d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 151115d09e83STaniya Das }; 151215d09e83STaniya Das 151315d09e83STaniya Das static struct gdsc ife_1_gdsc = { 151415d09e83STaniya Das .gdscr = 0xa004, 151515d09e83STaniya Das .pd = { 151615d09e83STaniya Das .name = "ife_1_gdsc", 151715d09e83STaniya Das }, 151815d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 151915d09e83STaniya Das }; 152015d09e83STaniya Das 152115d09e83STaniya Das static struct gdsc ipe_0_gdsc = { 152215d09e83STaniya Das .gdscr = 0x7004, 152315d09e83STaniya Das .pd = { 152415d09e83STaniya Das .name = "ipe_0_gdsc", 152515d09e83STaniya Das }, 152615d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 152715d09e83STaniya Das .flags = HW_CTRL, 152815d09e83STaniya Das }; 152915d09e83STaniya Das 153015d09e83STaniya Das static struct gdsc titan_top_gdsc = { 153115d09e83STaniya Das .gdscr = 0xb134, 153215d09e83STaniya Das .pd = { 153315d09e83STaniya Das .name = "titan_top_gdsc", 153415d09e83STaniya Das }, 153515d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 153615d09e83STaniya Das }; 153715d09e83STaniya Das 153815d09e83STaniya Das static struct clk_hw *cam_cc_sc7180_hws[] = { 153915d09e83STaniya Das [CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw, 154015d09e83STaniya Das }; 154115d09e83STaniya Das 154215d09e83STaniya Das static struct clk_regmap *cam_cc_sc7180_clocks[] = { 154315d09e83STaniya Das [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 154415d09e83STaniya Das [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 154515d09e83STaniya Das [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 154615d09e83STaniya Das [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 154715d09e83STaniya Das [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 154815d09e83STaniya Das [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 154915d09e83STaniya Das [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 155015d09e83STaniya Das [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 155115d09e83STaniya Das [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 155215d09e83STaniya Das [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 155315d09e83STaniya Das [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 155415d09e83STaniya Das [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 155515d09e83STaniya Das [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 155615d09e83STaniya Das [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 155715d09e83STaniya Das [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 155815d09e83STaniya Das [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 155915d09e83STaniya Das [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 156015d09e83STaniya Das [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 156115d09e83STaniya Das [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 156215d09e83STaniya Das [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 156315d09e83STaniya Das [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 156415d09e83STaniya Das [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 156515d09e83STaniya Das [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 156615d09e83STaniya Das [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 156715d09e83STaniya Das [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 156815d09e83STaniya Das [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 156915d09e83STaniya Das [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 157015d09e83STaniya Das [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 157115d09e83STaniya Das [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 157215d09e83STaniya Das [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 157315d09e83STaniya Das [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 157415d09e83STaniya Das [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 157515d09e83STaniya Das [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 157615d09e83STaniya Das [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 157715d09e83STaniya Das [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 157815d09e83STaniya Das [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 157915d09e83STaniya Das [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 158015d09e83STaniya Das [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 158115d09e83STaniya Das [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 158215d09e83STaniya Das [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 158315d09e83STaniya Das [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 158415d09e83STaniya Das [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 158515d09e83STaniya Das [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 158615d09e83STaniya Das [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 158715d09e83STaniya Das [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 158815d09e83STaniya Das [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 158915d09e83STaniya Das [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 159015d09e83STaniya Das [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 159115d09e83STaniya Das [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 159215d09e83STaniya Das [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 159315d09e83STaniya Das [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 159415d09e83STaniya Das [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 159515d09e83STaniya Das [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 159615d09e83STaniya Das [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 159715d09e83STaniya Das [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 159815d09e83STaniya Das [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 159915d09e83STaniya Das [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 160015d09e83STaniya Das [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 160115d09e83STaniya Das [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 160215d09e83STaniya Das [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 160315d09e83STaniya Das [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 160415d09e83STaniya Das [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 160515d09e83STaniya Das [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 160615d09e83STaniya Das [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 160715d09e83STaniya Das [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 160815d09e83STaniya Das [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 160915d09e83STaniya Das [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 161015d09e83STaniya Das [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 161115d09e83STaniya Das [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 161215d09e83STaniya Das [CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr, 161315d09e83STaniya Das [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 161415d09e83STaniya Das [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 161515d09e83STaniya Das [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 161615d09e83STaniya Das [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 161715d09e83STaniya Das }; 161815d09e83STaniya Das static struct gdsc *cam_cc_sc7180_gdscs[] = { 161915d09e83STaniya Das [BPS_GDSC] = &bps_gdsc, 162015d09e83STaniya Das [IFE_0_GDSC] = &ife_0_gdsc, 162115d09e83STaniya Das [IFE_1_GDSC] = &ife_1_gdsc, 162215d09e83STaniya Das [IPE_0_GDSC] = &ipe_0_gdsc, 162315d09e83STaniya Das [TITAN_TOP_GDSC] = &titan_top_gdsc, 162415d09e83STaniya Das }; 162515d09e83STaniya Das 162615d09e83STaniya Das static const struct regmap_config cam_cc_sc7180_regmap_config = { 162715d09e83STaniya Das .reg_bits = 32, 162815d09e83STaniya Das .reg_stride = 4, 162915d09e83STaniya Das .val_bits = 32, 163015d09e83STaniya Das .max_register = 0xd028, 163115d09e83STaniya Das .fast_io = true, 163215d09e83STaniya Das }; 163315d09e83STaniya Das 163415d09e83STaniya Das static const struct qcom_cc_desc cam_cc_sc7180_desc = { 163515d09e83STaniya Das .config = &cam_cc_sc7180_regmap_config, 163615d09e83STaniya Das .clk_hws = cam_cc_sc7180_hws, 163715d09e83STaniya Das .num_clk_hws = ARRAY_SIZE(cam_cc_sc7180_hws), 163815d09e83STaniya Das .clks = cam_cc_sc7180_clocks, 163915d09e83STaniya Das .num_clks = ARRAY_SIZE(cam_cc_sc7180_clocks), 164015d09e83STaniya Das .gdscs = cam_cc_sc7180_gdscs, 164115d09e83STaniya Das .num_gdscs = ARRAY_SIZE(cam_cc_sc7180_gdscs), 164215d09e83STaniya Das }; 164315d09e83STaniya Das 164415d09e83STaniya Das static const struct of_device_id cam_cc_sc7180_match_table[] = { 164515d09e83STaniya Das { .compatible = "qcom,sc7180-camcc" }, 164615d09e83STaniya Das { } 164715d09e83STaniya Das }; 164815d09e83STaniya Das MODULE_DEVICE_TABLE(of, cam_cc_sc7180_match_table); 164915d09e83STaniya Das 165015d09e83STaniya Das static int cam_cc_sc7180_probe(struct platform_device *pdev) 165115d09e83STaniya Das { 165215d09e83STaniya Das struct regmap *regmap; 165315d09e83STaniya Das int ret; 165415d09e83STaniya Das 165572cfc73fSDmitry Baryshkov ret = devm_pm_runtime_enable(&pdev->dev); 165672cfc73fSDmitry Baryshkov if (ret < 0) 165772cfc73fSDmitry Baryshkov return ret; 165872cfc73fSDmitry Baryshkov 165972cfc73fSDmitry Baryshkov ret = devm_pm_clk_create(&pdev->dev); 166015d09e83STaniya Das if (ret < 0) 166115d09e83STaniya Das return ret; 166215d09e83STaniya Das 166315d09e83STaniya Das ret = pm_clk_add(&pdev->dev, "xo"); 166415d09e83STaniya Das if (ret < 0) { 166515d09e83STaniya Das dev_err(&pdev->dev, "Failed to acquire XO clock\n"); 166672cfc73fSDmitry Baryshkov return ret; 166715d09e83STaniya Das } 166815d09e83STaniya Das 166915d09e83STaniya Das ret = pm_clk_add(&pdev->dev, "iface"); 167015d09e83STaniya Das if (ret < 0) { 167115d09e83STaniya Das dev_err(&pdev->dev, "Failed to acquire iface clock\n"); 167272cfc73fSDmitry Baryshkov return ret; 167315d09e83STaniya Das } 167415d09e83STaniya Das 16758d402594SStephen Boyd ret = pm_runtime_get(&pdev->dev); 16768d402594SStephen Boyd if (ret) 167772cfc73fSDmitry Baryshkov return ret; 167815d09e83STaniya Das 167915d09e83STaniya Das regmap = qcom_cc_map(pdev, &cam_cc_sc7180_desc); 168015d09e83STaniya Das if (IS_ERR(regmap)) { 168115d09e83STaniya Das ret = PTR_ERR(regmap); 16828d402594SStephen Boyd pm_runtime_put(&pdev->dev); 168372cfc73fSDmitry Baryshkov return ret; 168415d09e83STaniya Das } 168515d09e83STaniya Das 168615d09e83STaniya Das clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 168715d09e83STaniya Das clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 168815d09e83STaniya Das clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 168915d09e83STaniya Das clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 169015d09e83STaniya Das 169115d09e83STaniya Das ret = qcom_cc_really_probe(pdev, &cam_cc_sc7180_desc, regmap); 16928d402594SStephen Boyd pm_runtime_put(&pdev->dev); 169315d09e83STaniya Das if (ret < 0) { 169415d09e83STaniya Das dev_err(&pdev->dev, "Failed to register CAM CC clocks\n"); 169572cfc73fSDmitry Baryshkov return ret; 169615d09e83STaniya Das } 169715d09e83STaniya Das 169815d09e83STaniya Das return 0; 169915d09e83STaniya Das } 170015d09e83STaniya Das 170115d09e83STaniya Das static const struct dev_pm_ops cam_cc_pm_ops = { 170215d09e83STaniya Das SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 170315d09e83STaniya Das }; 170415d09e83STaniya Das 170515d09e83STaniya Das static struct platform_driver cam_cc_sc7180_driver = { 170615d09e83STaniya Das .probe = cam_cc_sc7180_probe, 170715d09e83STaniya Das .driver = { 170815d09e83STaniya Das .name = "cam_cc-sc7180", 170915d09e83STaniya Das .of_match_table = cam_cc_sc7180_match_table, 171015d09e83STaniya Das .pm = &cam_cc_pm_ops, 171115d09e83STaniya Das }, 171215d09e83STaniya Das }; 171315d09e83STaniya Das 171415d09e83STaniya Das static int __init cam_cc_sc7180_init(void) 171515d09e83STaniya Das { 171615d09e83STaniya Das return platform_driver_register(&cam_cc_sc7180_driver); 171715d09e83STaniya Das } 171815d09e83STaniya Das subsys_initcall(cam_cc_sc7180_init); 171915d09e83STaniya Das 172015d09e83STaniya Das static void __exit cam_cc_sc7180_exit(void) 172115d09e83STaniya Das { 172215d09e83STaniya Das platform_driver_unregister(&cam_cc_sc7180_driver); 172315d09e83STaniya Das } 172415d09e83STaniya Das module_exit(cam_cc_sc7180_exit); 172515d09e83STaniya Das 172615d09e83STaniya Das MODULE_DESCRIPTION("QTI CAM_CC SC7180 Driver"); 172715d09e83STaniya Das MODULE_LICENSE("GPL v2"); 1728