1*15d09e83STaniya Das // SPDX-License-Identifier: GPL-2.0-only 2*15d09e83STaniya Das /* 3*15d09e83STaniya Das * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4*15d09e83STaniya Das */ 5*15d09e83STaniya Das 6*15d09e83STaniya Das #include <linux/clk-provider.h> 7*15d09e83STaniya Das #include <linux/err.h> 8*15d09e83STaniya Das #include <linux/module.h> 9*15d09e83STaniya Das #include <linux/of.h> 10*15d09e83STaniya Das #include <linux/of_device.h> 11*15d09e83STaniya Das #include <linux/pm_clock.h> 12*15d09e83STaniya Das #include <linux/pm_runtime.h> 13*15d09e83STaniya Das #include <linux/regmap.h> 14*15d09e83STaniya Das 15*15d09e83STaniya Das #include <dt-bindings/clock/qcom,camcc-sc7180.h> 16*15d09e83STaniya Das 17*15d09e83STaniya Das #include "clk-alpha-pll.h" 18*15d09e83STaniya Das #include "clk-branch.h" 19*15d09e83STaniya Das #include "clk-rcg.h" 20*15d09e83STaniya Das #include "clk-regmap.h" 21*15d09e83STaniya Das #include "common.h" 22*15d09e83STaniya Das #include "gdsc.h" 23*15d09e83STaniya Das #include "reset.h" 24*15d09e83STaniya Das 25*15d09e83STaniya Das enum { 26*15d09e83STaniya Das P_BI_TCXO, 27*15d09e83STaniya Das P_CAM_CC_PLL0_OUT_EVEN, 28*15d09e83STaniya Das P_CAM_CC_PLL1_OUT_EVEN, 29*15d09e83STaniya Das P_CAM_CC_PLL2_OUT_AUX, 30*15d09e83STaniya Das P_CAM_CC_PLL2_OUT_EARLY, 31*15d09e83STaniya Das P_CAM_CC_PLL3_OUT_MAIN, 32*15d09e83STaniya Das P_CORE_BI_PLL_TEST_SE, 33*15d09e83STaniya Das }; 34*15d09e83STaniya Das 35*15d09e83STaniya Das static const struct pll_vco agera_vco[] = { 36*15d09e83STaniya Das { 600000000, 3300000000UL, 0 }, 37*15d09e83STaniya Das }; 38*15d09e83STaniya Das 39*15d09e83STaniya Das static const struct pll_vco fabia_vco[] = { 40*15d09e83STaniya Das { 249600000, 2000000000UL, 0 }, 41*15d09e83STaniya Das }; 42*15d09e83STaniya Das 43*15d09e83STaniya Das /* 600MHz configuration */ 44*15d09e83STaniya Das static const struct alpha_pll_config cam_cc_pll0_config = { 45*15d09e83STaniya Das .l = 0x1f, 46*15d09e83STaniya Das .alpha = 0x4000, 47*15d09e83STaniya Das .config_ctl_val = 0x20485699, 48*15d09e83STaniya Das .config_ctl_hi_val = 0x00002067, 49*15d09e83STaniya Das .test_ctl_val = 0x40000000, 50*15d09e83STaniya Das .user_ctl_hi_val = 0x00004805, 51*15d09e83STaniya Das .user_ctl_val = 0x00000001, 52*15d09e83STaniya Das }; 53*15d09e83STaniya Das 54*15d09e83STaniya Das static struct clk_alpha_pll cam_cc_pll0 = { 55*15d09e83STaniya Das .offset = 0x0, 56*15d09e83STaniya Das .vco_table = fabia_vco, 57*15d09e83STaniya Das .num_vco = ARRAY_SIZE(fabia_vco), 58*15d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 59*15d09e83STaniya Das .clkr = { 60*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 61*15d09e83STaniya Das .name = "cam_cc_pll0", 62*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 63*15d09e83STaniya Das .fw_name = "bi_tcxo", 64*15d09e83STaniya Das }, 65*15d09e83STaniya Das .num_parents = 1, 66*15d09e83STaniya Das .ops = &clk_alpha_pll_fabia_ops, 67*15d09e83STaniya Das }, 68*15d09e83STaniya Das }, 69*15d09e83STaniya Das }; 70*15d09e83STaniya Das 71*15d09e83STaniya Das /* 860MHz configuration */ 72*15d09e83STaniya Das static const struct alpha_pll_config cam_cc_pll1_config = { 73*15d09e83STaniya Das .l = 0x2a, 74*15d09e83STaniya Das .alpha = 0x1555, 75*15d09e83STaniya Das .config_ctl_val = 0x20485699, 76*15d09e83STaniya Das .config_ctl_hi_val = 0x00002067, 77*15d09e83STaniya Das .test_ctl_val = 0x40000000, 78*15d09e83STaniya Das .user_ctl_hi_val = 0x00004805, 79*15d09e83STaniya Das }; 80*15d09e83STaniya Das 81*15d09e83STaniya Das static struct clk_alpha_pll cam_cc_pll1 = { 82*15d09e83STaniya Das .offset = 0x1000, 83*15d09e83STaniya Das .vco_table = fabia_vco, 84*15d09e83STaniya Das .num_vco = ARRAY_SIZE(fabia_vco), 85*15d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 86*15d09e83STaniya Das .clkr = { 87*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 88*15d09e83STaniya Das .name = "cam_cc_pll1", 89*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 90*15d09e83STaniya Das .fw_name = "bi_tcxo", 91*15d09e83STaniya Das }, 92*15d09e83STaniya Das .num_parents = 1, 93*15d09e83STaniya Das .ops = &clk_alpha_pll_fabia_ops, 94*15d09e83STaniya Das }, 95*15d09e83STaniya Das }, 96*15d09e83STaniya Das }; 97*15d09e83STaniya Das 98*15d09e83STaniya Das /* 1920MHz configuration */ 99*15d09e83STaniya Das static const struct alpha_pll_config cam_cc_pll2_config = { 100*15d09e83STaniya Das .l = 0x64, 101*15d09e83STaniya Das .config_ctl_val = 0x20000800, 102*15d09e83STaniya Das .config_ctl_hi_val = 0x400003D2, 103*15d09e83STaniya Das .test_ctl_val = 0x04000400, 104*15d09e83STaniya Das .test_ctl_hi_val = 0x00004000, 105*15d09e83STaniya Das .user_ctl_val = 0x0000030F, 106*15d09e83STaniya Das }; 107*15d09e83STaniya Das 108*15d09e83STaniya Das static struct clk_alpha_pll cam_cc_pll2 = { 109*15d09e83STaniya Das .offset = 0x2000, 110*15d09e83STaniya Das .vco_table = agera_vco, 111*15d09e83STaniya Das .num_vco = ARRAY_SIZE(agera_vco), 112*15d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 113*15d09e83STaniya Das .clkr = { 114*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 115*15d09e83STaniya Das .name = "cam_cc_pll2", 116*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 117*15d09e83STaniya Das .fw_name = "bi_tcxo", 118*15d09e83STaniya Das }, 119*15d09e83STaniya Das .num_parents = 1, 120*15d09e83STaniya Das .ops = &clk_alpha_pll_agera_ops, 121*15d09e83STaniya Das }, 122*15d09e83STaniya Das }, 123*15d09e83STaniya Das }; 124*15d09e83STaniya Das 125*15d09e83STaniya Das static struct clk_fixed_factor cam_cc_pll2_out_early = { 126*15d09e83STaniya Das .mult = 1, 127*15d09e83STaniya Das .div = 2, 128*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 129*15d09e83STaniya Das .name = "cam_cc_pll2_out_early", 130*15d09e83STaniya Das .parent_names = (const char *[]){ "cam_cc_pll2" }, 131*15d09e83STaniya Das .num_parents = 1, 132*15d09e83STaniya Das .ops = &clk_fixed_factor_ops, 133*15d09e83STaniya Das }, 134*15d09e83STaniya Das }; 135*15d09e83STaniya Das 136*15d09e83STaniya Das static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = { 137*15d09e83STaniya Das { 0x3, 4 }, 138*15d09e83STaniya Das { } 139*15d09e83STaniya Das }; 140*15d09e83STaniya Das 141*15d09e83STaniya Das static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { 142*15d09e83STaniya Das .offset = 0x2000, 143*15d09e83STaniya Das .post_div_shift = 8, 144*15d09e83STaniya Das .post_div_table = post_div_table_cam_cc_pll2_out_aux, 145*15d09e83STaniya Das .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux), 146*15d09e83STaniya Das .width = 2, 147*15d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], 148*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 149*15d09e83STaniya Das .name = "cam_cc_pll2_out_aux", 150*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 151*15d09e83STaniya Das .hw = &cam_cc_pll2.clkr.hw, 152*15d09e83STaniya Das }, 153*15d09e83STaniya Das .num_parents = 1, 154*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 155*15d09e83STaniya Das .ops = &clk_alpha_pll_postdiv_ops, 156*15d09e83STaniya Das }, 157*15d09e83STaniya Das }; 158*15d09e83STaniya Das 159*15d09e83STaniya Das /* 1080MHz configuration */ 160*15d09e83STaniya Das static const struct alpha_pll_config cam_cc_pll3_config = { 161*15d09e83STaniya Das .l = 0x38, 162*15d09e83STaniya Das .alpha = 0x4000, 163*15d09e83STaniya Das .config_ctl_val = 0x20485699, 164*15d09e83STaniya Das .config_ctl_hi_val = 0x00002067, 165*15d09e83STaniya Das .test_ctl_val = 0x40000000, 166*15d09e83STaniya Das .user_ctl_hi_val = 0x00004805, 167*15d09e83STaniya Das }; 168*15d09e83STaniya Das 169*15d09e83STaniya Das static struct clk_alpha_pll cam_cc_pll3 = { 170*15d09e83STaniya Das .offset = 0x3000, 171*15d09e83STaniya Das .vco_table = fabia_vco, 172*15d09e83STaniya Das .num_vco = ARRAY_SIZE(fabia_vco), 173*15d09e83STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 174*15d09e83STaniya Das .clkr = { 175*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 176*15d09e83STaniya Das .name = "cam_cc_pll3", 177*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 178*15d09e83STaniya Das .fw_name = "bi_tcxo", 179*15d09e83STaniya Das }, 180*15d09e83STaniya Das .num_parents = 1, 181*15d09e83STaniya Das .ops = &clk_alpha_pll_fabia_ops, 182*15d09e83STaniya Das }, 183*15d09e83STaniya Das }, 184*15d09e83STaniya Das }; 185*15d09e83STaniya Das 186*15d09e83STaniya Das static const struct parent_map cam_cc_parent_map_0[] = { 187*15d09e83STaniya Das { P_BI_TCXO, 0 }, 188*15d09e83STaniya Das { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 189*15d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 190*15d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 191*15d09e83STaniya Das }; 192*15d09e83STaniya Das 193*15d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_0[] = { 194*15d09e83STaniya Das { .fw_name = "bi_tcxo" }, 195*15d09e83STaniya Das { .hw = &cam_cc_pll1.clkr.hw }, 196*15d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 197*15d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 198*15d09e83STaniya Das }; 199*15d09e83STaniya Das 200*15d09e83STaniya Das static const struct parent_map cam_cc_parent_map_1[] = { 201*15d09e83STaniya Das { P_BI_TCXO, 0 }, 202*15d09e83STaniya Das { P_CAM_CC_PLL2_OUT_AUX, 1 }, 203*15d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 204*15d09e83STaniya Das }; 205*15d09e83STaniya Das 206*15d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_1[] = { 207*15d09e83STaniya Das { .fw_name = "bi_tcxo" }, 208*15d09e83STaniya Das { .hw = &cam_cc_pll2_out_aux.clkr.hw }, 209*15d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 210*15d09e83STaniya Das }; 211*15d09e83STaniya Das 212*15d09e83STaniya Das static const struct parent_map cam_cc_parent_map_2[] = { 213*15d09e83STaniya Das { P_BI_TCXO, 0 }, 214*15d09e83STaniya Das { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 215*15d09e83STaniya Das { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 216*15d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 217*15d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 218*15d09e83STaniya Das }; 219*15d09e83STaniya Das 220*15d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_2[] = { 221*15d09e83STaniya Das { .fw_name = "bi_tcxo" }, 222*15d09e83STaniya Das { .hw = &cam_cc_pll2_out_early.hw }, 223*15d09e83STaniya Das { .hw = &cam_cc_pll3.clkr.hw }, 224*15d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 225*15d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 226*15d09e83STaniya Das }; 227*15d09e83STaniya Das 228*15d09e83STaniya Das static const struct parent_map cam_cc_parent_map_3[] = { 229*15d09e83STaniya Das { P_BI_TCXO, 0 }, 230*15d09e83STaniya Das { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 231*15d09e83STaniya Das { P_CAM_CC_PLL2_OUT_EARLY, 4 }, 232*15d09e83STaniya Das { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 233*15d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 234*15d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 235*15d09e83STaniya Das }; 236*15d09e83STaniya Das 237*15d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_3[] = { 238*15d09e83STaniya Das { .fw_name = "bi_tcxo" }, 239*15d09e83STaniya Das { .hw = &cam_cc_pll1.clkr.hw }, 240*15d09e83STaniya Das { .hw = &cam_cc_pll2_out_early.hw }, 241*15d09e83STaniya Das { .hw = &cam_cc_pll3.clkr.hw }, 242*15d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 243*15d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 244*15d09e83STaniya Das }; 245*15d09e83STaniya Das 246*15d09e83STaniya Das static const struct parent_map cam_cc_parent_map_4[] = { 247*15d09e83STaniya Das { P_BI_TCXO, 0 }, 248*15d09e83STaniya Das { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 249*15d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 250*15d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 251*15d09e83STaniya Das }; 252*15d09e83STaniya Das 253*15d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_4[] = { 254*15d09e83STaniya Das { .fw_name = "bi_tcxo" }, 255*15d09e83STaniya Das { .hw = &cam_cc_pll3.clkr.hw }, 256*15d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 257*15d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 258*15d09e83STaniya Das }; 259*15d09e83STaniya Das 260*15d09e83STaniya Das static const struct parent_map cam_cc_parent_map_5[] = { 261*15d09e83STaniya Das { P_BI_TCXO, 0 }, 262*15d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 263*15d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 264*15d09e83STaniya Das }; 265*15d09e83STaniya Das 266*15d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_5[] = { 267*15d09e83STaniya Das { .fw_name = "bi_tcxo" }, 268*15d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 269*15d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 270*15d09e83STaniya Das }; 271*15d09e83STaniya Das 272*15d09e83STaniya Das static const struct parent_map cam_cc_parent_map_6[] = { 273*15d09e83STaniya Das { P_BI_TCXO, 0 }, 274*15d09e83STaniya Das { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 275*15d09e83STaniya Das { P_CAM_CC_PLL3_OUT_MAIN, 5 }, 276*15d09e83STaniya Das { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 277*15d09e83STaniya Das { P_CORE_BI_PLL_TEST_SE, 7 }, 278*15d09e83STaniya Das }; 279*15d09e83STaniya Das 280*15d09e83STaniya Das static const struct clk_parent_data cam_cc_parent_data_6[] = { 281*15d09e83STaniya Das { .fw_name = "bi_tcxo" }, 282*15d09e83STaniya Das { .hw = &cam_cc_pll1.clkr.hw }, 283*15d09e83STaniya Das { .hw = &cam_cc_pll3.clkr.hw }, 284*15d09e83STaniya Das { .hw = &cam_cc_pll0.clkr.hw }, 285*15d09e83STaniya Das { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 286*15d09e83STaniya Das }; 287*15d09e83STaniya Das 288*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 289*15d09e83STaniya Das F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 290*15d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 291*15d09e83STaniya Das F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 292*15d09e83STaniya Das F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 293*15d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 294*15d09e83STaniya Das { } 295*15d09e83STaniya Das }; 296*15d09e83STaniya Das 297*15d09e83STaniya Das static struct clk_rcg2 cam_cc_bps_clk_src = { 298*15d09e83STaniya Das .cmd_rcgr = 0x6010, 299*15d09e83STaniya Das .mnd_width = 0, 300*15d09e83STaniya Das .hid_width = 5, 301*15d09e83STaniya Das .parent_map = cam_cc_parent_map_2, 302*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_bps_clk_src, 303*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 304*15d09e83STaniya Das .name = "cam_cc_bps_clk_src", 305*15d09e83STaniya Das .parent_data = cam_cc_parent_data_2, 306*15d09e83STaniya Das .num_parents = 5, 307*15d09e83STaniya Das .ops = &clk_rcg2_ops, 308*15d09e83STaniya Das }, 309*15d09e83STaniya Das }; 310*15d09e83STaniya Das 311*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 312*15d09e83STaniya Das F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 313*15d09e83STaniya Das F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 314*15d09e83STaniya Das F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 315*15d09e83STaniya Das { } 316*15d09e83STaniya Das }; 317*15d09e83STaniya Das 318*15d09e83STaniya Das static struct clk_rcg2 cam_cc_cci_0_clk_src = { 319*15d09e83STaniya Das .cmd_rcgr = 0xb0d8, 320*15d09e83STaniya Das .mnd_width = 8, 321*15d09e83STaniya Das .hid_width = 5, 322*15d09e83STaniya Das .parent_map = cam_cc_parent_map_5, 323*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 324*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 325*15d09e83STaniya Das .name = "cam_cc_cci_0_clk_src", 326*15d09e83STaniya Das .parent_data = cam_cc_parent_data_5, 327*15d09e83STaniya Das .num_parents = 3, 328*15d09e83STaniya Das .ops = &clk_rcg2_ops, 329*15d09e83STaniya Das }, 330*15d09e83STaniya Das }; 331*15d09e83STaniya Das 332*15d09e83STaniya Das static struct clk_rcg2 cam_cc_cci_1_clk_src = { 333*15d09e83STaniya Das .cmd_rcgr = 0xb14c, 334*15d09e83STaniya Das .mnd_width = 8, 335*15d09e83STaniya Das .hid_width = 5, 336*15d09e83STaniya Das .parent_map = cam_cc_parent_map_5, 337*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 338*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 339*15d09e83STaniya Das .name = "cam_cc_cci_1_clk_src", 340*15d09e83STaniya Das .parent_data = cam_cc_parent_data_5, 341*15d09e83STaniya Das .num_parents = 3, 342*15d09e83STaniya Das .ops = &clk_rcg2_ops, 343*15d09e83STaniya Das }, 344*15d09e83STaniya Das }; 345*15d09e83STaniya Das 346*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 347*15d09e83STaniya Das F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 348*15d09e83STaniya Das F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), 349*15d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 350*15d09e83STaniya Das { } 351*15d09e83STaniya Das }; 352*15d09e83STaniya Das 353*15d09e83STaniya Das static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 354*15d09e83STaniya Das .cmd_rcgr = 0x9064, 355*15d09e83STaniya Das .mnd_width = 0, 356*15d09e83STaniya Das .hid_width = 5, 357*15d09e83STaniya Das .parent_map = cam_cc_parent_map_3, 358*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 359*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 360*15d09e83STaniya Das .name = "cam_cc_cphy_rx_clk_src", 361*15d09e83STaniya Das .parent_data = cam_cc_parent_data_3, 362*15d09e83STaniya Das .num_parents = 6, 363*15d09e83STaniya Das .ops = &clk_rcg2_ops, 364*15d09e83STaniya Das }, 365*15d09e83STaniya Das }; 366*15d09e83STaniya Das 367*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 368*15d09e83STaniya Das F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 369*15d09e83STaniya Das { } 370*15d09e83STaniya Das }; 371*15d09e83STaniya Das 372*15d09e83STaniya Das static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 373*15d09e83STaniya Das .cmd_rcgr = 0x5004, 374*15d09e83STaniya Das .mnd_width = 0, 375*15d09e83STaniya Das .hid_width = 5, 376*15d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 377*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 378*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 379*15d09e83STaniya Das .name = "cam_cc_csi0phytimer_clk_src", 380*15d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 381*15d09e83STaniya Das .num_parents = 4, 382*15d09e83STaniya Das .ops = &clk_rcg2_ops, 383*15d09e83STaniya Das }, 384*15d09e83STaniya Das }; 385*15d09e83STaniya Das 386*15d09e83STaniya Das static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 387*15d09e83STaniya Das .cmd_rcgr = 0x5028, 388*15d09e83STaniya Das .mnd_width = 0, 389*15d09e83STaniya Das .hid_width = 5, 390*15d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 391*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 392*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 393*15d09e83STaniya Das .name = "cam_cc_csi1phytimer_clk_src", 394*15d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 395*15d09e83STaniya Das .num_parents = 4, 396*15d09e83STaniya Das .ops = &clk_rcg2_ops, 397*15d09e83STaniya Das }, 398*15d09e83STaniya Das }; 399*15d09e83STaniya Das 400*15d09e83STaniya Das static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 401*15d09e83STaniya Das .cmd_rcgr = 0x504c, 402*15d09e83STaniya Das .mnd_width = 0, 403*15d09e83STaniya Das .hid_width = 5, 404*15d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 405*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 406*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 407*15d09e83STaniya Das .name = "cam_cc_csi2phytimer_clk_src", 408*15d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 409*15d09e83STaniya Das .num_parents = 4, 410*15d09e83STaniya Das .ops = &clk_rcg2_ops, 411*15d09e83STaniya Das }, 412*15d09e83STaniya Das }; 413*15d09e83STaniya Das 414*15d09e83STaniya Das static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 415*15d09e83STaniya Das .cmd_rcgr = 0x5070, 416*15d09e83STaniya Das .mnd_width = 0, 417*15d09e83STaniya Das .hid_width = 5, 418*15d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 419*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 420*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 421*15d09e83STaniya Das .name = "cam_cc_csi3phytimer_clk_src", 422*15d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 423*15d09e83STaniya Das .num_parents = 4, 424*15d09e83STaniya Das .ops = &clk_rcg2_ops, 425*15d09e83STaniya Das }, 426*15d09e83STaniya Das }; 427*15d09e83STaniya Das 428*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 429*15d09e83STaniya Das F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 430*15d09e83STaniya Das F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 431*15d09e83STaniya Das F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 432*15d09e83STaniya Das F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 433*15d09e83STaniya Das { } 434*15d09e83STaniya Das }; 435*15d09e83STaniya Das 436*15d09e83STaniya Das static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 437*15d09e83STaniya Das .cmd_rcgr = 0x603c, 438*15d09e83STaniya Das .mnd_width = 0, 439*15d09e83STaniya Das .hid_width = 5, 440*15d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 441*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 442*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 443*15d09e83STaniya Das .name = "cam_cc_fast_ahb_clk_src", 444*15d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 445*15d09e83STaniya Das .num_parents = 4, 446*15d09e83STaniya Das .ops = &clk_rcg2_ops, 447*15d09e83STaniya Das }, 448*15d09e83STaniya Das }; 449*15d09e83STaniya Das 450*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 451*15d09e83STaniya Das F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 452*15d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 453*15d09e83STaniya Das F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 454*15d09e83STaniya Das F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 455*15d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 456*15d09e83STaniya Das { } 457*15d09e83STaniya Das }; 458*15d09e83STaniya Das 459*15d09e83STaniya Das static struct clk_rcg2 cam_cc_icp_clk_src = { 460*15d09e83STaniya Das .cmd_rcgr = 0xb088, 461*15d09e83STaniya Das .mnd_width = 0, 462*15d09e83STaniya Das .hid_width = 5, 463*15d09e83STaniya Das .parent_map = cam_cc_parent_map_2, 464*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_icp_clk_src, 465*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 466*15d09e83STaniya Das .name = "cam_cc_icp_clk_src", 467*15d09e83STaniya Das .parent_data = cam_cc_parent_data_2, 468*15d09e83STaniya Das .num_parents = 5, 469*15d09e83STaniya Das .ops = &clk_rcg2_ops, 470*15d09e83STaniya Das }, 471*15d09e83STaniya Das }; 472*15d09e83STaniya Das 473*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 474*15d09e83STaniya Das F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 475*15d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 476*15d09e83STaniya Das F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 477*15d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 478*15d09e83STaniya Das { } 479*15d09e83STaniya Das }; 480*15d09e83STaniya Das 481*15d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_0_clk_src = { 482*15d09e83STaniya Das .cmd_rcgr = 0x9010, 483*15d09e83STaniya Das .mnd_width = 0, 484*15d09e83STaniya Das .hid_width = 5, 485*15d09e83STaniya Das .parent_map = cam_cc_parent_map_4, 486*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 487*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 488*15d09e83STaniya Das .name = "cam_cc_ife_0_clk_src", 489*15d09e83STaniya Das .parent_data = cam_cc_parent_data_4, 490*15d09e83STaniya Das .num_parents = 4, 491*15d09e83STaniya Das .ops = &clk_rcg2_ops, 492*15d09e83STaniya Das }, 493*15d09e83STaniya Das }; 494*15d09e83STaniya Das 495*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 496*15d09e83STaniya Das F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 497*15d09e83STaniya Das F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), 498*15d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 499*15d09e83STaniya Das F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), 500*15d09e83STaniya Das { } 501*15d09e83STaniya Das }; 502*15d09e83STaniya Das 503*15d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 504*15d09e83STaniya Das .cmd_rcgr = 0x903c, 505*15d09e83STaniya Das .mnd_width = 0, 506*15d09e83STaniya Das .hid_width = 5, 507*15d09e83STaniya Das .parent_map = cam_cc_parent_map_3, 508*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 509*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 510*15d09e83STaniya Das .name = "cam_cc_ife_0_csid_clk_src", 511*15d09e83STaniya Das .parent_data = cam_cc_parent_data_3, 512*15d09e83STaniya Das .num_parents = 6, 513*15d09e83STaniya Das .ops = &clk_rcg2_ops, 514*15d09e83STaniya Das }, 515*15d09e83STaniya Das }; 516*15d09e83STaniya Das 517*15d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_1_clk_src = { 518*15d09e83STaniya Das .cmd_rcgr = 0xa010, 519*15d09e83STaniya Das .mnd_width = 0, 520*15d09e83STaniya Das .hid_width = 5, 521*15d09e83STaniya Das .parent_map = cam_cc_parent_map_4, 522*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 523*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 524*15d09e83STaniya Das .name = "cam_cc_ife_1_clk_src", 525*15d09e83STaniya Das .parent_data = cam_cc_parent_data_4, 526*15d09e83STaniya Das .num_parents = 4, 527*15d09e83STaniya Das .ops = &clk_rcg2_ops, 528*15d09e83STaniya Das }, 529*15d09e83STaniya Das }; 530*15d09e83STaniya Das 531*15d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 532*15d09e83STaniya Das .cmd_rcgr = 0xa034, 533*15d09e83STaniya Das .mnd_width = 0, 534*15d09e83STaniya Das .hid_width = 5, 535*15d09e83STaniya Das .parent_map = cam_cc_parent_map_3, 536*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 537*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 538*15d09e83STaniya Das .name = "cam_cc_ife_1_csid_clk_src", 539*15d09e83STaniya Das .parent_data = cam_cc_parent_data_3, 540*15d09e83STaniya Das .num_parents = 6, 541*15d09e83STaniya Das .ops = &clk_rcg2_ops, 542*15d09e83STaniya Das }, 543*15d09e83STaniya Das }; 544*15d09e83STaniya Das 545*15d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 546*15d09e83STaniya Das .cmd_rcgr = 0xb004, 547*15d09e83STaniya Das .mnd_width = 0, 548*15d09e83STaniya Das .hid_width = 5, 549*15d09e83STaniya Das .parent_map = cam_cc_parent_map_4, 550*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 551*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 552*15d09e83STaniya Das .name = "cam_cc_ife_lite_clk_src", 553*15d09e83STaniya Das .parent_data = cam_cc_parent_data_4, 554*15d09e83STaniya Das .num_parents = 4, 555*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 556*15d09e83STaniya Das .ops = &clk_rcg2_ops, 557*15d09e83STaniya Das }, 558*15d09e83STaniya Das }; 559*15d09e83STaniya Das 560*15d09e83STaniya Das static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 561*15d09e83STaniya Das .cmd_rcgr = 0xb024, 562*15d09e83STaniya Das .mnd_width = 0, 563*15d09e83STaniya Das .hid_width = 5, 564*15d09e83STaniya Das .parent_map = cam_cc_parent_map_3, 565*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 566*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 567*15d09e83STaniya Das .name = "cam_cc_ife_lite_csid_clk_src", 568*15d09e83STaniya Das .parent_data = cam_cc_parent_data_3, 569*15d09e83STaniya Das .num_parents = 6, 570*15d09e83STaniya Das .ops = &clk_rcg2_ops, 571*15d09e83STaniya Das }, 572*15d09e83STaniya Das }; 573*15d09e83STaniya Das 574*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 575*15d09e83STaniya Das F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 576*15d09e83STaniya Das F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), 577*15d09e83STaniya Das F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), 578*15d09e83STaniya Das F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), 579*15d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 580*15d09e83STaniya Das { } 581*15d09e83STaniya Das }; 582*15d09e83STaniya Das 583*15d09e83STaniya Das static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 584*15d09e83STaniya Das .cmd_rcgr = 0x7010, 585*15d09e83STaniya Das .mnd_width = 0, 586*15d09e83STaniya Das .hid_width = 5, 587*15d09e83STaniya Das .parent_map = cam_cc_parent_map_2, 588*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 589*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 590*15d09e83STaniya Das .name = "cam_cc_ipe_0_clk_src", 591*15d09e83STaniya Das .parent_data = cam_cc_parent_data_2, 592*15d09e83STaniya Das .num_parents = 5, 593*15d09e83STaniya Das .ops = &clk_rcg2_ops, 594*15d09e83STaniya Das }, 595*15d09e83STaniya Das }; 596*15d09e83STaniya Das 597*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { 598*15d09e83STaniya Das F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0), 599*15d09e83STaniya Das F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0), 600*15d09e83STaniya Das F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 601*15d09e83STaniya Das F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), 602*15d09e83STaniya Das F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 603*15d09e83STaniya Das { } 604*15d09e83STaniya Das }; 605*15d09e83STaniya Das 606*15d09e83STaniya Das static struct clk_rcg2 cam_cc_jpeg_clk_src = { 607*15d09e83STaniya Das .cmd_rcgr = 0xb04c, 608*15d09e83STaniya Das .mnd_width = 0, 609*15d09e83STaniya Das .hid_width = 5, 610*15d09e83STaniya Das .parent_map = cam_cc_parent_map_2, 611*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_jpeg_clk_src, 612*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 613*15d09e83STaniya Das .name = "cam_cc_jpeg_clk_src", 614*15d09e83STaniya Das .parent_data = cam_cc_parent_data_2, 615*15d09e83STaniya Das .num_parents = 5, 616*15d09e83STaniya Das .ops = &clk_rcg2_ops, 617*15d09e83STaniya Das }, 618*15d09e83STaniya Das }; 619*15d09e83STaniya Das 620*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 621*15d09e83STaniya Das F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 622*15d09e83STaniya Das F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), 623*15d09e83STaniya Das F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 624*15d09e83STaniya Das F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 625*15d09e83STaniya Das { } 626*15d09e83STaniya Das }; 627*15d09e83STaniya Das 628*15d09e83STaniya Das static struct clk_rcg2 cam_cc_lrme_clk_src = { 629*15d09e83STaniya Das .cmd_rcgr = 0xb0f8, 630*15d09e83STaniya Das .mnd_width = 0, 631*15d09e83STaniya Das .hid_width = 5, 632*15d09e83STaniya Das .parent_map = cam_cc_parent_map_6, 633*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_lrme_clk_src, 634*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 635*15d09e83STaniya Das .name = "cam_cc_lrme_clk_src", 636*15d09e83STaniya Das .parent_data = cam_cc_parent_data_6, 637*15d09e83STaniya Das .num_parents = 5, 638*15d09e83STaniya Das .ops = &clk_rcg2_ops, 639*15d09e83STaniya Das }, 640*15d09e83STaniya Das }; 641*15d09e83STaniya Das 642*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 643*15d09e83STaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 644*15d09e83STaniya Das F(24000000, P_CAM_CC_PLL2_OUT_AUX, 10, 1, 2), 645*15d09e83STaniya Das F(64000000, P_CAM_CC_PLL2_OUT_AUX, 7.5, 0, 0), 646*15d09e83STaniya Das { } 647*15d09e83STaniya Das }; 648*15d09e83STaniya Das 649*15d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk0_clk_src = { 650*15d09e83STaniya Das .cmd_rcgr = 0x4004, 651*15d09e83STaniya Das .mnd_width = 8, 652*15d09e83STaniya Das .hid_width = 5, 653*15d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 654*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 655*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 656*15d09e83STaniya Das .name = "cam_cc_mclk0_clk_src", 657*15d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 658*15d09e83STaniya Das .num_parents = 3, 659*15d09e83STaniya Das .ops = &clk_rcg2_ops, 660*15d09e83STaniya Das }, 661*15d09e83STaniya Das }; 662*15d09e83STaniya Das 663*15d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk1_clk_src = { 664*15d09e83STaniya Das .cmd_rcgr = 0x4024, 665*15d09e83STaniya Das .mnd_width = 8, 666*15d09e83STaniya Das .hid_width = 5, 667*15d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 668*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 669*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 670*15d09e83STaniya Das .name = "cam_cc_mclk1_clk_src", 671*15d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 672*15d09e83STaniya Das .num_parents = 3, 673*15d09e83STaniya Das .ops = &clk_rcg2_ops, 674*15d09e83STaniya Das }, 675*15d09e83STaniya Das }; 676*15d09e83STaniya Das 677*15d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk2_clk_src = { 678*15d09e83STaniya Das .cmd_rcgr = 0x4044, 679*15d09e83STaniya Das .mnd_width = 8, 680*15d09e83STaniya Das .hid_width = 5, 681*15d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 682*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 683*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 684*15d09e83STaniya Das .name = "cam_cc_mclk2_clk_src", 685*15d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 686*15d09e83STaniya Das .num_parents = 3, 687*15d09e83STaniya Das .ops = &clk_rcg2_ops, 688*15d09e83STaniya Das }, 689*15d09e83STaniya Das }; 690*15d09e83STaniya Das 691*15d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk3_clk_src = { 692*15d09e83STaniya Das .cmd_rcgr = 0x4064, 693*15d09e83STaniya Das .mnd_width = 8, 694*15d09e83STaniya Das .hid_width = 5, 695*15d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 696*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 697*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 698*15d09e83STaniya Das .name = "cam_cc_mclk3_clk_src", 699*15d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 700*15d09e83STaniya Das .num_parents = 3, 701*15d09e83STaniya Das .ops = &clk_rcg2_ops, 702*15d09e83STaniya Das }, 703*15d09e83STaniya Das }; 704*15d09e83STaniya Das 705*15d09e83STaniya Das static struct clk_rcg2 cam_cc_mclk4_clk_src = { 706*15d09e83STaniya Das .cmd_rcgr = 0x4084, 707*15d09e83STaniya Das .mnd_width = 8, 708*15d09e83STaniya Das .hid_width = 5, 709*15d09e83STaniya Das .parent_map = cam_cc_parent_map_1, 710*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 711*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 712*15d09e83STaniya Das .name = "cam_cc_mclk4_clk_src", 713*15d09e83STaniya Das .parent_data = cam_cc_parent_data_1, 714*15d09e83STaniya Das .num_parents = 3, 715*15d09e83STaniya Das .ops = &clk_rcg2_ops, 716*15d09e83STaniya Das }, 717*15d09e83STaniya Das }; 718*15d09e83STaniya Das 719*15d09e83STaniya Das static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 720*15d09e83STaniya Das F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 721*15d09e83STaniya Das { } 722*15d09e83STaniya Das }; 723*15d09e83STaniya Das 724*15d09e83STaniya Das static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 725*15d09e83STaniya Das .cmd_rcgr = 0x6058, 726*15d09e83STaniya Das .mnd_width = 0, 727*15d09e83STaniya Das .hid_width = 5, 728*15d09e83STaniya Das .parent_map = cam_cc_parent_map_0, 729*15d09e83STaniya Das .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 730*15d09e83STaniya Das .clkr.hw.init = &(struct clk_init_data){ 731*15d09e83STaniya Das .name = "cam_cc_slow_ahb_clk_src", 732*15d09e83STaniya Das .parent_data = cam_cc_parent_data_0, 733*15d09e83STaniya Das .num_parents = 4, 734*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 735*15d09e83STaniya Das .ops = &clk_rcg2_ops, 736*15d09e83STaniya Das }, 737*15d09e83STaniya Das }; 738*15d09e83STaniya Das 739*15d09e83STaniya Das static struct clk_branch cam_cc_bps_ahb_clk = { 740*15d09e83STaniya Das .halt_reg = 0x6070, 741*15d09e83STaniya Das .halt_check = BRANCH_HALT, 742*15d09e83STaniya Das .clkr = { 743*15d09e83STaniya Das .enable_reg = 0x6070, 744*15d09e83STaniya Das .enable_mask = BIT(0), 745*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 746*15d09e83STaniya Das .name = "cam_cc_bps_ahb_clk", 747*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 748*15d09e83STaniya Das .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 749*15d09e83STaniya Das }, 750*15d09e83STaniya Das .num_parents = 1, 751*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 752*15d09e83STaniya Das .ops = &clk_branch2_ops, 753*15d09e83STaniya Das }, 754*15d09e83STaniya Das }, 755*15d09e83STaniya Das }; 756*15d09e83STaniya Das 757*15d09e83STaniya Das static struct clk_branch cam_cc_bps_areg_clk = { 758*15d09e83STaniya Das .halt_reg = 0x6054, 759*15d09e83STaniya Das .halt_check = BRANCH_HALT, 760*15d09e83STaniya Das .clkr = { 761*15d09e83STaniya Das .enable_reg = 0x6054, 762*15d09e83STaniya Das .enable_mask = BIT(0), 763*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 764*15d09e83STaniya Das .name = "cam_cc_bps_areg_clk", 765*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 766*15d09e83STaniya Das .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, 767*15d09e83STaniya Das }, 768*15d09e83STaniya Das .num_parents = 1, 769*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 770*15d09e83STaniya Das .ops = &clk_branch2_ops, 771*15d09e83STaniya Das }, 772*15d09e83STaniya Das }, 773*15d09e83STaniya Das }; 774*15d09e83STaniya Das 775*15d09e83STaniya Das static struct clk_branch cam_cc_bps_axi_clk = { 776*15d09e83STaniya Das .halt_reg = 0x6038, 777*15d09e83STaniya Das .halt_check = BRANCH_HALT, 778*15d09e83STaniya Das .clkr = { 779*15d09e83STaniya Das .enable_reg = 0x6038, 780*15d09e83STaniya Das .enable_mask = BIT(0), 781*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 782*15d09e83STaniya Das .name = "cam_cc_bps_axi_clk", 783*15d09e83STaniya Das .ops = &clk_branch2_ops, 784*15d09e83STaniya Das }, 785*15d09e83STaniya Das }, 786*15d09e83STaniya Das }; 787*15d09e83STaniya Das 788*15d09e83STaniya Das static struct clk_branch cam_cc_bps_clk = { 789*15d09e83STaniya Das .halt_reg = 0x6028, 790*15d09e83STaniya Das .halt_check = BRANCH_HALT, 791*15d09e83STaniya Das .clkr = { 792*15d09e83STaniya Das .enable_reg = 0x6028, 793*15d09e83STaniya Das .enable_mask = BIT(0), 794*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 795*15d09e83STaniya Das .name = "cam_cc_bps_clk", 796*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 797*15d09e83STaniya Das .hw = &cam_cc_bps_clk_src.clkr.hw, 798*15d09e83STaniya Das }, 799*15d09e83STaniya Das .num_parents = 1, 800*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 801*15d09e83STaniya Das .ops = &clk_branch2_ops, 802*15d09e83STaniya Das }, 803*15d09e83STaniya Das }, 804*15d09e83STaniya Das }; 805*15d09e83STaniya Das 806*15d09e83STaniya Das static struct clk_branch cam_cc_camnoc_axi_clk = { 807*15d09e83STaniya Das .halt_reg = 0xb124, 808*15d09e83STaniya Das .halt_check = BRANCH_HALT, 809*15d09e83STaniya Das .clkr = { 810*15d09e83STaniya Das .enable_reg = 0xb124, 811*15d09e83STaniya Das .enable_mask = BIT(0), 812*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 813*15d09e83STaniya Das .name = "cam_cc_camnoc_axi_clk", 814*15d09e83STaniya Das .ops = &clk_branch2_ops, 815*15d09e83STaniya Das }, 816*15d09e83STaniya Das }, 817*15d09e83STaniya Das }; 818*15d09e83STaniya Das 819*15d09e83STaniya Das static struct clk_branch cam_cc_cci_0_clk = { 820*15d09e83STaniya Das .halt_reg = 0xb0f0, 821*15d09e83STaniya Das .halt_check = BRANCH_HALT, 822*15d09e83STaniya Das .clkr = { 823*15d09e83STaniya Das .enable_reg = 0xb0f0, 824*15d09e83STaniya Das .enable_mask = BIT(0), 825*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 826*15d09e83STaniya Das .name = "cam_cc_cci_0_clk", 827*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 828*15d09e83STaniya Das .hw = &cam_cc_cci_0_clk_src.clkr.hw, 829*15d09e83STaniya Das }, 830*15d09e83STaniya Das .num_parents = 1, 831*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 832*15d09e83STaniya Das .ops = &clk_branch2_ops, 833*15d09e83STaniya Das }, 834*15d09e83STaniya Das }, 835*15d09e83STaniya Das }; 836*15d09e83STaniya Das 837*15d09e83STaniya Das static struct clk_branch cam_cc_cci_1_clk = { 838*15d09e83STaniya Das .halt_reg = 0xb164, 839*15d09e83STaniya Das .halt_check = BRANCH_HALT, 840*15d09e83STaniya Das .clkr = { 841*15d09e83STaniya Das .enable_reg = 0xb164, 842*15d09e83STaniya Das .enable_mask = BIT(0), 843*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 844*15d09e83STaniya Das .name = "cam_cc_cci_1_clk", 845*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 846*15d09e83STaniya Das .hw = &cam_cc_cci_1_clk_src.clkr.hw, 847*15d09e83STaniya Das }, 848*15d09e83STaniya Das .num_parents = 1, 849*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 850*15d09e83STaniya Das .ops = &clk_branch2_ops, 851*15d09e83STaniya Das }, 852*15d09e83STaniya Das }, 853*15d09e83STaniya Das }; 854*15d09e83STaniya Das 855*15d09e83STaniya Das static struct clk_branch cam_cc_core_ahb_clk = { 856*15d09e83STaniya Das .halt_reg = 0xb144, 857*15d09e83STaniya Das .halt_check = BRANCH_HALT_DELAY, 858*15d09e83STaniya Das .clkr = { 859*15d09e83STaniya Das .enable_reg = 0xb144, 860*15d09e83STaniya Das .enable_mask = BIT(0), 861*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 862*15d09e83STaniya Das .name = "cam_cc_core_ahb_clk", 863*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 864*15d09e83STaniya Das .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 865*15d09e83STaniya Das }, 866*15d09e83STaniya Das .num_parents = 1, 867*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 868*15d09e83STaniya Das .ops = &clk_branch2_ops, 869*15d09e83STaniya Das }, 870*15d09e83STaniya Das }, 871*15d09e83STaniya Das }; 872*15d09e83STaniya Das 873*15d09e83STaniya Das static struct clk_branch cam_cc_cpas_ahb_clk = { 874*15d09e83STaniya Das .halt_reg = 0xb11c, 875*15d09e83STaniya Das .halt_check = BRANCH_HALT, 876*15d09e83STaniya Das .clkr = { 877*15d09e83STaniya Das .enable_reg = 0xb11c, 878*15d09e83STaniya Das .enable_mask = BIT(0), 879*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 880*15d09e83STaniya Das .name = "cam_cc_cpas_ahb_clk", 881*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 882*15d09e83STaniya Das .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 883*15d09e83STaniya Das }, 884*15d09e83STaniya Das .num_parents = 1, 885*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 886*15d09e83STaniya Das .ops = &clk_branch2_ops, 887*15d09e83STaniya Das }, 888*15d09e83STaniya Das }, 889*15d09e83STaniya Das }; 890*15d09e83STaniya Das 891*15d09e83STaniya Das static struct clk_branch cam_cc_csi0phytimer_clk = { 892*15d09e83STaniya Das .halt_reg = 0x501c, 893*15d09e83STaniya Das .halt_check = BRANCH_HALT, 894*15d09e83STaniya Das .clkr = { 895*15d09e83STaniya Das .enable_reg = 0x501c, 896*15d09e83STaniya Das .enable_mask = BIT(0), 897*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 898*15d09e83STaniya Das .name = "cam_cc_csi0phytimer_clk", 899*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 900*15d09e83STaniya Das .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, 901*15d09e83STaniya Das }, 902*15d09e83STaniya Das .num_parents = 1, 903*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 904*15d09e83STaniya Das .ops = &clk_branch2_ops, 905*15d09e83STaniya Das }, 906*15d09e83STaniya Das }, 907*15d09e83STaniya Das }; 908*15d09e83STaniya Das 909*15d09e83STaniya Das static struct clk_branch cam_cc_csi1phytimer_clk = { 910*15d09e83STaniya Das .halt_reg = 0x5040, 911*15d09e83STaniya Das .halt_check = BRANCH_HALT, 912*15d09e83STaniya Das .clkr = { 913*15d09e83STaniya Das .enable_reg = 0x5040, 914*15d09e83STaniya Das .enable_mask = BIT(0), 915*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 916*15d09e83STaniya Das .name = "cam_cc_csi1phytimer_clk", 917*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 918*15d09e83STaniya Das .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, 919*15d09e83STaniya Das }, 920*15d09e83STaniya Das .num_parents = 1, 921*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 922*15d09e83STaniya Das .ops = &clk_branch2_ops, 923*15d09e83STaniya Das }, 924*15d09e83STaniya Das }, 925*15d09e83STaniya Das }; 926*15d09e83STaniya Das 927*15d09e83STaniya Das static struct clk_branch cam_cc_csi2phytimer_clk = { 928*15d09e83STaniya Das .halt_reg = 0x5064, 929*15d09e83STaniya Das .halt_check = BRANCH_HALT, 930*15d09e83STaniya Das .clkr = { 931*15d09e83STaniya Das .enable_reg = 0x5064, 932*15d09e83STaniya Das .enable_mask = BIT(0), 933*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 934*15d09e83STaniya Das .name = "cam_cc_csi2phytimer_clk", 935*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 936*15d09e83STaniya Das .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, 937*15d09e83STaniya Das }, 938*15d09e83STaniya Das .num_parents = 1, 939*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 940*15d09e83STaniya Das .ops = &clk_branch2_ops, 941*15d09e83STaniya Das }, 942*15d09e83STaniya Das }, 943*15d09e83STaniya Das }; 944*15d09e83STaniya Das 945*15d09e83STaniya Das static struct clk_branch cam_cc_csi3phytimer_clk = { 946*15d09e83STaniya Das .halt_reg = 0x5088, 947*15d09e83STaniya Das .halt_check = BRANCH_HALT, 948*15d09e83STaniya Das .clkr = { 949*15d09e83STaniya Das .enable_reg = 0x5088, 950*15d09e83STaniya Das .enable_mask = BIT(0), 951*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 952*15d09e83STaniya Das .name = "cam_cc_csi3phytimer_clk", 953*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 954*15d09e83STaniya Das .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, 955*15d09e83STaniya Das }, 956*15d09e83STaniya Das .num_parents = 1, 957*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 958*15d09e83STaniya Das .ops = &clk_branch2_ops, 959*15d09e83STaniya Das }, 960*15d09e83STaniya Das }, 961*15d09e83STaniya Das }; 962*15d09e83STaniya Das 963*15d09e83STaniya Das static struct clk_branch cam_cc_csiphy0_clk = { 964*15d09e83STaniya Das .halt_reg = 0x5020, 965*15d09e83STaniya Das .halt_check = BRANCH_HALT, 966*15d09e83STaniya Das .clkr = { 967*15d09e83STaniya Das .enable_reg = 0x5020, 968*15d09e83STaniya Das .enable_mask = BIT(0), 969*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 970*15d09e83STaniya Das .name = "cam_cc_csiphy0_clk", 971*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 972*15d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 973*15d09e83STaniya Das }, 974*15d09e83STaniya Das .num_parents = 1, 975*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 976*15d09e83STaniya Das .ops = &clk_branch2_ops, 977*15d09e83STaniya Das }, 978*15d09e83STaniya Das }, 979*15d09e83STaniya Das }; 980*15d09e83STaniya Das 981*15d09e83STaniya Das static struct clk_branch cam_cc_csiphy1_clk = { 982*15d09e83STaniya Das .halt_reg = 0x5044, 983*15d09e83STaniya Das .halt_check = BRANCH_HALT, 984*15d09e83STaniya Das .clkr = { 985*15d09e83STaniya Das .enable_reg = 0x5044, 986*15d09e83STaniya Das .enable_mask = BIT(0), 987*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 988*15d09e83STaniya Das .name = "cam_cc_csiphy1_clk", 989*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 990*15d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 991*15d09e83STaniya Das }, 992*15d09e83STaniya Das .num_parents = 1, 993*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 994*15d09e83STaniya Das .ops = &clk_branch2_ops, 995*15d09e83STaniya Das }, 996*15d09e83STaniya Das }, 997*15d09e83STaniya Das }; 998*15d09e83STaniya Das 999*15d09e83STaniya Das static struct clk_branch cam_cc_csiphy2_clk = { 1000*15d09e83STaniya Das .halt_reg = 0x5068, 1001*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1002*15d09e83STaniya Das .clkr = { 1003*15d09e83STaniya Das .enable_reg = 0x5068, 1004*15d09e83STaniya Das .enable_mask = BIT(0), 1005*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1006*15d09e83STaniya Das .name = "cam_cc_csiphy2_clk", 1007*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1008*15d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 1009*15d09e83STaniya Das }, 1010*15d09e83STaniya Das .num_parents = 1, 1011*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1012*15d09e83STaniya Das .ops = &clk_branch2_ops, 1013*15d09e83STaniya Das }, 1014*15d09e83STaniya Das }, 1015*15d09e83STaniya Das }; 1016*15d09e83STaniya Das 1017*15d09e83STaniya Das static struct clk_branch cam_cc_csiphy3_clk = { 1018*15d09e83STaniya Das .halt_reg = 0x508c, 1019*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1020*15d09e83STaniya Das .clkr = { 1021*15d09e83STaniya Das .enable_reg = 0x508c, 1022*15d09e83STaniya Das .enable_mask = BIT(0), 1023*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1024*15d09e83STaniya Das .name = "cam_cc_csiphy3_clk", 1025*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1026*15d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 1027*15d09e83STaniya Das }, 1028*15d09e83STaniya Das .num_parents = 1, 1029*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1030*15d09e83STaniya Das .ops = &clk_branch2_ops, 1031*15d09e83STaniya Das }, 1032*15d09e83STaniya Das }, 1033*15d09e83STaniya Das }; 1034*15d09e83STaniya Das 1035*15d09e83STaniya Das static struct clk_branch cam_cc_icp_clk = { 1036*15d09e83STaniya Das .halt_reg = 0xb0a0, 1037*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1038*15d09e83STaniya Das .clkr = { 1039*15d09e83STaniya Das .enable_reg = 0xb0a0, 1040*15d09e83STaniya Das .enable_mask = BIT(0), 1041*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1042*15d09e83STaniya Das .name = "cam_cc_icp_clk", 1043*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1044*15d09e83STaniya Das .hw = &cam_cc_icp_clk_src.clkr.hw, 1045*15d09e83STaniya Das }, 1046*15d09e83STaniya Das .num_parents = 1, 1047*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1048*15d09e83STaniya Das .ops = &clk_branch2_ops, 1049*15d09e83STaniya Das }, 1050*15d09e83STaniya Das }, 1051*15d09e83STaniya Das }; 1052*15d09e83STaniya Das 1053*15d09e83STaniya Das static struct clk_branch cam_cc_ife_0_axi_clk = { 1054*15d09e83STaniya Das .halt_reg = 0x9080, 1055*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1056*15d09e83STaniya Das .clkr = { 1057*15d09e83STaniya Das .enable_reg = 0x9080, 1058*15d09e83STaniya Das .enable_mask = BIT(0), 1059*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1060*15d09e83STaniya Das .name = "cam_cc_ife_0_axi_clk", 1061*15d09e83STaniya Das .ops = &clk_branch2_ops, 1062*15d09e83STaniya Das }, 1063*15d09e83STaniya Das }, 1064*15d09e83STaniya Das }; 1065*15d09e83STaniya Das 1066*15d09e83STaniya Das static struct clk_branch cam_cc_ife_0_clk = { 1067*15d09e83STaniya Das .halt_reg = 0x9028, 1068*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1069*15d09e83STaniya Das .clkr = { 1070*15d09e83STaniya Das .enable_reg = 0x9028, 1071*15d09e83STaniya Das .enable_mask = BIT(0), 1072*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1073*15d09e83STaniya Das .name = "cam_cc_ife_0_clk", 1074*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1075*15d09e83STaniya Das .hw = &cam_cc_ife_0_clk_src.clkr.hw, 1076*15d09e83STaniya Das }, 1077*15d09e83STaniya Das .num_parents = 1, 1078*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1079*15d09e83STaniya Das .ops = &clk_branch2_ops, 1080*15d09e83STaniya Das }, 1081*15d09e83STaniya Das }, 1082*15d09e83STaniya Das }; 1083*15d09e83STaniya Das 1084*15d09e83STaniya Das static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1085*15d09e83STaniya Das .halt_reg = 0x907c, 1086*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1087*15d09e83STaniya Das .clkr = { 1088*15d09e83STaniya Das .enable_reg = 0x907c, 1089*15d09e83STaniya Das .enable_mask = BIT(0), 1090*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1091*15d09e83STaniya Das .name = "cam_cc_ife_0_cphy_rx_clk", 1092*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1093*15d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 1094*15d09e83STaniya Das }, 1095*15d09e83STaniya Das .num_parents = 1, 1096*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1097*15d09e83STaniya Das .ops = &clk_branch2_ops, 1098*15d09e83STaniya Das }, 1099*15d09e83STaniya Das }, 1100*15d09e83STaniya Das }; 1101*15d09e83STaniya Das 1102*15d09e83STaniya Das static struct clk_branch cam_cc_ife_0_csid_clk = { 1103*15d09e83STaniya Das .halt_reg = 0x9054, 1104*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1105*15d09e83STaniya Das .clkr = { 1106*15d09e83STaniya Das .enable_reg = 0x9054, 1107*15d09e83STaniya Das .enable_mask = BIT(0), 1108*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1109*15d09e83STaniya Das .name = "cam_cc_ife_0_csid_clk", 1110*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1111*15d09e83STaniya Das .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw, 1112*15d09e83STaniya Das }, 1113*15d09e83STaniya Das .num_parents = 1, 1114*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1115*15d09e83STaniya Das .ops = &clk_branch2_ops, 1116*15d09e83STaniya Das }, 1117*15d09e83STaniya Das }, 1118*15d09e83STaniya Das }; 1119*15d09e83STaniya Das 1120*15d09e83STaniya Das static struct clk_branch cam_cc_ife_0_dsp_clk = { 1121*15d09e83STaniya Das .halt_reg = 0x9038, 1122*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1123*15d09e83STaniya Das .clkr = { 1124*15d09e83STaniya Das .enable_reg = 0x9038, 1125*15d09e83STaniya Das .enable_mask = BIT(0), 1126*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1127*15d09e83STaniya Das .name = "cam_cc_ife_0_dsp_clk", 1128*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1129*15d09e83STaniya Das .hw = &cam_cc_ife_0_clk_src.clkr.hw, 1130*15d09e83STaniya Das }, 1131*15d09e83STaniya Das .num_parents = 1, 1132*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1133*15d09e83STaniya Das .ops = &clk_branch2_ops, 1134*15d09e83STaniya Das }, 1135*15d09e83STaniya Das }, 1136*15d09e83STaniya Das }; 1137*15d09e83STaniya Das 1138*15d09e83STaniya Das static struct clk_branch cam_cc_ife_1_axi_clk = { 1139*15d09e83STaniya Das .halt_reg = 0xa058, 1140*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1141*15d09e83STaniya Das .clkr = { 1142*15d09e83STaniya Das .enable_reg = 0xa058, 1143*15d09e83STaniya Das .enable_mask = BIT(0), 1144*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1145*15d09e83STaniya Das .name = "cam_cc_ife_1_axi_clk", 1146*15d09e83STaniya Das .ops = &clk_branch2_ops, 1147*15d09e83STaniya Das }, 1148*15d09e83STaniya Das }, 1149*15d09e83STaniya Das }; 1150*15d09e83STaniya Das 1151*15d09e83STaniya Das static struct clk_branch cam_cc_ife_1_clk = { 1152*15d09e83STaniya Das .halt_reg = 0xa028, 1153*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1154*15d09e83STaniya Das .clkr = { 1155*15d09e83STaniya Das .enable_reg = 0xa028, 1156*15d09e83STaniya Das .enable_mask = BIT(0), 1157*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1158*15d09e83STaniya Das .name = "cam_cc_ife_1_clk", 1159*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1160*15d09e83STaniya Das .hw = &cam_cc_ife_1_clk_src.clkr.hw, 1161*15d09e83STaniya Das }, 1162*15d09e83STaniya Das .num_parents = 1, 1163*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1164*15d09e83STaniya Das .ops = &clk_branch2_ops, 1165*15d09e83STaniya Das }, 1166*15d09e83STaniya Das }, 1167*15d09e83STaniya Das }; 1168*15d09e83STaniya Das 1169*15d09e83STaniya Das static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1170*15d09e83STaniya Das .halt_reg = 0xa054, 1171*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1172*15d09e83STaniya Das .clkr = { 1173*15d09e83STaniya Das .enable_reg = 0xa054, 1174*15d09e83STaniya Das .enable_mask = BIT(0), 1175*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1176*15d09e83STaniya Das .name = "cam_cc_ife_1_cphy_rx_clk", 1177*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1178*15d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 1179*15d09e83STaniya Das }, 1180*15d09e83STaniya Das .num_parents = 1, 1181*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1182*15d09e83STaniya Das .ops = &clk_branch2_ops, 1183*15d09e83STaniya Das }, 1184*15d09e83STaniya Das }, 1185*15d09e83STaniya Das }; 1186*15d09e83STaniya Das 1187*15d09e83STaniya Das static struct clk_branch cam_cc_ife_1_csid_clk = { 1188*15d09e83STaniya Das .halt_reg = 0xa04c, 1189*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1190*15d09e83STaniya Das .clkr = { 1191*15d09e83STaniya Das .enable_reg = 0xa04c, 1192*15d09e83STaniya Das .enable_mask = BIT(0), 1193*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1194*15d09e83STaniya Das .name = "cam_cc_ife_1_csid_clk", 1195*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1196*15d09e83STaniya Das .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw, 1197*15d09e83STaniya Das }, 1198*15d09e83STaniya Das .num_parents = 1, 1199*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1200*15d09e83STaniya Das .ops = &clk_branch2_ops, 1201*15d09e83STaniya Das }, 1202*15d09e83STaniya Das }, 1203*15d09e83STaniya Das }; 1204*15d09e83STaniya Das 1205*15d09e83STaniya Das static struct clk_branch cam_cc_ife_1_dsp_clk = { 1206*15d09e83STaniya Das .halt_reg = 0xa030, 1207*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1208*15d09e83STaniya Das .clkr = { 1209*15d09e83STaniya Das .enable_reg = 0xa030, 1210*15d09e83STaniya Das .enable_mask = BIT(0), 1211*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1212*15d09e83STaniya Das .name = "cam_cc_ife_1_dsp_clk", 1213*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1214*15d09e83STaniya Das .hw = &cam_cc_ife_1_clk_src.clkr.hw, 1215*15d09e83STaniya Das }, 1216*15d09e83STaniya Das .num_parents = 1, 1217*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1218*15d09e83STaniya Das .ops = &clk_branch2_ops, 1219*15d09e83STaniya Das }, 1220*15d09e83STaniya Das }, 1221*15d09e83STaniya Das }; 1222*15d09e83STaniya Das 1223*15d09e83STaniya Das static struct clk_branch cam_cc_ife_lite_clk = { 1224*15d09e83STaniya Das .halt_reg = 0xb01c, 1225*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1226*15d09e83STaniya Das .clkr = { 1227*15d09e83STaniya Das .enable_reg = 0xb01c, 1228*15d09e83STaniya Das .enable_mask = BIT(0), 1229*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1230*15d09e83STaniya Das .name = "cam_cc_ife_lite_clk", 1231*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1232*15d09e83STaniya Das .hw = &cam_cc_ife_lite_clk_src.clkr.hw, 1233*15d09e83STaniya Das }, 1234*15d09e83STaniya Das .num_parents = 1, 1235*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1236*15d09e83STaniya Das .ops = &clk_branch2_ops, 1237*15d09e83STaniya Das }, 1238*15d09e83STaniya Das }, 1239*15d09e83STaniya Das }; 1240*15d09e83STaniya Das 1241*15d09e83STaniya Das static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1242*15d09e83STaniya Das .halt_reg = 0xb044, 1243*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1244*15d09e83STaniya Das .clkr = { 1245*15d09e83STaniya Das .enable_reg = 0xb044, 1246*15d09e83STaniya Das .enable_mask = BIT(0), 1247*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1248*15d09e83STaniya Das .name = "cam_cc_ife_lite_cphy_rx_clk", 1249*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1250*15d09e83STaniya Das .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, 1251*15d09e83STaniya Das }, 1252*15d09e83STaniya Das .num_parents = 1, 1253*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1254*15d09e83STaniya Das .ops = &clk_branch2_ops, 1255*15d09e83STaniya Das }, 1256*15d09e83STaniya Das }, 1257*15d09e83STaniya Das }; 1258*15d09e83STaniya Das 1259*15d09e83STaniya Das static struct clk_branch cam_cc_ife_lite_csid_clk = { 1260*15d09e83STaniya Das .halt_reg = 0xb03c, 1261*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1262*15d09e83STaniya Das .clkr = { 1263*15d09e83STaniya Das .enable_reg = 0xb03c, 1264*15d09e83STaniya Das .enable_mask = BIT(0), 1265*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1266*15d09e83STaniya Das .name = "cam_cc_ife_lite_csid_clk", 1267*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1268*15d09e83STaniya Das .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1269*15d09e83STaniya Das }, 1270*15d09e83STaniya Das .num_parents = 1, 1271*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1272*15d09e83STaniya Das .ops = &clk_branch2_ops, 1273*15d09e83STaniya Das }, 1274*15d09e83STaniya Das }, 1275*15d09e83STaniya Das }; 1276*15d09e83STaniya Das 1277*15d09e83STaniya Das static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1278*15d09e83STaniya Das .halt_reg = 0x7040, 1279*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1280*15d09e83STaniya Das .clkr = { 1281*15d09e83STaniya Das .enable_reg = 0x7040, 1282*15d09e83STaniya Das .enable_mask = BIT(0), 1283*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1284*15d09e83STaniya Das .name = "cam_cc_ipe_0_ahb_clk", 1285*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1286*15d09e83STaniya Das .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, 1287*15d09e83STaniya Das }, 1288*15d09e83STaniya Das .num_parents = 1, 1289*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1290*15d09e83STaniya Das .ops = &clk_branch2_ops, 1291*15d09e83STaniya Das }, 1292*15d09e83STaniya Das }, 1293*15d09e83STaniya Das }; 1294*15d09e83STaniya Das 1295*15d09e83STaniya Das static struct clk_branch cam_cc_ipe_0_areg_clk = { 1296*15d09e83STaniya Das .halt_reg = 0x703c, 1297*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1298*15d09e83STaniya Das .clkr = { 1299*15d09e83STaniya Das .enable_reg = 0x703c, 1300*15d09e83STaniya Das .enable_mask = BIT(0), 1301*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1302*15d09e83STaniya Das .name = "cam_cc_ipe_0_areg_clk", 1303*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1304*15d09e83STaniya Das .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, 1305*15d09e83STaniya Das }, 1306*15d09e83STaniya Das .num_parents = 1, 1307*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1308*15d09e83STaniya Das .ops = &clk_branch2_ops, 1309*15d09e83STaniya Das }, 1310*15d09e83STaniya Das }, 1311*15d09e83STaniya Das }; 1312*15d09e83STaniya Das 1313*15d09e83STaniya Das static struct clk_branch cam_cc_ipe_0_axi_clk = { 1314*15d09e83STaniya Das .halt_reg = 0x7038, 1315*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1316*15d09e83STaniya Das .clkr = { 1317*15d09e83STaniya Das .enable_reg = 0x7038, 1318*15d09e83STaniya Das .enable_mask = BIT(0), 1319*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1320*15d09e83STaniya Das .name = "cam_cc_ipe_0_axi_clk", 1321*15d09e83STaniya Das .ops = &clk_branch2_ops, 1322*15d09e83STaniya Das }, 1323*15d09e83STaniya Das }, 1324*15d09e83STaniya Das }; 1325*15d09e83STaniya Das 1326*15d09e83STaniya Das static struct clk_branch cam_cc_ipe_0_clk = { 1327*15d09e83STaniya Das .halt_reg = 0x7028, 1328*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1329*15d09e83STaniya Das .clkr = { 1330*15d09e83STaniya Das .enable_reg = 0x7028, 1331*15d09e83STaniya Das .enable_mask = BIT(0), 1332*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1333*15d09e83STaniya Das .name = "cam_cc_ipe_0_clk", 1334*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1335*15d09e83STaniya Das .hw = &cam_cc_ipe_0_clk_src.clkr.hw, 1336*15d09e83STaniya Das }, 1337*15d09e83STaniya Das .num_parents = 1, 1338*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1339*15d09e83STaniya Das .ops = &clk_branch2_ops, 1340*15d09e83STaniya Das }, 1341*15d09e83STaniya Das }, 1342*15d09e83STaniya Das }; 1343*15d09e83STaniya Das 1344*15d09e83STaniya Das static struct clk_branch cam_cc_jpeg_clk = { 1345*15d09e83STaniya Das .halt_reg = 0xb064, 1346*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1347*15d09e83STaniya Das .clkr = { 1348*15d09e83STaniya Das .enable_reg = 0xb064, 1349*15d09e83STaniya Das .enable_mask = BIT(0), 1350*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1351*15d09e83STaniya Das .name = "cam_cc_jpeg_clk", 1352*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1353*15d09e83STaniya Das .hw = &cam_cc_jpeg_clk_src.clkr.hw, 1354*15d09e83STaniya Das }, 1355*15d09e83STaniya Das .num_parents = 1, 1356*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1357*15d09e83STaniya Das .ops = &clk_branch2_ops, 1358*15d09e83STaniya Das }, 1359*15d09e83STaniya Das }, 1360*15d09e83STaniya Das }; 1361*15d09e83STaniya Das 1362*15d09e83STaniya Das static struct clk_branch cam_cc_lrme_clk = { 1363*15d09e83STaniya Das .halt_reg = 0xb110, 1364*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1365*15d09e83STaniya Das .clkr = { 1366*15d09e83STaniya Das .enable_reg = 0xb110, 1367*15d09e83STaniya Das .enable_mask = BIT(0), 1368*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1369*15d09e83STaniya Das .name = "cam_cc_lrme_clk", 1370*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1371*15d09e83STaniya Das .hw = &cam_cc_lrme_clk_src.clkr.hw, 1372*15d09e83STaniya Das }, 1373*15d09e83STaniya Das .num_parents = 1, 1374*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1375*15d09e83STaniya Das .ops = &clk_branch2_ops, 1376*15d09e83STaniya Das }, 1377*15d09e83STaniya Das }, 1378*15d09e83STaniya Das }; 1379*15d09e83STaniya Das 1380*15d09e83STaniya Das static struct clk_branch cam_cc_mclk0_clk = { 1381*15d09e83STaniya Das .halt_reg = 0x401c, 1382*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1383*15d09e83STaniya Das .clkr = { 1384*15d09e83STaniya Das .enable_reg = 0x401c, 1385*15d09e83STaniya Das .enable_mask = BIT(0), 1386*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1387*15d09e83STaniya Das .name = "cam_cc_mclk0_clk", 1388*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1389*15d09e83STaniya Das .hw = &cam_cc_mclk0_clk_src.clkr.hw, 1390*15d09e83STaniya Das }, 1391*15d09e83STaniya Das .num_parents = 1, 1392*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1393*15d09e83STaniya Das .ops = &clk_branch2_ops, 1394*15d09e83STaniya Das }, 1395*15d09e83STaniya Das }, 1396*15d09e83STaniya Das }; 1397*15d09e83STaniya Das 1398*15d09e83STaniya Das static struct clk_branch cam_cc_mclk1_clk = { 1399*15d09e83STaniya Das .halt_reg = 0x403c, 1400*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1401*15d09e83STaniya Das .clkr = { 1402*15d09e83STaniya Das .enable_reg = 0x403c, 1403*15d09e83STaniya Das .enable_mask = BIT(0), 1404*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1405*15d09e83STaniya Das .name = "cam_cc_mclk1_clk", 1406*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1407*15d09e83STaniya Das .hw = &cam_cc_mclk1_clk_src.clkr.hw, 1408*15d09e83STaniya Das }, 1409*15d09e83STaniya Das .num_parents = 1, 1410*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1411*15d09e83STaniya Das .ops = &clk_branch2_ops, 1412*15d09e83STaniya Das }, 1413*15d09e83STaniya Das }, 1414*15d09e83STaniya Das }; 1415*15d09e83STaniya Das 1416*15d09e83STaniya Das static struct clk_branch cam_cc_mclk2_clk = { 1417*15d09e83STaniya Das .halt_reg = 0x405c, 1418*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1419*15d09e83STaniya Das .clkr = { 1420*15d09e83STaniya Das .enable_reg = 0x405c, 1421*15d09e83STaniya Das .enable_mask = BIT(0), 1422*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1423*15d09e83STaniya Das .name = "cam_cc_mclk2_clk", 1424*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1425*15d09e83STaniya Das .hw = &cam_cc_mclk2_clk_src.clkr.hw, 1426*15d09e83STaniya Das }, 1427*15d09e83STaniya Das .num_parents = 1, 1428*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1429*15d09e83STaniya Das .ops = &clk_branch2_ops, 1430*15d09e83STaniya Das }, 1431*15d09e83STaniya Das }, 1432*15d09e83STaniya Das }; 1433*15d09e83STaniya Das 1434*15d09e83STaniya Das static struct clk_branch cam_cc_mclk3_clk = { 1435*15d09e83STaniya Das .halt_reg = 0x407c, 1436*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1437*15d09e83STaniya Das .clkr = { 1438*15d09e83STaniya Das .enable_reg = 0x407c, 1439*15d09e83STaniya Das .enable_mask = BIT(0), 1440*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1441*15d09e83STaniya Das .name = "cam_cc_mclk3_clk", 1442*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1443*15d09e83STaniya Das .hw = &cam_cc_mclk3_clk_src.clkr.hw, 1444*15d09e83STaniya Das }, 1445*15d09e83STaniya Das .num_parents = 1, 1446*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1447*15d09e83STaniya Das .ops = &clk_branch2_ops, 1448*15d09e83STaniya Das }, 1449*15d09e83STaniya Das }, 1450*15d09e83STaniya Das }; 1451*15d09e83STaniya Das 1452*15d09e83STaniya Das static struct clk_branch cam_cc_mclk4_clk = { 1453*15d09e83STaniya Das .halt_reg = 0x409c, 1454*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1455*15d09e83STaniya Das .clkr = { 1456*15d09e83STaniya Das .enable_reg = 0x409c, 1457*15d09e83STaniya Das .enable_mask = BIT(0), 1458*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1459*15d09e83STaniya Das .name = "cam_cc_mclk4_clk", 1460*15d09e83STaniya Das .parent_data = &(const struct clk_parent_data){ 1461*15d09e83STaniya Das .hw = &cam_cc_mclk4_clk_src.clkr.hw, 1462*15d09e83STaniya Das }, 1463*15d09e83STaniya Das .num_parents = 1, 1464*15d09e83STaniya Das .flags = CLK_SET_RATE_PARENT, 1465*15d09e83STaniya Das .ops = &clk_branch2_ops, 1466*15d09e83STaniya Das }, 1467*15d09e83STaniya Das }, 1468*15d09e83STaniya Das }; 1469*15d09e83STaniya Das 1470*15d09e83STaniya Das static struct clk_branch cam_cc_soc_ahb_clk = { 1471*15d09e83STaniya Das .halt_reg = 0xb140, 1472*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1473*15d09e83STaniya Das .clkr = { 1474*15d09e83STaniya Das .enable_reg = 0xb140, 1475*15d09e83STaniya Das .enable_mask = BIT(0), 1476*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1477*15d09e83STaniya Das .name = "cam_cc_soc_ahb_clk", 1478*15d09e83STaniya Das .ops = &clk_branch2_ops, 1479*15d09e83STaniya Das }, 1480*15d09e83STaniya Das }, 1481*15d09e83STaniya Das }; 1482*15d09e83STaniya Das 1483*15d09e83STaniya Das static struct clk_branch cam_cc_sys_tmr_clk = { 1484*15d09e83STaniya Das .halt_reg = 0xb0a8, 1485*15d09e83STaniya Das .halt_check = BRANCH_HALT, 1486*15d09e83STaniya Das .clkr = { 1487*15d09e83STaniya Das .enable_reg = 0xb0a8, 1488*15d09e83STaniya Das .enable_mask = BIT(0), 1489*15d09e83STaniya Das .hw.init = &(struct clk_init_data){ 1490*15d09e83STaniya Das .name = "cam_cc_sys_tmr_clk", 1491*15d09e83STaniya Das .ops = &clk_branch2_ops, 1492*15d09e83STaniya Das }, 1493*15d09e83STaniya Das }, 1494*15d09e83STaniya Das }; 1495*15d09e83STaniya Das 1496*15d09e83STaniya Das static struct gdsc bps_gdsc = { 1497*15d09e83STaniya Das .gdscr = 0x6004, 1498*15d09e83STaniya Das .pd = { 1499*15d09e83STaniya Das .name = "bps_gdsc", 1500*15d09e83STaniya Das }, 1501*15d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 1502*15d09e83STaniya Das .flags = HW_CTRL, 1503*15d09e83STaniya Das }; 1504*15d09e83STaniya Das 1505*15d09e83STaniya Das static struct gdsc ife_0_gdsc = { 1506*15d09e83STaniya Das .gdscr = 0x9004, 1507*15d09e83STaniya Das .pd = { 1508*15d09e83STaniya Das .name = "ife_0_gdsc", 1509*15d09e83STaniya Das }, 1510*15d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 1511*15d09e83STaniya Das }; 1512*15d09e83STaniya Das 1513*15d09e83STaniya Das static struct gdsc ife_1_gdsc = { 1514*15d09e83STaniya Das .gdscr = 0xa004, 1515*15d09e83STaniya Das .pd = { 1516*15d09e83STaniya Das .name = "ife_1_gdsc", 1517*15d09e83STaniya Das }, 1518*15d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 1519*15d09e83STaniya Das }; 1520*15d09e83STaniya Das 1521*15d09e83STaniya Das static struct gdsc ipe_0_gdsc = { 1522*15d09e83STaniya Das .gdscr = 0x7004, 1523*15d09e83STaniya Das .pd = { 1524*15d09e83STaniya Das .name = "ipe_0_gdsc", 1525*15d09e83STaniya Das }, 1526*15d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 1527*15d09e83STaniya Das .flags = HW_CTRL, 1528*15d09e83STaniya Das }; 1529*15d09e83STaniya Das 1530*15d09e83STaniya Das static struct gdsc titan_top_gdsc = { 1531*15d09e83STaniya Das .gdscr = 0xb134, 1532*15d09e83STaniya Das .pd = { 1533*15d09e83STaniya Das .name = "titan_top_gdsc", 1534*15d09e83STaniya Das }, 1535*15d09e83STaniya Das .pwrsts = PWRSTS_OFF_ON, 1536*15d09e83STaniya Das }; 1537*15d09e83STaniya Das 1538*15d09e83STaniya Das static struct clk_hw *cam_cc_sc7180_hws[] = { 1539*15d09e83STaniya Das [CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw, 1540*15d09e83STaniya Das }; 1541*15d09e83STaniya Das 1542*15d09e83STaniya Das static struct clk_regmap *cam_cc_sc7180_clocks[] = { 1543*15d09e83STaniya Das [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1544*15d09e83STaniya Das [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1545*15d09e83STaniya Das [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 1546*15d09e83STaniya Das [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1547*15d09e83STaniya Das [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1548*15d09e83STaniya Das [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1549*15d09e83STaniya Das [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1550*15d09e83STaniya Das [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1551*15d09e83STaniya Das [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1552*15d09e83STaniya Das [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1553*15d09e83STaniya Das [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1554*15d09e83STaniya Das [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1555*15d09e83STaniya Das [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1556*15d09e83STaniya Das [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1557*15d09e83STaniya Das [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1558*15d09e83STaniya Das [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1559*15d09e83STaniya Das [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1560*15d09e83STaniya Das [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1561*15d09e83STaniya Das [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1562*15d09e83STaniya Das [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 1563*15d09e83STaniya Das [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 1564*15d09e83STaniya Das [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1565*15d09e83STaniya Das [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1566*15d09e83STaniya Das [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1567*15d09e83STaniya Das [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 1568*15d09e83STaniya Das [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1569*15d09e83STaniya Das [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1570*15d09e83STaniya Das [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1571*15d09e83STaniya Das [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 1572*15d09e83STaniya Das [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1573*15d09e83STaniya Das [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1574*15d09e83STaniya Das [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 1575*15d09e83STaniya Das [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 1576*15d09e83STaniya Das [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 1577*15d09e83STaniya Das [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 1578*15d09e83STaniya Das [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 1579*15d09e83STaniya Das [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1580*15d09e83STaniya Das [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1581*15d09e83STaniya Das [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 1582*15d09e83STaniya Das [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 1583*15d09e83STaniya Das [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 1584*15d09e83STaniya Das [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 1585*15d09e83STaniya Das [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1586*15d09e83STaniya Das [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1587*15d09e83STaniya Das [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1588*15d09e83STaniya Das [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1589*15d09e83STaniya Das [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1590*15d09e83STaniya Das [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 1591*15d09e83STaniya Das [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 1592*15d09e83STaniya Das [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 1593*15d09e83STaniya Das [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 1594*15d09e83STaniya Das [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 1595*15d09e83STaniya Das [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 1596*15d09e83STaniya Das [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 1597*15d09e83STaniya Das [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 1598*15d09e83STaniya Das [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 1599*15d09e83STaniya Das [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1600*15d09e83STaniya Das [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1601*15d09e83STaniya Das [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1602*15d09e83STaniya Das [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1603*15d09e83STaniya Das [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1604*15d09e83STaniya Das [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1605*15d09e83STaniya Das [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1606*15d09e83STaniya Das [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1607*15d09e83STaniya Das [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 1608*15d09e83STaniya Das [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 1609*15d09e83STaniya Das [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1610*15d09e83STaniya Das [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1611*15d09e83STaniya Das [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1612*15d09e83STaniya Das [CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr, 1613*15d09e83STaniya Das [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1614*15d09e83STaniya Das [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1615*15d09e83STaniya Das [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 1616*15d09e83STaniya Das [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 1617*15d09e83STaniya Das }; 1618*15d09e83STaniya Das static struct gdsc *cam_cc_sc7180_gdscs[] = { 1619*15d09e83STaniya Das [BPS_GDSC] = &bps_gdsc, 1620*15d09e83STaniya Das [IFE_0_GDSC] = &ife_0_gdsc, 1621*15d09e83STaniya Das [IFE_1_GDSC] = &ife_1_gdsc, 1622*15d09e83STaniya Das [IPE_0_GDSC] = &ipe_0_gdsc, 1623*15d09e83STaniya Das [TITAN_TOP_GDSC] = &titan_top_gdsc, 1624*15d09e83STaniya Das }; 1625*15d09e83STaniya Das 1626*15d09e83STaniya Das static const struct regmap_config cam_cc_sc7180_regmap_config = { 1627*15d09e83STaniya Das .reg_bits = 32, 1628*15d09e83STaniya Das .reg_stride = 4, 1629*15d09e83STaniya Das .val_bits = 32, 1630*15d09e83STaniya Das .max_register = 0xd028, 1631*15d09e83STaniya Das .fast_io = true, 1632*15d09e83STaniya Das }; 1633*15d09e83STaniya Das 1634*15d09e83STaniya Das static const struct qcom_cc_desc cam_cc_sc7180_desc = { 1635*15d09e83STaniya Das .config = &cam_cc_sc7180_regmap_config, 1636*15d09e83STaniya Das .clk_hws = cam_cc_sc7180_hws, 1637*15d09e83STaniya Das .num_clk_hws = ARRAY_SIZE(cam_cc_sc7180_hws), 1638*15d09e83STaniya Das .clks = cam_cc_sc7180_clocks, 1639*15d09e83STaniya Das .num_clks = ARRAY_SIZE(cam_cc_sc7180_clocks), 1640*15d09e83STaniya Das .gdscs = cam_cc_sc7180_gdscs, 1641*15d09e83STaniya Das .num_gdscs = ARRAY_SIZE(cam_cc_sc7180_gdscs), 1642*15d09e83STaniya Das }; 1643*15d09e83STaniya Das 1644*15d09e83STaniya Das static const struct of_device_id cam_cc_sc7180_match_table[] = { 1645*15d09e83STaniya Das { .compatible = "qcom,sc7180-camcc" }, 1646*15d09e83STaniya Das { } 1647*15d09e83STaniya Das }; 1648*15d09e83STaniya Das MODULE_DEVICE_TABLE(of, cam_cc_sc7180_match_table); 1649*15d09e83STaniya Das 1650*15d09e83STaniya Das static int cam_cc_sc7180_probe(struct platform_device *pdev) 1651*15d09e83STaniya Das { 1652*15d09e83STaniya Das struct regmap *regmap; 1653*15d09e83STaniya Das int ret; 1654*15d09e83STaniya Das 1655*15d09e83STaniya Das pm_runtime_enable(&pdev->dev); 1656*15d09e83STaniya Das ret = pm_clk_create(&pdev->dev); 1657*15d09e83STaniya Das if (ret < 0) 1658*15d09e83STaniya Das return ret; 1659*15d09e83STaniya Das 1660*15d09e83STaniya Das ret = pm_clk_add(&pdev->dev, "xo"); 1661*15d09e83STaniya Das if (ret < 0) { 1662*15d09e83STaniya Das dev_err(&pdev->dev, "Failed to acquire XO clock\n"); 1663*15d09e83STaniya Das goto disable_pm_runtime; 1664*15d09e83STaniya Das } 1665*15d09e83STaniya Das 1666*15d09e83STaniya Das ret = pm_clk_add(&pdev->dev, "iface"); 1667*15d09e83STaniya Das if (ret < 0) { 1668*15d09e83STaniya Das dev_err(&pdev->dev, "Failed to acquire iface clock\n"); 1669*15d09e83STaniya Das goto disable_pm_runtime; 1670*15d09e83STaniya Das } 1671*15d09e83STaniya Das 1672*15d09e83STaniya Das ret = pm_clk_runtime_resume(&pdev->dev); 1673*15d09e83STaniya Das if (ret < 0) { 1674*15d09e83STaniya Das dev_err(&pdev->dev, "pm runtime resume failed\n"); 1675*15d09e83STaniya Das goto destroy_pm_clk; 1676*15d09e83STaniya Das } 1677*15d09e83STaniya Das 1678*15d09e83STaniya Das regmap = qcom_cc_map(pdev, &cam_cc_sc7180_desc); 1679*15d09e83STaniya Das if (IS_ERR(regmap)) { 1680*15d09e83STaniya Das ret = PTR_ERR(regmap); 1681*15d09e83STaniya Das pm_clk_runtime_suspend(&pdev->dev); 1682*15d09e83STaniya Das goto destroy_pm_clk; 1683*15d09e83STaniya Das } 1684*15d09e83STaniya Das 1685*15d09e83STaniya Das clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 1686*15d09e83STaniya Das clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 1687*15d09e83STaniya Das clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 1688*15d09e83STaniya Das clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 1689*15d09e83STaniya Das 1690*15d09e83STaniya Das ret = qcom_cc_really_probe(pdev, &cam_cc_sc7180_desc, regmap); 1691*15d09e83STaniya Das 1692*15d09e83STaniya Das pm_clk_runtime_suspend(&pdev->dev); 1693*15d09e83STaniya Das 1694*15d09e83STaniya Das if (ret < 0) { 1695*15d09e83STaniya Das dev_err(&pdev->dev, "Failed to register CAM CC clocks\n"); 1696*15d09e83STaniya Das goto destroy_pm_clk; 1697*15d09e83STaniya Das } 1698*15d09e83STaniya Das 1699*15d09e83STaniya Das return 0; 1700*15d09e83STaniya Das 1701*15d09e83STaniya Das destroy_pm_clk: 1702*15d09e83STaniya Das pm_clk_destroy(&pdev->dev); 1703*15d09e83STaniya Das 1704*15d09e83STaniya Das disable_pm_runtime: 1705*15d09e83STaniya Das pm_runtime_disable(&pdev->dev); 1706*15d09e83STaniya Das 1707*15d09e83STaniya Das return ret; 1708*15d09e83STaniya Das } 1709*15d09e83STaniya Das 1710*15d09e83STaniya Das static const struct dev_pm_ops cam_cc_pm_ops = { 1711*15d09e83STaniya Das SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 1712*15d09e83STaniya Das }; 1713*15d09e83STaniya Das 1714*15d09e83STaniya Das static struct platform_driver cam_cc_sc7180_driver = { 1715*15d09e83STaniya Das .probe = cam_cc_sc7180_probe, 1716*15d09e83STaniya Das .driver = { 1717*15d09e83STaniya Das .name = "cam_cc-sc7180", 1718*15d09e83STaniya Das .of_match_table = cam_cc_sc7180_match_table, 1719*15d09e83STaniya Das .pm = &cam_cc_pm_ops, 1720*15d09e83STaniya Das }, 1721*15d09e83STaniya Das }; 1722*15d09e83STaniya Das 1723*15d09e83STaniya Das static int __init cam_cc_sc7180_init(void) 1724*15d09e83STaniya Das { 1725*15d09e83STaniya Das return platform_driver_register(&cam_cc_sc7180_driver); 1726*15d09e83STaniya Das } 1727*15d09e83STaniya Das subsys_initcall(cam_cc_sc7180_init); 1728*15d09e83STaniya Das 1729*15d09e83STaniya Das static void __exit cam_cc_sc7180_exit(void) 1730*15d09e83STaniya Das { 1731*15d09e83STaniya Das platform_driver_unregister(&cam_cc_sc7180_driver); 1732*15d09e83STaniya Das } 1733*15d09e83STaniya Das module_exit(cam_cc_sc7180_exit); 1734*15d09e83STaniya Das 1735*15d09e83STaniya Das MODULE_DESCRIPTION("QTI CAM_CC SC7180 Driver"); 1736*15d09e83STaniya Das MODULE_LICENSE("GPL v2"); 1737