1ecd2bacfSSivaprakash Murugesan // SPDX-License-Identifier: GPL-2.0 2ecd2bacfSSivaprakash Murugesan // Copyright (c) 2018, The Linux Foundation. All rights reserved. 3ecd2bacfSSivaprakash Murugesan #include <linux/clk-provider.h> 4ecd2bacfSSivaprakash Murugesan #include <linux/module.h> 5ecd2bacfSSivaprakash Murugesan #include <linux/platform_device.h> 6ecd2bacfSSivaprakash Murugesan #include <linux/regmap.h> 7ecd2bacfSSivaprakash Murugesan 8ecd2bacfSSivaprakash Murugesan #include "clk-alpha-pll.h" 9ecd2bacfSSivaprakash Murugesan 10ecd2bacfSSivaprakash Murugesan static const u8 ipq_pll_offsets[] = { 11ecd2bacfSSivaprakash Murugesan [PLL_OFF_L_VAL] = 0x08, 12ecd2bacfSSivaprakash Murugesan [PLL_OFF_ALPHA_VAL] = 0x10, 13ecd2bacfSSivaprakash Murugesan [PLL_OFF_USER_CTL] = 0x18, 14ecd2bacfSSivaprakash Murugesan [PLL_OFF_CONFIG_CTL] = 0x20, 15ecd2bacfSSivaprakash Murugesan [PLL_OFF_CONFIG_CTL_U] = 0x24, 16ecd2bacfSSivaprakash Murugesan [PLL_OFF_STATUS] = 0x28, 17ecd2bacfSSivaprakash Murugesan [PLL_OFF_TEST_CTL] = 0x30, 18ecd2bacfSSivaprakash Murugesan [PLL_OFF_TEST_CTL_U] = 0x34, 19ecd2bacfSSivaprakash Murugesan }; 20ecd2bacfSSivaprakash Murugesan 21ecd2bacfSSivaprakash Murugesan static struct clk_alpha_pll ipq_pll = { 22ecd2bacfSSivaprakash Murugesan .offset = 0x0, 23ecd2bacfSSivaprakash Murugesan .regs = ipq_pll_offsets, 24ecd2bacfSSivaprakash Murugesan .flags = SUPPORTS_DYNAMIC_UPDATE, 25ecd2bacfSSivaprakash Murugesan .clkr = { 26ecd2bacfSSivaprakash Murugesan .enable_reg = 0x0, 27ecd2bacfSSivaprakash Murugesan .enable_mask = BIT(0), 28ecd2bacfSSivaprakash Murugesan .hw.init = &(struct clk_init_data){ 29ecd2bacfSSivaprakash Murugesan .name = "a53pll", 30ecd2bacfSSivaprakash Murugesan .parent_data = &(const struct clk_parent_data) { 31ecd2bacfSSivaprakash Murugesan .fw_name = "xo", 32ecd2bacfSSivaprakash Murugesan }, 33ecd2bacfSSivaprakash Murugesan .num_parents = 1, 34ecd2bacfSSivaprakash Murugesan .ops = &clk_alpha_pll_huayra_ops, 35ecd2bacfSSivaprakash Murugesan }, 36ecd2bacfSSivaprakash Murugesan }, 37ecd2bacfSSivaprakash Murugesan }; 38ecd2bacfSSivaprakash Murugesan 39ecd2bacfSSivaprakash Murugesan static const struct alpha_pll_config ipq_pll_config = { 40ecd2bacfSSivaprakash Murugesan .l = 0x37, 41ecd2bacfSSivaprakash Murugesan .config_ctl_val = 0x04141200, 42ecd2bacfSSivaprakash Murugesan .config_ctl_hi_val = 0x0, 43ecd2bacfSSivaprakash Murugesan .early_output_mask = BIT(3), 44ecd2bacfSSivaprakash Murugesan .main_output_mask = BIT(0), 45ecd2bacfSSivaprakash Murugesan }; 46ecd2bacfSSivaprakash Murugesan 47ecd2bacfSSivaprakash Murugesan static const struct regmap_config ipq_pll_regmap_config = { 48ecd2bacfSSivaprakash Murugesan .reg_bits = 32, 49ecd2bacfSSivaprakash Murugesan .reg_stride = 4, 50ecd2bacfSSivaprakash Murugesan .val_bits = 32, 51ecd2bacfSSivaprakash Murugesan .max_register = 0x40, 52ecd2bacfSSivaprakash Murugesan .fast_io = true, 53ecd2bacfSSivaprakash Murugesan }; 54ecd2bacfSSivaprakash Murugesan 55ecd2bacfSSivaprakash Murugesan static int apss_ipq_pll_probe(struct platform_device *pdev) 56ecd2bacfSSivaprakash Murugesan { 57ecd2bacfSSivaprakash Murugesan struct device *dev = &pdev->dev; 58ecd2bacfSSivaprakash Murugesan struct regmap *regmap; 59ecd2bacfSSivaprakash Murugesan void __iomem *base; 60ecd2bacfSSivaprakash Murugesan int ret; 61ecd2bacfSSivaprakash Murugesan 62ecd2bacfSSivaprakash Murugesan base = devm_platform_ioremap_resource(pdev, 0); 63ecd2bacfSSivaprakash Murugesan if (IS_ERR(base)) 64ecd2bacfSSivaprakash Murugesan return PTR_ERR(base); 65ecd2bacfSSivaprakash Murugesan 66ecd2bacfSSivaprakash Murugesan regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config); 67ecd2bacfSSivaprakash Murugesan if (IS_ERR(regmap)) 68ecd2bacfSSivaprakash Murugesan return PTR_ERR(regmap); 69ecd2bacfSSivaprakash Murugesan 70ecd2bacfSSivaprakash Murugesan clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config); 71ecd2bacfSSivaprakash Murugesan 72ecd2bacfSSivaprakash Murugesan ret = devm_clk_register_regmap(dev, &ipq_pll.clkr); 73ecd2bacfSSivaprakash Murugesan if (ret) 74ecd2bacfSSivaprakash Murugesan return ret; 75ecd2bacfSSivaprakash Murugesan 76ecd2bacfSSivaprakash Murugesan return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 77ecd2bacfSSivaprakash Murugesan &ipq_pll.clkr.hw); 78ecd2bacfSSivaprakash Murugesan } 79ecd2bacfSSivaprakash Murugesan 80ecd2bacfSSivaprakash Murugesan static const struct of_device_id apss_ipq_pll_match_table[] = { 81ecd2bacfSSivaprakash Murugesan { .compatible = "qcom,ipq6018-a53pll" }, 82ecd2bacfSSivaprakash Murugesan { } 83ecd2bacfSSivaprakash Murugesan }; 84*d0a859edSChen Hui MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); 85ecd2bacfSSivaprakash Murugesan 86ecd2bacfSSivaprakash Murugesan static struct platform_driver apss_ipq_pll_driver = { 87ecd2bacfSSivaprakash Murugesan .probe = apss_ipq_pll_probe, 88ecd2bacfSSivaprakash Murugesan .driver = { 89ecd2bacfSSivaprakash Murugesan .name = "qcom-ipq-apss-pll", 90ecd2bacfSSivaprakash Murugesan .of_match_table = apss_ipq_pll_match_table, 91ecd2bacfSSivaprakash Murugesan }, 92ecd2bacfSSivaprakash Murugesan }; 93ecd2bacfSSivaprakash Murugesan module_platform_driver(apss_ipq_pll_driver); 94ecd2bacfSSivaprakash Murugesan 95ecd2bacfSSivaprakash Murugesan MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver"); 96ecd2bacfSSivaprakash Murugesan MODULE_LICENSE("GPL v2"); 97