1ecd2bacfSSivaprakash Murugesan // SPDX-License-Identifier: GPL-2.0 2ecd2bacfSSivaprakash Murugesan // Copyright (c) 2018, The Linux Foundation. All rights reserved. 3ecd2bacfSSivaprakash Murugesan #include <linux/clk-provider.h> 4ecd2bacfSSivaprakash Murugesan #include <linux/module.h> 5823a117eSRobert Marko #include <linux/of_device.h> 6ecd2bacfSSivaprakash Murugesan #include <linux/platform_device.h> 7ecd2bacfSSivaprakash Murugesan #include <linux/regmap.h> 8ecd2bacfSSivaprakash Murugesan 9ecd2bacfSSivaprakash Murugesan #include "clk-alpha-pll.h" 10ecd2bacfSSivaprakash Murugesan 11ecd2bacfSSivaprakash Murugesan static const u8 ipq_pll_offsets[] = { 12ecd2bacfSSivaprakash Murugesan [PLL_OFF_L_VAL] = 0x08, 13ecd2bacfSSivaprakash Murugesan [PLL_OFF_ALPHA_VAL] = 0x10, 14ecd2bacfSSivaprakash Murugesan [PLL_OFF_USER_CTL] = 0x18, 15ecd2bacfSSivaprakash Murugesan [PLL_OFF_CONFIG_CTL] = 0x20, 16ecd2bacfSSivaprakash Murugesan [PLL_OFF_CONFIG_CTL_U] = 0x24, 17ecd2bacfSSivaprakash Murugesan [PLL_OFF_STATUS] = 0x28, 18ecd2bacfSSivaprakash Murugesan [PLL_OFF_TEST_CTL] = 0x30, 19ecd2bacfSSivaprakash Murugesan [PLL_OFF_TEST_CTL_U] = 0x34, 20ecd2bacfSSivaprakash Murugesan }; 21ecd2bacfSSivaprakash Murugesan 22ecd2bacfSSivaprakash Murugesan static struct clk_alpha_pll ipq_pll = { 23ecd2bacfSSivaprakash Murugesan .offset = 0x0, 24ecd2bacfSSivaprakash Murugesan .regs = ipq_pll_offsets, 25ecd2bacfSSivaprakash Murugesan .flags = SUPPORTS_DYNAMIC_UPDATE, 26ecd2bacfSSivaprakash Murugesan .clkr = { 27ecd2bacfSSivaprakash Murugesan .enable_reg = 0x0, 28ecd2bacfSSivaprakash Murugesan .enable_mask = BIT(0), 29ecd2bacfSSivaprakash Murugesan .hw.init = &(struct clk_init_data){ 30ecd2bacfSSivaprakash Murugesan .name = "a53pll", 31ecd2bacfSSivaprakash Murugesan .parent_data = &(const struct clk_parent_data) { 32ecd2bacfSSivaprakash Murugesan .fw_name = "xo", 33ecd2bacfSSivaprakash Murugesan }, 34ecd2bacfSSivaprakash Murugesan .num_parents = 1, 35ecd2bacfSSivaprakash Murugesan .ops = &clk_alpha_pll_huayra_ops, 36ecd2bacfSSivaprakash Murugesan }, 37ecd2bacfSSivaprakash Murugesan }, 38ecd2bacfSSivaprakash Murugesan }; 39ecd2bacfSSivaprakash Murugesan 40823a117eSRobert Marko static const struct alpha_pll_config ipq6018_pll_config = { 41ecd2bacfSSivaprakash Murugesan .l = 0x37, 422a4d7024SRobert Marko .config_ctl_val = 0x240d4828, 432a4d7024SRobert Marko .config_ctl_hi_val = 0x6, 44ecd2bacfSSivaprakash Murugesan .early_output_mask = BIT(3), 452a4d7024SRobert Marko .aux2_output_mask = BIT(2), 462a4d7024SRobert Marko .aux_output_mask = BIT(1), 47ecd2bacfSSivaprakash Murugesan .main_output_mask = BIT(0), 482a4d7024SRobert Marko .test_ctl_val = 0x1c0000C0, 492a4d7024SRobert Marko .test_ctl_hi_val = 0x4000, 50ecd2bacfSSivaprakash Murugesan }; 51ecd2bacfSSivaprakash Murugesan 52*cca7b7d5SRobert Marko static const struct alpha_pll_config ipq8074_pll_config = { 53*cca7b7d5SRobert Marko .l = 0x48, 54*cca7b7d5SRobert Marko .config_ctl_val = 0x200d4828, 55*cca7b7d5SRobert Marko .config_ctl_hi_val = 0x6, 56*cca7b7d5SRobert Marko .early_output_mask = BIT(3), 57*cca7b7d5SRobert Marko .aux2_output_mask = BIT(2), 58*cca7b7d5SRobert Marko .aux_output_mask = BIT(1), 59*cca7b7d5SRobert Marko .main_output_mask = BIT(0), 60*cca7b7d5SRobert Marko .test_ctl_val = 0x1c000000, 61*cca7b7d5SRobert Marko .test_ctl_hi_val = 0x4000, 62*cca7b7d5SRobert Marko }; 63*cca7b7d5SRobert Marko 64ecd2bacfSSivaprakash Murugesan static const struct regmap_config ipq_pll_regmap_config = { 65ecd2bacfSSivaprakash Murugesan .reg_bits = 32, 66ecd2bacfSSivaprakash Murugesan .reg_stride = 4, 67ecd2bacfSSivaprakash Murugesan .val_bits = 32, 68ecd2bacfSSivaprakash Murugesan .max_register = 0x40, 69ecd2bacfSSivaprakash Murugesan .fast_io = true, 70ecd2bacfSSivaprakash Murugesan }; 71ecd2bacfSSivaprakash Murugesan 72ecd2bacfSSivaprakash Murugesan static int apss_ipq_pll_probe(struct platform_device *pdev) 73ecd2bacfSSivaprakash Murugesan { 74823a117eSRobert Marko const struct alpha_pll_config *ipq_pll_config; 75ecd2bacfSSivaprakash Murugesan struct device *dev = &pdev->dev; 76ecd2bacfSSivaprakash Murugesan struct regmap *regmap; 77ecd2bacfSSivaprakash Murugesan void __iomem *base; 78ecd2bacfSSivaprakash Murugesan int ret; 79ecd2bacfSSivaprakash Murugesan 80ecd2bacfSSivaprakash Murugesan base = devm_platform_ioremap_resource(pdev, 0); 81ecd2bacfSSivaprakash Murugesan if (IS_ERR(base)) 82ecd2bacfSSivaprakash Murugesan return PTR_ERR(base); 83ecd2bacfSSivaprakash Murugesan 84ecd2bacfSSivaprakash Murugesan regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config); 85ecd2bacfSSivaprakash Murugesan if (IS_ERR(regmap)) 86ecd2bacfSSivaprakash Murugesan return PTR_ERR(regmap); 87ecd2bacfSSivaprakash Murugesan 88823a117eSRobert Marko ipq_pll_config = of_device_get_match_data(&pdev->dev); 89823a117eSRobert Marko if (!ipq_pll_config) 90823a117eSRobert Marko return -ENODEV; 91823a117eSRobert Marko 92823a117eSRobert Marko clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config); 93ecd2bacfSSivaprakash Murugesan 94ecd2bacfSSivaprakash Murugesan ret = devm_clk_register_regmap(dev, &ipq_pll.clkr); 95ecd2bacfSSivaprakash Murugesan if (ret) 96ecd2bacfSSivaprakash Murugesan return ret; 97ecd2bacfSSivaprakash Murugesan 98ecd2bacfSSivaprakash Murugesan return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 99ecd2bacfSSivaprakash Murugesan &ipq_pll.clkr.hw); 100ecd2bacfSSivaprakash Murugesan } 101ecd2bacfSSivaprakash Murugesan 102ecd2bacfSSivaprakash Murugesan static const struct of_device_id apss_ipq_pll_match_table[] = { 103823a117eSRobert Marko { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config }, 104*cca7b7d5SRobert Marko { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config }, 105ecd2bacfSSivaprakash Murugesan { } 106ecd2bacfSSivaprakash Murugesan }; 107d0a859edSChen Hui MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); 108ecd2bacfSSivaprakash Murugesan 109ecd2bacfSSivaprakash Murugesan static struct platform_driver apss_ipq_pll_driver = { 110ecd2bacfSSivaprakash Murugesan .probe = apss_ipq_pll_probe, 111ecd2bacfSSivaprakash Murugesan .driver = { 112ecd2bacfSSivaprakash Murugesan .name = "qcom-ipq-apss-pll", 113ecd2bacfSSivaprakash Murugesan .of_match_table = apss_ipq_pll_match_table, 114ecd2bacfSSivaprakash Murugesan }, 115ecd2bacfSSivaprakash Murugesan }; 116ecd2bacfSSivaprakash Murugesan module_platform_driver(apss_ipq_pll_driver); 117ecd2bacfSSivaprakash Murugesan 118ecd2bacfSSivaprakash Murugesan MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver"); 119ecd2bacfSSivaprakash Murugesan MODULE_LICENSE("GPL v2"); 120