1ecd2bacfSSivaprakash Murugesan // SPDX-License-Identifier: GPL-2.0 2ecd2bacfSSivaprakash Murugesan // Copyright (c) 2018, The Linux Foundation. All rights reserved. 3ecd2bacfSSivaprakash Murugesan #include <linux/clk-provider.h> 4ecd2bacfSSivaprakash Murugesan #include <linux/module.h> 5823a117eSRobert Marko #include <linux/of_device.h> 6ecd2bacfSSivaprakash Murugesan #include <linux/platform_device.h> 7ecd2bacfSSivaprakash Murugesan #include <linux/regmap.h> 8ecd2bacfSSivaprakash Murugesan 9ecd2bacfSSivaprakash Murugesan #include "clk-alpha-pll.h" 10ecd2bacfSSivaprakash Murugesan 111d83f18bSKathiravan T /* 121d83f18bSKathiravan T * Even though APSS PLL type is of existing one (like Huayra), its offsets 131d83f18bSKathiravan T * are different from the one mentioned in the clk-alpha-pll.c, since the 141d83f18bSKathiravan T * PLL is specific to APSS, so lets the define the same. 151d83f18bSKathiravan T */ 161d83f18bSKathiravan T static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = { 171d83f18bSKathiravan T [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 18ecd2bacfSSivaprakash Murugesan [PLL_OFF_L_VAL] = 0x08, 19ecd2bacfSSivaprakash Murugesan [PLL_OFF_ALPHA_VAL] = 0x10, 20ecd2bacfSSivaprakash Murugesan [PLL_OFF_USER_CTL] = 0x18, 21ecd2bacfSSivaprakash Murugesan [PLL_OFF_CONFIG_CTL] = 0x20, 22ecd2bacfSSivaprakash Murugesan [PLL_OFF_CONFIG_CTL_U] = 0x24, 23ecd2bacfSSivaprakash Murugesan [PLL_OFF_STATUS] = 0x28, 24ecd2bacfSSivaprakash Murugesan [PLL_OFF_TEST_CTL] = 0x30, 25ecd2bacfSSivaprakash Murugesan [PLL_OFF_TEST_CTL_U] = 0x34, 261d83f18bSKathiravan T }, 27*c7ef7fbbSKathiravan T [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 28*c7ef7fbbSKathiravan T [PLL_OFF_L_VAL] = 0x08, 29*c7ef7fbbSKathiravan T [PLL_OFF_ALPHA_VAL] = 0x10, 30*c7ef7fbbSKathiravan T [PLL_OFF_ALPHA_VAL_U] = 0x14, 31*c7ef7fbbSKathiravan T [PLL_OFF_USER_CTL] = 0x18, 32*c7ef7fbbSKathiravan T [PLL_OFF_USER_CTL_U] = 0x1c, 33*c7ef7fbbSKathiravan T [PLL_OFF_CONFIG_CTL] = 0x20, 34*c7ef7fbbSKathiravan T [PLL_OFF_STATUS] = 0x28, 35*c7ef7fbbSKathiravan T [PLL_OFF_TEST_CTL] = 0x30, 36*c7ef7fbbSKathiravan T [PLL_OFF_TEST_CTL_U] = 0x34, 37*c7ef7fbbSKathiravan T }, 38ecd2bacfSSivaprakash Murugesan }; 39ecd2bacfSSivaprakash Murugesan 401d83f18bSKathiravan T static struct clk_alpha_pll ipq_pll_huayra = { 41ecd2bacfSSivaprakash Murugesan .offset = 0x0, 421d83f18bSKathiravan T .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA], 43ecd2bacfSSivaprakash Murugesan .flags = SUPPORTS_DYNAMIC_UPDATE, 44ecd2bacfSSivaprakash Murugesan .clkr = { 45ecd2bacfSSivaprakash Murugesan .enable_reg = 0x0, 46ecd2bacfSSivaprakash Murugesan .enable_mask = BIT(0), 47ecd2bacfSSivaprakash Murugesan .hw.init = &(struct clk_init_data){ 48ecd2bacfSSivaprakash Murugesan .name = "a53pll", 49ecd2bacfSSivaprakash Murugesan .parent_data = &(const struct clk_parent_data) { 50ecd2bacfSSivaprakash Murugesan .fw_name = "xo", 51ecd2bacfSSivaprakash Murugesan }, 52ecd2bacfSSivaprakash Murugesan .num_parents = 1, 53ecd2bacfSSivaprakash Murugesan .ops = &clk_alpha_pll_huayra_ops, 54ecd2bacfSSivaprakash Murugesan }, 55ecd2bacfSSivaprakash Murugesan }, 56ecd2bacfSSivaprakash Murugesan }; 57ecd2bacfSSivaprakash Murugesan 58*c7ef7fbbSKathiravan T static struct clk_alpha_pll ipq_pll_stromer_plus = { 59*c7ef7fbbSKathiravan T .offset = 0x0, 60*c7ef7fbbSKathiravan T .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], 61*c7ef7fbbSKathiravan T .flags = SUPPORTS_DYNAMIC_UPDATE, 62*c7ef7fbbSKathiravan T .clkr = { 63*c7ef7fbbSKathiravan T .enable_reg = 0x0, 64*c7ef7fbbSKathiravan T .enable_mask = BIT(0), 65*c7ef7fbbSKathiravan T .hw.init = &(struct clk_init_data){ 66*c7ef7fbbSKathiravan T .name = "a53pll", 67*c7ef7fbbSKathiravan T .parent_data = &(const struct clk_parent_data) { 68*c7ef7fbbSKathiravan T .fw_name = "xo", 69*c7ef7fbbSKathiravan T }, 70*c7ef7fbbSKathiravan T .num_parents = 1, 71*c7ef7fbbSKathiravan T .ops = &clk_alpha_pll_stromer_ops, 72*c7ef7fbbSKathiravan T }, 73*c7ef7fbbSKathiravan T }, 74*c7ef7fbbSKathiravan T }; 75*c7ef7fbbSKathiravan T 76*c7ef7fbbSKathiravan T static const struct alpha_pll_config ipq5332_pll_config = { 77*c7ef7fbbSKathiravan T .l = 0x3e, 78*c7ef7fbbSKathiravan T .config_ctl_val = 0x4001075b, 79*c7ef7fbbSKathiravan T .config_ctl_hi_val = 0x304, 80*c7ef7fbbSKathiravan T .main_output_mask = BIT(0), 81*c7ef7fbbSKathiravan T .aux_output_mask = BIT(1), 82*c7ef7fbbSKathiravan T .early_output_mask = BIT(3), 83*c7ef7fbbSKathiravan T .alpha_en_mask = BIT(24), 84*c7ef7fbbSKathiravan T .status_val = 0x3, 85*c7ef7fbbSKathiravan T .status_mask = GENMASK(10, 8), 86*c7ef7fbbSKathiravan T .lock_det = BIT(2), 87*c7ef7fbbSKathiravan T .test_ctl_hi_val = 0x00400003, 88*c7ef7fbbSKathiravan T }; 89*c7ef7fbbSKathiravan T 90823a117eSRobert Marko static const struct alpha_pll_config ipq6018_pll_config = { 91ecd2bacfSSivaprakash Murugesan .l = 0x37, 922a4d7024SRobert Marko .config_ctl_val = 0x240d4828, 932a4d7024SRobert Marko .config_ctl_hi_val = 0x6, 94ecd2bacfSSivaprakash Murugesan .early_output_mask = BIT(3), 952a4d7024SRobert Marko .aux2_output_mask = BIT(2), 962a4d7024SRobert Marko .aux_output_mask = BIT(1), 97ecd2bacfSSivaprakash Murugesan .main_output_mask = BIT(0), 982a4d7024SRobert Marko .test_ctl_val = 0x1c0000C0, 992a4d7024SRobert Marko .test_ctl_hi_val = 0x4000, 100ecd2bacfSSivaprakash Murugesan }; 101ecd2bacfSSivaprakash Murugesan 102cca7b7d5SRobert Marko static const struct alpha_pll_config ipq8074_pll_config = { 103cca7b7d5SRobert Marko .l = 0x48, 104cca7b7d5SRobert Marko .config_ctl_val = 0x200d4828, 105cca7b7d5SRobert Marko .config_ctl_hi_val = 0x6, 106cca7b7d5SRobert Marko .early_output_mask = BIT(3), 107cca7b7d5SRobert Marko .aux2_output_mask = BIT(2), 108cca7b7d5SRobert Marko .aux_output_mask = BIT(1), 109cca7b7d5SRobert Marko .main_output_mask = BIT(0), 110cca7b7d5SRobert Marko .test_ctl_val = 0x1c000000, 111cca7b7d5SRobert Marko .test_ctl_hi_val = 0x4000, 112cca7b7d5SRobert Marko }; 113cca7b7d5SRobert Marko 1141d83f18bSKathiravan T struct apss_pll_data { 115*c7ef7fbbSKathiravan T int pll_type; 1161d83f18bSKathiravan T struct clk_alpha_pll *pll; 1171d83f18bSKathiravan T const struct alpha_pll_config *pll_config; 1181d83f18bSKathiravan T }; 1191d83f18bSKathiravan T 120*c7ef7fbbSKathiravan T static struct apss_pll_data ipq5332_pll_data = { 121*c7ef7fbbSKathiravan T .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, 122*c7ef7fbbSKathiravan T .pll = &ipq_pll_stromer_plus, 123*c7ef7fbbSKathiravan T .pll_config = &ipq5332_pll_config, 124*c7ef7fbbSKathiravan T }; 125*c7ef7fbbSKathiravan T 1261d83f18bSKathiravan T static struct apss_pll_data ipq8074_pll_data = { 127*c7ef7fbbSKathiravan T .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, 1281d83f18bSKathiravan T .pll = &ipq_pll_huayra, 1291d83f18bSKathiravan T .pll_config = &ipq8074_pll_config, 1301d83f18bSKathiravan T }; 1311d83f18bSKathiravan T 1321d83f18bSKathiravan T static struct apss_pll_data ipq6018_pll_data = { 133*c7ef7fbbSKathiravan T .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, 1341d83f18bSKathiravan T .pll = &ipq_pll_huayra, 1351d83f18bSKathiravan T .pll_config = &ipq6018_pll_config, 1361d83f18bSKathiravan T }; 1371d83f18bSKathiravan T 138ecd2bacfSSivaprakash Murugesan static const struct regmap_config ipq_pll_regmap_config = { 139ecd2bacfSSivaprakash Murugesan .reg_bits = 32, 140ecd2bacfSSivaprakash Murugesan .reg_stride = 4, 141ecd2bacfSSivaprakash Murugesan .val_bits = 32, 142ecd2bacfSSivaprakash Murugesan .max_register = 0x40, 143ecd2bacfSSivaprakash Murugesan .fast_io = true, 144ecd2bacfSSivaprakash Murugesan }; 145ecd2bacfSSivaprakash Murugesan 146ecd2bacfSSivaprakash Murugesan static int apss_ipq_pll_probe(struct platform_device *pdev) 147ecd2bacfSSivaprakash Murugesan { 1481d83f18bSKathiravan T const struct apss_pll_data *data; 149ecd2bacfSSivaprakash Murugesan struct device *dev = &pdev->dev; 150ecd2bacfSSivaprakash Murugesan struct regmap *regmap; 151ecd2bacfSSivaprakash Murugesan void __iomem *base; 152ecd2bacfSSivaprakash Murugesan int ret; 153ecd2bacfSSivaprakash Murugesan 154ecd2bacfSSivaprakash Murugesan base = devm_platform_ioremap_resource(pdev, 0); 155ecd2bacfSSivaprakash Murugesan if (IS_ERR(base)) 156ecd2bacfSSivaprakash Murugesan return PTR_ERR(base); 157ecd2bacfSSivaprakash Murugesan 158ecd2bacfSSivaprakash Murugesan regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config); 159ecd2bacfSSivaprakash Murugesan if (IS_ERR(regmap)) 160ecd2bacfSSivaprakash Murugesan return PTR_ERR(regmap); 161ecd2bacfSSivaprakash Murugesan 1621d83f18bSKathiravan T data = of_device_get_match_data(&pdev->dev); 1631d83f18bSKathiravan T if (!data) 164823a117eSRobert Marko return -ENODEV; 165823a117eSRobert Marko 166*c7ef7fbbSKathiravan T if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) 1671d83f18bSKathiravan T clk_alpha_pll_configure(data->pll, regmap, data->pll_config); 168*c7ef7fbbSKathiravan T else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) 169*c7ef7fbbSKathiravan T clk_stromer_pll_configure(data->pll, regmap, data->pll_config); 170ecd2bacfSSivaprakash Murugesan 1711d83f18bSKathiravan T ret = devm_clk_register_regmap(dev, &data->pll->clkr); 172ecd2bacfSSivaprakash Murugesan if (ret) 173ecd2bacfSSivaprakash Murugesan return ret; 174ecd2bacfSSivaprakash Murugesan 175ecd2bacfSSivaprakash Murugesan return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1761d83f18bSKathiravan T &data->pll->clkr.hw); 177ecd2bacfSSivaprakash Murugesan } 178ecd2bacfSSivaprakash Murugesan 179ecd2bacfSSivaprakash Murugesan static const struct of_device_id apss_ipq_pll_match_table[] = { 180*c7ef7fbbSKathiravan T { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, 1811d83f18bSKathiravan T { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, 1821d83f18bSKathiravan T { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, 183ecd2bacfSSivaprakash Murugesan { } 184ecd2bacfSSivaprakash Murugesan }; 185d0a859edSChen Hui MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); 186ecd2bacfSSivaprakash Murugesan 187ecd2bacfSSivaprakash Murugesan static struct platform_driver apss_ipq_pll_driver = { 188ecd2bacfSSivaprakash Murugesan .probe = apss_ipq_pll_probe, 189ecd2bacfSSivaprakash Murugesan .driver = { 190ecd2bacfSSivaprakash Murugesan .name = "qcom-ipq-apss-pll", 191ecd2bacfSSivaprakash Murugesan .of_match_table = apss_ipq_pll_match_table, 192ecd2bacfSSivaprakash Murugesan }, 193ecd2bacfSSivaprakash Murugesan }; 194ecd2bacfSSivaprakash Murugesan module_platform_driver(apss_ipq_pll_driver); 195ecd2bacfSSivaprakash Murugesan 196ecd2bacfSSivaprakash Murugesan MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver"); 197ecd2bacfSSivaprakash Murugesan MODULE_LICENSE("GPL v2"); 198