1ecd2bacfSSivaprakash Murugesan // SPDX-License-Identifier: GPL-2.0 2ecd2bacfSSivaprakash Murugesan // Copyright (c) 2018, The Linux Foundation. All rights reserved. 3ecd2bacfSSivaprakash Murugesan #include <linux/clk-provider.h> 4ecd2bacfSSivaprakash Murugesan #include <linux/module.h> 5*a96cbb14SRob Herring #include <linux/of.h> 6ecd2bacfSSivaprakash Murugesan #include <linux/platform_device.h> 7ecd2bacfSSivaprakash Murugesan #include <linux/regmap.h> 8ecd2bacfSSivaprakash Murugesan 9ecd2bacfSSivaprakash Murugesan #include "clk-alpha-pll.h" 10ecd2bacfSSivaprakash Murugesan 111d83f18bSKathiravan T /* 121d83f18bSKathiravan T * Even though APSS PLL type is of existing one (like Huayra), its offsets 131d83f18bSKathiravan T * are different from the one mentioned in the clk-alpha-pll.c, since the 141d83f18bSKathiravan T * PLL is specific to APSS, so lets the define the same. 151d83f18bSKathiravan T */ 161d83f18bSKathiravan T static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = { 171d83f18bSKathiravan T [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 18ecd2bacfSSivaprakash Murugesan [PLL_OFF_L_VAL] = 0x08, 19ecd2bacfSSivaprakash Murugesan [PLL_OFF_ALPHA_VAL] = 0x10, 20ecd2bacfSSivaprakash Murugesan [PLL_OFF_USER_CTL] = 0x18, 21ecd2bacfSSivaprakash Murugesan [PLL_OFF_CONFIG_CTL] = 0x20, 22ecd2bacfSSivaprakash Murugesan [PLL_OFF_CONFIG_CTL_U] = 0x24, 23ecd2bacfSSivaprakash Murugesan [PLL_OFF_STATUS] = 0x28, 24ecd2bacfSSivaprakash Murugesan [PLL_OFF_TEST_CTL] = 0x30, 25ecd2bacfSSivaprakash Murugesan [PLL_OFF_TEST_CTL_U] = 0x34, 261d83f18bSKathiravan T }, 27c7ef7fbbSKathiravan T [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 28c7ef7fbbSKathiravan T [PLL_OFF_L_VAL] = 0x08, 29c7ef7fbbSKathiravan T [PLL_OFF_ALPHA_VAL] = 0x10, 30c7ef7fbbSKathiravan T [PLL_OFF_ALPHA_VAL_U] = 0x14, 31c7ef7fbbSKathiravan T [PLL_OFF_USER_CTL] = 0x18, 32c7ef7fbbSKathiravan T [PLL_OFF_USER_CTL_U] = 0x1c, 33c7ef7fbbSKathiravan T [PLL_OFF_CONFIG_CTL] = 0x20, 34c7ef7fbbSKathiravan T [PLL_OFF_STATUS] = 0x28, 35c7ef7fbbSKathiravan T [PLL_OFF_TEST_CTL] = 0x30, 36c7ef7fbbSKathiravan T [PLL_OFF_TEST_CTL_U] = 0x34, 37c7ef7fbbSKathiravan T }, 38ecd2bacfSSivaprakash Murugesan }; 39ecd2bacfSSivaprakash Murugesan 401d83f18bSKathiravan T static struct clk_alpha_pll ipq_pll_huayra = { 41ecd2bacfSSivaprakash Murugesan .offset = 0x0, 421d83f18bSKathiravan T .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA], 43ecd2bacfSSivaprakash Murugesan .flags = SUPPORTS_DYNAMIC_UPDATE, 44ecd2bacfSSivaprakash Murugesan .clkr = { 45ecd2bacfSSivaprakash Murugesan .enable_reg = 0x0, 46ecd2bacfSSivaprakash Murugesan .enable_mask = BIT(0), 47ecd2bacfSSivaprakash Murugesan .hw.init = &(struct clk_init_data){ 48ecd2bacfSSivaprakash Murugesan .name = "a53pll", 49ecd2bacfSSivaprakash Murugesan .parent_data = &(const struct clk_parent_data) { 50ecd2bacfSSivaprakash Murugesan .fw_name = "xo", 51ecd2bacfSSivaprakash Murugesan }, 52ecd2bacfSSivaprakash Murugesan .num_parents = 1, 53ecd2bacfSSivaprakash Murugesan .ops = &clk_alpha_pll_huayra_ops, 54ecd2bacfSSivaprakash Murugesan }, 55ecd2bacfSSivaprakash Murugesan }, 56ecd2bacfSSivaprakash Murugesan }; 57ecd2bacfSSivaprakash Murugesan 58c7ef7fbbSKathiravan T static struct clk_alpha_pll ipq_pll_stromer_plus = { 59c7ef7fbbSKathiravan T .offset = 0x0, 60c7ef7fbbSKathiravan T .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], 61c7ef7fbbSKathiravan T .flags = SUPPORTS_DYNAMIC_UPDATE, 62c7ef7fbbSKathiravan T .clkr = { 63c7ef7fbbSKathiravan T .enable_reg = 0x0, 64c7ef7fbbSKathiravan T .enable_mask = BIT(0), 65c7ef7fbbSKathiravan T .hw.init = &(struct clk_init_data){ 66c7ef7fbbSKathiravan T .name = "a53pll", 67c7ef7fbbSKathiravan T .parent_data = &(const struct clk_parent_data) { 68c7ef7fbbSKathiravan T .fw_name = "xo", 69c7ef7fbbSKathiravan T }, 70c7ef7fbbSKathiravan T .num_parents = 1, 71c7ef7fbbSKathiravan T .ops = &clk_alpha_pll_stromer_ops, 72c7ef7fbbSKathiravan T }, 73c7ef7fbbSKathiravan T }, 74c7ef7fbbSKathiravan T }; 75c7ef7fbbSKathiravan T 76c7ef7fbbSKathiravan T static const struct alpha_pll_config ipq5332_pll_config = { 77c7ef7fbbSKathiravan T .l = 0x3e, 78c7ef7fbbSKathiravan T .config_ctl_val = 0x4001075b, 79c7ef7fbbSKathiravan T .config_ctl_hi_val = 0x304, 80c7ef7fbbSKathiravan T .main_output_mask = BIT(0), 81c7ef7fbbSKathiravan T .aux_output_mask = BIT(1), 82c7ef7fbbSKathiravan T .early_output_mask = BIT(3), 83c7ef7fbbSKathiravan T .alpha_en_mask = BIT(24), 84c7ef7fbbSKathiravan T .status_val = 0x3, 85c7ef7fbbSKathiravan T .status_mask = GENMASK(10, 8), 86c7ef7fbbSKathiravan T .lock_det = BIT(2), 87c7ef7fbbSKathiravan T .test_ctl_hi_val = 0x00400003, 88c7ef7fbbSKathiravan T }; 89c7ef7fbbSKathiravan T 90823a117eSRobert Marko static const struct alpha_pll_config ipq6018_pll_config = { 91ecd2bacfSSivaprakash Murugesan .l = 0x37, 922a4d7024SRobert Marko .config_ctl_val = 0x240d4828, 932a4d7024SRobert Marko .config_ctl_hi_val = 0x6, 94ecd2bacfSSivaprakash Murugesan .early_output_mask = BIT(3), 952a4d7024SRobert Marko .aux2_output_mask = BIT(2), 962a4d7024SRobert Marko .aux_output_mask = BIT(1), 97ecd2bacfSSivaprakash Murugesan .main_output_mask = BIT(0), 982a4d7024SRobert Marko .test_ctl_val = 0x1c0000C0, 992a4d7024SRobert Marko .test_ctl_hi_val = 0x4000, 100ecd2bacfSSivaprakash Murugesan }; 101ecd2bacfSSivaprakash Murugesan 102cca7b7d5SRobert Marko static const struct alpha_pll_config ipq8074_pll_config = { 103cca7b7d5SRobert Marko .l = 0x48, 104cca7b7d5SRobert Marko .config_ctl_val = 0x200d4828, 105cca7b7d5SRobert Marko .config_ctl_hi_val = 0x6, 106cca7b7d5SRobert Marko .early_output_mask = BIT(3), 107cca7b7d5SRobert Marko .aux2_output_mask = BIT(2), 108cca7b7d5SRobert Marko .aux_output_mask = BIT(1), 109cca7b7d5SRobert Marko .main_output_mask = BIT(0), 110cca7b7d5SRobert Marko .test_ctl_val = 0x1c000000, 111cca7b7d5SRobert Marko .test_ctl_hi_val = 0x4000, 112cca7b7d5SRobert Marko }; 113cca7b7d5SRobert Marko 11420beb85fSDevi Priya static const struct alpha_pll_config ipq9574_pll_config = { 11520beb85fSDevi Priya .l = 0x3b, 11620beb85fSDevi Priya .config_ctl_val = 0x200d4828, 11720beb85fSDevi Priya .config_ctl_hi_val = 0x6, 11820beb85fSDevi Priya .early_output_mask = BIT(3), 11920beb85fSDevi Priya .aux2_output_mask = BIT(2), 12020beb85fSDevi Priya .aux_output_mask = BIT(1), 12120beb85fSDevi Priya .main_output_mask = BIT(0), 12220beb85fSDevi Priya .test_ctl_val = 0x0, 12320beb85fSDevi Priya .test_ctl_hi_val = 0x4000, 12420beb85fSDevi Priya }; 12520beb85fSDevi Priya 1261d83f18bSKathiravan T struct apss_pll_data { 127c7ef7fbbSKathiravan T int pll_type; 1281d83f18bSKathiravan T struct clk_alpha_pll *pll; 1291d83f18bSKathiravan T const struct alpha_pll_config *pll_config; 1301d83f18bSKathiravan T }; 1311d83f18bSKathiravan T 132c7ef7fbbSKathiravan T static struct apss_pll_data ipq5332_pll_data = { 133c7ef7fbbSKathiravan T .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, 134c7ef7fbbSKathiravan T .pll = &ipq_pll_stromer_plus, 135c7ef7fbbSKathiravan T .pll_config = &ipq5332_pll_config, 136c7ef7fbbSKathiravan T }; 137c7ef7fbbSKathiravan T 1381d83f18bSKathiravan T static struct apss_pll_data ipq8074_pll_data = { 139c7ef7fbbSKathiravan T .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, 1401d83f18bSKathiravan T .pll = &ipq_pll_huayra, 1411d83f18bSKathiravan T .pll_config = &ipq8074_pll_config, 1421d83f18bSKathiravan T }; 1431d83f18bSKathiravan T 1441d83f18bSKathiravan T static struct apss_pll_data ipq6018_pll_data = { 145c7ef7fbbSKathiravan T .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, 1461d83f18bSKathiravan T .pll = &ipq_pll_huayra, 1471d83f18bSKathiravan T .pll_config = &ipq6018_pll_config, 1481d83f18bSKathiravan T }; 1491d83f18bSKathiravan T 15020beb85fSDevi Priya static struct apss_pll_data ipq9574_pll_data = { 15120beb85fSDevi Priya .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, 15220beb85fSDevi Priya .pll = &ipq_pll_huayra, 15320beb85fSDevi Priya .pll_config = &ipq9574_pll_config, 15420beb85fSDevi Priya }; 15520beb85fSDevi Priya 156ecd2bacfSSivaprakash Murugesan static const struct regmap_config ipq_pll_regmap_config = { 157ecd2bacfSSivaprakash Murugesan .reg_bits = 32, 158ecd2bacfSSivaprakash Murugesan .reg_stride = 4, 159ecd2bacfSSivaprakash Murugesan .val_bits = 32, 160ecd2bacfSSivaprakash Murugesan .max_register = 0x40, 161ecd2bacfSSivaprakash Murugesan .fast_io = true, 162ecd2bacfSSivaprakash Murugesan }; 163ecd2bacfSSivaprakash Murugesan 164ecd2bacfSSivaprakash Murugesan static int apss_ipq_pll_probe(struct platform_device *pdev) 165ecd2bacfSSivaprakash Murugesan { 1661d83f18bSKathiravan T const struct apss_pll_data *data; 167ecd2bacfSSivaprakash Murugesan struct device *dev = &pdev->dev; 168ecd2bacfSSivaprakash Murugesan struct regmap *regmap; 169ecd2bacfSSivaprakash Murugesan void __iomem *base; 170ecd2bacfSSivaprakash Murugesan int ret; 171ecd2bacfSSivaprakash Murugesan 172ecd2bacfSSivaprakash Murugesan base = devm_platform_ioremap_resource(pdev, 0); 173ecd2bacfSSivaprakash Murugesan if (IS_ERR(base)) 174ecd2bacfSSivaprakash Murugesan return PTR_ERR(base); 175ecd2bacfSSivaprakash Murugesan 176ecd2bacfSSivaprakash Murugesan regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config); 177ecd2bacfSSivaprakash Murugesan if (IS_ERR(regmap)) 178ecd2bacfSSivaprakash Murugesan return PTR_ERR(regmap); 179ecd2bacfSSivaprakash Murugesan 1801d83f18bSKathiravan T data = of_device_get_match_data(&pdev->dev); 1811d83f18bSKathiravan T if (!data) 182823a117eSRobert Marko return -ENODEV; 183823a117eSRobert Marko 184c7ef7fbbSKathiravan T if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) 1851d83f18bSKathiravan T clk_alpha_pll_configure(data->pll, regmap, data->pll_config); 186c7ef7fbbSKathiravan T else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) 187c7ef7fbbSKathiravan T clk_stromer_pll_configure(data->pll, regmap, data->pll_config); 188ecd2bacfSSivaprakash Murugesan 1891d83f18bSKathiravan T ret = devm_clk_register_regmap(dev, &data->pll->clkr); 190ecd2bacfSSivaprakash Murugesan if (ret) 191ecd2bacfSSivaprakash Murugesan return ret; 192ecd2bacfSSivaprakash Murugesan 193ecd2bacfSSivaprakash Murugesan return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1941d83f18bSKathiravan T &data->pll->clkr.hw); 195ecd2bacfSSivaprakash Murugesan } 196ecd2bacfSSivaprakash Murugesan 197ecd2bacfSSivaprakash Murugesan static const struct of_device_id apss_ipq_pll_match_table[] = { 198c7ef7fbbSKathiravan T { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, 1991d83f18bSKathiravan T { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, 2001d83f18bSKathiravan T { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, 20120beb85fSDevi Priya { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data }, 202ecd2bacfSSivaprakash Murugesan { } 203ecd2bacfSSivaprakash Murugesan }; 204d0a859edSChen Hui MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); 205ecd2bacfSSivaprakash Murugesan 206ecd2bacfSSivaprakash Murugesan static struct platform_driver apss_ipq_pll_driver = { 207ecd2bacfSSivaprakash Murugesan .probe = apss_ipq_pll_probe, 208ecd2bacfSSivaprakash Murugesan .driver = { 209ecd2bacfSSivaprakash Murugesan .name = "qcom-ipq-apss-pll", 210ecd2bacfSSivaprakash Murugesan .of_match_table = apss_ipq_pll_match_table, 211ecd2bacfSSivaprakash Murugesan }, 212ecd2bacfSSivaprakash Murugesan }; 213ecd2bacfSSivaprakash Murugesan module_platform_driver(apss_ipq_pll_driver); 214ecd2bacfSSivaprakash Murugesan 215ecd2bacfSSivaprakash Murugesan MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver"); 216ecd2bacfSSivaprakash Murugesan MODULE_LICENSE("GPL v2"); 217