15a5223ffSManivannan Sadhasivam // SPDX-License-Identifier: GPL-2.0
25a5223ffSManivannan Sadhasivam /*
35a5223ffSManivannan Sadhasivam * Qualcomm A7 PLL driver
45a5223ffSManivannan Sadhasivam *
55a5223ffSManivannan Sadhasivam * Copyright (c) 2020, Linaro Limited
65a5223ffSManivannan Sadhasivam * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
75a5223ffSManivannan Sadhasivam */
85a5223ffSManivannan Sadhasivam
95a5223ffSManivannan Sadhasivam #include <linux/clk-provider.h>
105a5223ffSManivannan Sadhasivam #include <linux/module.h>
115a5223ffSManivannan Sadhasivam #include <linux/platform_device.h>
125a5223ffSManivannan Sadhasivam #include <linux/regmap.h>
135a5223ffSManivannan Sadhasivam
145a5223ffSManivannan Sadhasivam #include "clk-alpha-pll.h"
155a5223ffSManivannan Sadhasivam
165a5223ffSManivannan Sadhasivam #define LUCID_PLL_OFF_L_VAL 0x04
175a5223ffSManivannan Sadhasivam
185a5223ffSManivannan Sadhasivam static const struct pll_vco lucid_vco[] = {
195a5223ffSManivannan Sadhasivam { 249600000, 2000000000, 0 },
205a5223ffSManivannan Sadhasivam };
215a5223ffSManivannan Sadhasivam
225a5223ffSManivannan Sadhasivam static struct clk_alpha_pll a7pll = {
235a5223ffSManivannan Sadhasivam .offset = 0x100,
245a5223ffSManivannan Sadhasivam .vco_table = lucid_vco,
255a5223ffSManivannan Sadhasivam .num_vco = ARRAY_SIZE(lucid_vco),
265a5223ffSManivannan Sadhasivam .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
275a5223ffSManivannan Sadhasivam .clkr = {
285a5223ffSManivannan Sadhasivam .hw.init = &(struct clk_init_data){
295a5223ffSManivannan Sadhasivam .name = "a7pll",
305a5223ffSManivannan Sadhasivam .parent_data = &(const struct clk_parent_data){
315a5223ffSManivannan Sadhasivam .fw_name = "bi_tcxo",
325a5223ffSManivannan Sadhasivam },
335a5223ffSManivannan Sadhasivam .num_parents = 1,
345a5223ffSManivannan Sadhasivam .ops = &clk_alpha_pll_lucid_ops,
355a5223ffSManivannan Sadhasivam },
365a5223ffSManivannan Sadhasivam },
375a5223ffSManivannan Sadhasivam };
385a5223ffSManivannan Sadhasivam
395a5223ffSManivannan Sadhasivam static const struct alpha_pll_config a7pll_config = {
405a5223ffSManivannan Sadhasivam .l = 0x39,
415a5223ffSManivannan Sadhasivam .config_ctl_val = 0x20485699,
425a5223ffSManivannan Sadhasivam .config_ctl_hi_val = 0x2261,
435a5223ffSManivannan Sadhasivam .config_ctl_hi1_val = 0x029A699C,
445a5223ffSManivannan Sadhasivam .user_ctl_val = 0x1,
455a5223ffSManivannan Sadhasivam .user_ctl_hi_val = 0x805,
465a5223ffSManivannan Sadhasivam };
475a5223ffSManivannan Sadhasivam
485a5223ffSManivannan Sadhasivam static const struct regmap_config a7pll_regmap_config = {
495a5223ffSManivannan Sadhasivam .reg_bits = 32,
505a5223ffSManivannan Sadhasivam .reg_stride = 4,
515a5223ffSManivannan Sadhasivam .val_bits = 32,
525a5223ffSManivannan Sadhasivam .max_register = 0x1000,
535a5223ffSManivannan Sadhasivam .fast_io = true,
545a5223ffSManivannan Sadhasivam };
555a5223ffSManivannan Sadhasivam
qcom_a7pll_probe(struct platform_device * pdev)565a5223ffSManivannan Sadhasivam static int qcom_a7pll_probe(struct platform_device *pdev)
575a5223ffSManivannan Sadhasivam {
585a5223ffSManivannan Sadhasivam struct device *dev = &pdev->dev;
595a5223ffSManivannan Sadhasivam struct regmap *regmap;
605a5223ffSManivannan Sadhasivam void __iomem *base;
615a5223ffSManivannan Sadhasivam u32 l_val;
625a5223ffSManivannan Sadhasivam int ret;
635a5223ffSManivannan Sadhasivam
645a5223ffSManivannan Sadhasivam base = devm_platform_ioremap_resource(pdev, 0);
655a5223ffSManivannan Sadhasivam if (IS_ERR(base))
665a5223ffSManivannan Sadhasivam return PTR_ERR(base);
675a5223ffSManivannan Sadhasivam
685a5223ffSManivannan Sadhasivam regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config);
695a5223ffSManivannan Sadhasivam if (IS_ERR(regmap))
705a5223ffSManivannan Sadhasivam return PTR_ERR(regmap);
715a5223ffSManivannan Sadhasivam
725a5223ffSManivannan Sadhasivam /* Configure PLL only if the l_val is zero */
735a5223ffSManivannan Sadhasivam regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val);
745a5223ffSManivannan Sadhasivam if (!l_val)
755a5223ffSManivannan Sadhasivam clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config);
765a5223ffSManivannan Sadhasivam
775a5223ffSManivannan Sadhasivam ret = devm_clk_register_regmap(dev, &a7pll.clkr);
785a5223ffSManivannan Sadhasivam if (ret)
795a5223ffSManivannan Sadhasivam return ret;
805a5223ffSManivannan Sadhasivam
815a5223ffSManivannan Sadhasivam return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
825a5223ffSManivannan Sadhasivam &a7pll.clkr.hw);
835a5223ffSManivannan Sadhasivam }
845a5223ffSManivannan Sadhasivam
855a5223ffSManivannan Sadhasivam static const struct of_device_id qcom_a7pll_match_table[] = {
865a5223ffSManivannan Sadhasivam { .compatible = "qcom,sdx55-a7pll" },
875a5223ffSManivannan Sadhasivam { }
885a5223ffSManivannan Sadhasivam };
89*77a618b1SChen Hui MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
905a5223ffSManivannan Sadhasivam
915a5223ffSManivannan Sadhasivam static struct platform_driver qcom_a7pll_driver = {
925a5223ffSManivannan Sadhasivam .probe = qcom_a7pll_probe,
935a5223ffSManivannan Sadhasivam .driver = {
945a5223ffSManivannan Sadhasivam .name = "qcom-a7pll",
955a5223ffSManivannan Sadhasivam .of_match_table = qcom_a7pll_match_table,
965a5223ffSManivannan Sadhasivam },
975a5223ffSManivannan Sadhasivam };
985a5223ffSManivannan Sadhasivam module_platform_driver(qcom_a7pll_driver);
995a5223ffSManivannan Sadhasivam
1005a5223ffSManivannan Sadhasivam MODULE_DESCRIPTION("Qualcomm A7 PLL Driver");
1015a5223ffSManivannan Sadhasivam MODULE_LICENSE("GPL v2");
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