1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Marvell PXA3xxx family clocks 4 * 5 * Copyright (C) 2014 Robert Jarzmik 6 * 7 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c 8 * 9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this 10 * should go away. 11 */ 12 #include <linux/io.h> 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clkdev.h> 16 #include <linux/of.h> 17 #include <linux/soc/pxa/cpu.h> 18 #include <mach/smemc.h> 19 #include <mach/pxa3xx-regs.h> 20 21 #include <dt-bindings/clock/pxa-clock.h> 22 #include "clk-pxa.h" 23 24 #define KHz 1000 25 #define MHz (1000 * 1000) 26 27 enum { 28 PXA_CORE_60Mhz = 0, 29 PXA_CORE_RUN, 30 PXA_CORE_TURBO, 31 }; 32 33 enum { 34 PXA_BUS_60Mhz = 0, 35 PXA_BUS_HSS, 36 }; 37 38 /* crystal frequency to HSIO bus frequency multiplier (HSS) */ 39 static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; 40 41 /* crystal frequency to static memory controller multiplier (SMCFS) */ 42 static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 43 static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 }; 44 45 static const char * const get_freq_khz[] = { 46 "core", "ring_osc_60mhz", "run", "cpll", "system_bus" 47 }; 48 49 /* 50 * Get the clock frequency as reflected by ACSR and the turbo flag. 51 * We assume these values have been applied via a fcs. 52 * If info is not 0 we also display the current settings. 53 */ 54 unsigned int pxa3xx_get_clk_frequency_khz(int info) 55 { 56 struct clk *clk; 57 unsigned long clks[5]; 58 int i; 59 60 for (i = 0; i < 5; i++) { 61 clk = clk_get(NULL, get_freq_khz[i]); 62 if (IS_ERR(clk)) { 63 clks[i] = 0; 64 } else { 65 clks[i] = clk_get_rate(clk); 66 clk_put(clk); 67 } 68 } 69 if (info) { 70 pr_info("RO Mode clock: %ld.%02ldMHz\n", 71 clks[1] / 1000000, (clks[0] % 1000000) / 10000); 72 pr_info("Run Mode clock: %ld.%02ldMHz\n", 73 clks[2] / 1000000, (clks[1] % 1000000) / 10000); 74 pr_info("Turbo Mode clock: %ld.%02ldMHz\n", 75 clks[3] / 1000000, (clks[2] % 1000000) / 10000); 76 pr_info("System bus clock: %ld.%02ldMHz\n", 77 clks[4] / 1000000, (clks[4] % 1000000) / 10000); 78 } 79 return (unsigned int)clks[0] / KHz; 80 } 81 82 static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw, 83 unsigned long parent_rate) 84 { 85 unsigned long ac97_div, rate; 86 87 ac97_div = AC97_DIV; 88 89 /* This may loose precision for some rates but won't for the 90 * standard 24.576MHz. 91 */ 92 rate = parent_rate / 2; 93 rate /= ((ac97_div >> 12) & 0x7fff); 94 rate *= (ac97_div & 0xfff); 95 96 return rate; 97 } 98 PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" }; 99 RATE_RO_OPS(clk_pxa3xx_ac97, "ac97"); 100 101 static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw, 102 unsigned long parent_rate) 103 { 104 unsigned long acsr = ACSR; 105 unsigned long memclkcfg = __raw_readl(MEMCLKCFG); 106 107 return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] / 108 df_clkdiv[(memclkcfg >> 16) & 0x3]; 109 } 110 PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" }; 111 RATE_RO_OPS(clk_pxa3xx_smemc, "smemc"); 112 113 static bool pxa3xx_is_ring_osc_forced(void) 114 { 115 unsigned long acsr = ACSR; 116 117 return acsr & ACCR_D0CS; 118 } 119 120 PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" }; 121 PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" }; 122 PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" }; 123 PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" }; 124 PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" }; 125 PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" }; 126 127 #define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA) 128 #define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \ 129 div_hp, bit, is_lp, flags) \ 130 PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \ 131 mult_hp, div_hp, is_lp, CKEN_AB(bit), \ 132 (CKEN_ ## bit % 32), flags) 133 #define PXA3XX_PBUS_CKEN(dev_id, con_id, bit, mult_lp, div_lp, \ 134 mult_hp, div_hp, delay) \ 135 PXA3XX_CKEN(dev_id, con_id, pxa3xx_pbus_parents, mult_lp, \ 136 div_lp, mult_hp, div_hp, bit, pxa3xx_is_ring_osc_forced, 0) 137 #define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents) \ 138 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 139 CKEN_AB(bit), (CKEN_ ## bit % 32), 0) 140 141 static struct desc_clk_cken pxa3xx_clocks[] __initdata = { 142 PXA3XX_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 4, 1, 42, 1), 143 PXA3XX_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 4, 1, 42, 1), 144 PXA3XX_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 4, 1, 42, 1), 145 PXA3XX_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 5, 1, 19, 0), 146 PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5), 147 PXA3XX_PBUS_CKEN("pxa27x-ohci", NULL, USBH, 1, 4, 1, 13, 0), 148 PXA3XX_PBUS_CKEN("pxa3xx-u2d", NULL, USB2, 1, 4, 1, 13, 0), 149 PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0), 150 PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0), 151 PXA3XX_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC1, 1, 4, 1, 24, 0), 152 PXA3XX_PBUS_CKEN("pxa2xx-mci.1", NULL, MMC2, 1, 4, 1, 24, 0), 153 PXA3XX_PBUS_CKEN("pxa2xx-mci.2", NULL, MMC3, 1, 4, 1, 24, 0), 154 155 PXA3XX_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD, 156 pxa3xx_32Khz_bus_parents), 157 PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents), 158 PXA3XX_CKEN_1RATE("pxa3xx-ssp.1", NULL, SSP2, pxa3xx_13MHz_bus_parents), 159 PXA3XX_CKEN_1RATE("pxa3xx-ssp.2", NULL, SSP3, pxa3xx_13MHz_bus_parents), 160 PXA3XX_CKEN_1RATE("pxa3xx-ssp.3", NULL, SSP4, pxa3xx_13MHz_bus_parents), 161 162 PXA3XX_CKEN(NULL, "AC97CLK", pxa3xx_ac97_bus_parents, 1, 4, 1, 1, AC97, 163 pxa3xx_is_ring_osc_forced, 0), 164 PXA3XX_CKEN(NULL, "CAMCLK", pxa3xx_sbus_parents, 1, 2, 1, 1, CAMERA, 165 pxa3xx_is_ring_osc_forced, 0), 166 PXA3XX_CKEN("pxa2xx-fb", NULL, pxa3xx_sbus_parents, 1, 1, 1, 1, LCD, 167 pxa3xx_is_ring_osc_forced, 0), 168 PXA3XX_CKEN("pxa2xx-pcmcia", NULL, pxa3xx_smemcbus_parents, 1, 4, 169 1, 1, SMC, pxa3xx_is_ring_osc_forced, CLK_IGNORE_UNUSED), 170 }; 171 172 static struct desc_clk_cken pxa300_310_clocks[] __initdata = { 173 174 PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0), 175 PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0), 176 PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents), 177 }; 178 179 static struct desc_clk_cken pxa320_clocks[] __initdata = { 180 PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 6, 0), 181 PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA320_GCU, 1, 1, 1, 1, 0), 182 PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents), 183 }; 184 185 static struct desc_clk_cken pxa93x_clocks[] __initdata = { 186 187 PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0), 188 PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0), 189 PXA3XX_CKEN_1RATE("pxa93x-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents), 190 }; 191 192 static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw, 193 unsigned long parent_rate) 194 { 195 unsigned long acsr = ACSR; 196 unsigned int hss = (acsr >> 14) & 0x3; 197 198 if (pxa3xx_is_ring_osc_forced()) 199 return parent_rate; 200 return parent_rate / 48 * hss_mult[hss]; 201 } 202 203 static u8 clk_pxa3xx_system_bus_get_parent(struct clk_hw *hw) 204 { 205 if (pxa3xx_is_ring_osc_forced()) 206 return PXA_BUS_60Mhz; 207 else 208 return PXA_BUS_HSS; 209 } 210 211 PARENTS(clk_pxa3xx_system_bus) = { "ring_osc_60mhz", "spll_624mhz" }; 212 MUX_RO_RATE_RO_OPS(clk_pxa3xx_system_bus, "system_bus"); 213 214 static unsigned long clk_pxa3xx_core_get_rate(struct clk_hw *hw, 215 unsigned long parent_rate) 216 { 217 return parent_rate; 218 } 219 220 static u8 clk_pxa3xx_core_get_parent(struct clk_hw *hw) 221 { 222 unsigned long xclkcfg; 223 unsigned int t; 224 225 if (pxa3xx_is_ring_osc_forced()) 226 return PXA_CORE_60Mhz; 227 228 /* Read XCLKCFG register turbo bit */ 229 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 230 t = xclkcfg & 0x1; 231 232 if (t) 233 return PXA_CORE_TURBO; 234 return PXA_CORE_RUN; 235 } 236 PARENTS(clk_pxa3xx_core) = { "ring_osc_60mhz", "run", "cpll" }; 237 MUX_RO_RATE_RO_OPS(clk_pxa3xx_core, "core"); 238 239 static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw, 240 unsigned long parent_rate) 241 { 242 unsigned long acsr = ACSR; 243 unsigned int xn = (acsr & ACCR_XN_MASK) >> 8; 244 unsigned int t, xclkcfg; 245 246 /* Read XCLKCFG register turbo bit */ 247 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 248 t = xclkcfg & 0x1; 249 250 return t ? (parent_rate / xn) * 2 : parent_rate; 251 } 252 PARENTS(clk_pxa3xx_run) = { "cpll" }; 253 RATE_RO_OPS(clk_pxa3xx_run, "run"); 254 255 static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw, 256 unsigned long parent_rate) 257 { 258 unsigned long acsr = ACSR; 259 unsigned int xn = (acsr & ACCR_XN_MASK) >> 8; 260 unsigned int xl = acsr & ACCR_XL_MASK; 261 unsigned int t, xclkcfg; 262 263 /* Read XCLKCFG register turbo bit */ 264 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 265 t = xclkcfg & 0x1; 266 267 pr_info("RJK: parent_rate=%lu, xl=%u, xn=%u\n", parent_rate, xl, xn); 268 return t ? parent_rate * xl * xn : parent_rate * xl; 269 } 270 PARENTS(clk_pxa3xx_cpll) = { "osc_13mhz" }; 271 RATE_RO_OPS(clk_pxa3xx_cpll, "cpll"); 272 273 static void __init pxa3xx_register_core(void) 274 { 275 clk_register_clk_pxa3xx_cpll(); 276 clk_register_clk_pxa3xx_run(); 277 278 clkdev_pxa_register(CLK_CORE, "core", NULL, 279 clk_register_clk_pxa3xx_core()); 280 } 281 282 static void __init pxa3xx_register_plls(void) 283 { 284 clk_register_fixed_rate(NULL, "osc_13mhz", NULL, 285 CLK_GET_RATE_NOCACHE, 286 13 * MHz); 287 clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL, 288 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, 289 CLK_GET_RATE_NOCACHE, 290 32768)); 291 clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL, 292 CLK_GET_RATE_NOCACHE, 293 120 * MHz); 294 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0); 295 clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1); 296 clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz", 297 0, 1, 2); 298 } 299 300 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ 301 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent } 302 struct dummy_clk { 303 const char *con_id; 304 const char *dev_id; 305 const char *parent; 306 }; 307 static struct dummy_clk dummy_clks[] __initdata = { 308 DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"), 309 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"), 310 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"), 311 DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"), 312 }; 313 314 static void __init pxa3xx_dummy_clocks_init(void) 315 { 316 struct clk *clk; 317 struct dummy_clk *d; 318 const char *name; 319 int i; 320 321 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) { 322 d = &dummy_clks[i]; 323 name = d->dev_id ? d->dev_id : d->con_id; 324 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1); 325 clk_register_clkdev(clk, d->con_id, d->dev_id); 326 } 327 } 328 329 static void __init pxa3xx_base_clocks_init(void) 330 { 331 struct clk *clk; 332 333 pxa3xx_register_plls(); 334 pxa3xx_register_core(); 335 clk_register_clk_pxa3xx_system_bus(); 336 clk_register_clk_pxa3xx_ac97(); 337 clk_register_clk_pxa3xx_smemc(); 338 clk = clk_register_gate(NULL, "CLK_POUT", 339 "osc_13mhz", 0, OSCC, 11, 0, NULL); 340 clk_register_clkdev(clk, "CLK_POUT", NULL); 341 clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL, 342 clk_register_fixed_factor(NULL, "os-timer0", 343 "osc_13mhz", 0, 1, 4)); 344 } 345 346 int __init pxa3xx_clocks_init(void) 347 { 348 int ret; 349 350 pxa3xx_base_clocks_init(); 351 pxa3xx_dummy_clocks_init(); 352 ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks)); 353 if (ret) 354 return ret; 355 if (cpu_is_pxa320()) 356 return clk_pxa_cken_init(pxa320_clocks, 357 ARRAY_SIZE(pxa320_clocks)); 358 if (cpu_is_pxa300() || cpu_is_pxa310()) 359 return clk_pxa_cken_init(pxa300_310_clocks, 360 ARRAY_SIZE(pxa300_310_clocks)); 361 return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks)); 362 } 363 364 static void __init pxa3xx_dt_clocks_init(struct device_node *np) 365 { 366 pxa3xx_clocks_init(); 367 clk_pxa_dt_common_init(np); 368 } 369 CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init); 370