1 /* 2 * Marvell PXA27x family clocks 3 * 4 * Copyright (C) 2014 Robert Jarzmik 5 * 6 * Heavily inspired from former arch/arm/mach-pxa/clock.c. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 */ 13 #include <linux/clk-provider.h> 14 #include <mach/pxa2xx-regs.h> 15 #include <linux/io.h> 16 #include <linux/clk.h> 17 #include <linux/clkdev.h> 18 #include <linux/of.h> 19 20 #include <mach/smemc.h> 21 22 #include <dt-bindings/clock/pxa-clock.h> 23 #include "clk-pxa.h" 24 25 #define KHz 1000 26 #define MHz (1000 * 1000) 27 28 enum { 29 PXA_CORE_13Mhz = 0, 30 PXA_CORE_RUN, 31 PXA_CORE_TURBO, 32 }; 33 34 enum { 35 PXA_BUS_13Mhz = 0, 36 PXA_BUS_RUN, 37 }; 38 39 enum { 40 PXA_LCD_13Mhz = 0, 41 PXA_LCD_RUN, 42 }; 43 44 enum { 45 PXA_MEM_13Mhz = 0, 46 PXA_MEM_SYSTEM_BUS, 47 PXA_MEM_RUN, 48 }; 49 50 #define PXA27x_CLKCFG(B, HT, T) \ 51 (CLKCFG_FCS | \ 52 ((B) ? CLKCFG_FASTBUS : 0) | \ 53 ((HT) ? CLKCFG_HALFTURBO : 0) | \ 54 ((T) ? CLKCFG_TURBO : 0)) 55 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L) 56 57 #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3) 58 #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3) 59 60 /* Define the refresh period in mSec for the SDRAM and the number of rows */ 61 #define SDRAM_TREF 64 /* standard 64ms SDRAM */ 62 63 static const char * const get_freq_khz[] = { 64 "core", "run", "cpll", "memory", 65 "system_bus" 66 }; 67 68 static int get_sdram_rows(void) 69 { 70 static int sdram_rows; 71 unsigned int drac2 = 0, drac0 = 0; 72 u32 mdcnfg; 73 74 if (sdram_rows) 75 return sdram_rows; 76 77 mdcnfg = readl_relaxed(MDCNFG); 78 79 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) 80 drac2 = MDCNFG_DRAC2(mdcnfg); 81 82 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1)) 83 drac0 = MDCNFG_DRAC0(mdcnfg); 84 85 sdram_rows = 1 << (11 + max(drac0, drac2)); 86 return sdram_rows; 87 } 88 89 static u32 mdrefr_dri(unsigned int freq_khz) 90 { 91 u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows(); 92 93 return (interval - 31) / 32; 94 } 95 96 /* 97 * Get the clock frequency as reflected by CCSR and the turbo flag. 98 * We assume these values have been applied via a fcs. 99 * If info is not 0 we also display the current settings. 100 */ 101 unsigned int pxa27x_get_clk_frequency_khz(int info) 102 { 103 struct clk *clk; 104 unsigned long clks[5]; 105 int i; 106 107 for (i = 0; i < 5; i++) { 108 clk = clk_get(NULL, get_freq_khz[i]); 109 if (IS_ERR(clk)) { 110 clks[i] = 0; 111 } else { 112 clks[i] = clk_get_rate(clk); 113 clk_put(clk); 114 } 115 } 116 if (info) { 117 pr_info("Run Mode clock: %ld.%02ldMHz\n", 118 clks[1] / 1000000, (clks[1] % 1000000) / 10000); 119 pr_info("Turbo Mode clock: %ld.%02ldMHz\n", 120 clks[2] / 1000000, (clks[2] % 1000000) / 10000); 121 pr_info("Memory clock: %ld.%02ldMHz\n", 122 clks[3] / 1000000, (clks[3] % 1000000) / 10000); 123 pr_info("System bus clock: %ld.%02ldMHz\n", 124 clks[4] / 1000000, (clks[4] % 1000000) / 10000); 125 } 126 return (unsigned int)clks[0] / KHz; 127 } 128 129 bool pxa27x_is_ppll_disabled(void) 130 { 131 unsigned long ccsr = readl(CCSR); 132 133 return ccsr & (1 << CCCR_PPDIS_BIT); 134 } 135 136 #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \ 137 bit, is_lp, flags) \ 138 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \ 139 is_lp, CKEN, CKEN_ ## bit, flags) 140 #define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ 141 PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \ 142 div_hp, bit, pxa27x_is_ppll_disabled, 0) 143 144 PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" }; 145 PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" }; 146 PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" }; 147 PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" }; 148 PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" }; 149 150 #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ 151 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 152 CKEN, CKEN_ ## bit, 0) 153 #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ 154 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 155 CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED) 156 157 static struct desc_clk_cken pxa27x_clocks[] __initdata = { 158 PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1), 159 PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1), 160 PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1), 161 PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0), 162 PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0), 163 PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5), 164 PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0), 165 PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0), 166 PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0), 167 PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0), 168 PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0), 169 PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0), 170 PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0), 171 PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0), 172 PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0), 173 PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0), 174 PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0), 175 PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0), 176 PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0), 177 PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0), 178 PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0), 179 180 PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD, 181 pxa27x_32Mhz_bus_parents, 0), 182 PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0), 183 PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0), 184 PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA, 185 pxa27x_lcd_bus_parents, 0), 186 PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC, 187 pxa27x_membus_parents, 0), 188 189 }; 190 191 /* 192 * PXA270 definitions 193 * 194 * For the PXA27x: 195 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG. 196 * 197 * A = 0 => memory controller clock from table 3-7, 198 * A = 1 => memory controller clock = system bus clock 199 * Run mode frequency = 13 MHz * L 200 * Turbo mode frequency = 13 MHz * L * N 201 * System bus frequency = 13 MHz * L / (B + 1) 202 * 203 * In CCCR: 204 * A = 1 205 * L = 16 oscillator to run mode ratio 206 * 2N = 6 2 * (turbo mode to run mode ratio) 207 * 208 * In CCLKCFG: 209 * B = 1 Fast bus mode 210 * HT = 0 Half-Turbo mode 211 * T = 1 Turbo mode 212 * 213 * For now, just support some of the combinations in table 3-7 of 214 * PXA27x Processor Family Developer's Manual to simplify frequency 215 * change sequences. 216 */ 217 static struct pxa2xx_freq pxa27x_freqs[] = { 218 {104000000, 104000, PXA27x_CCCR(1, 8, 2), 0, PXA27x_CLKCFG(1, 0, 1) }, 219 {156000000, 104000, PXA27x_CCCR(1, 8, 3), 0, PXA27x_CLKCFG(1, 0, 1) }, 220 {208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) }, 221 {312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) }, 222 {416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) }, 223 {520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) }, 224 {624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) }, 225 }; 226 227 static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw, 228 unsigned long parent_rate) 229 { 230 unsigned long clkcfg; 231 unsigned int t, ht; 232 unsigned int l, L, n2, N; 233 unsigned long ccsr = readl(CCSR); 234 235 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 236 t = clkcfg & (1 << 0); 237 ht = clkcfg & (1 << 2); 238 239 l = ccsr & CCSR_L_MASK; 240 n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT; 241 L = l * parent_rate; 242 N = (L * n2) / 2; 243 244 return N; 245 } 246 247 static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw, 248 struct clk_rate_request *req) 249 { 250 return pxa2xx_determine_rate(req, pxa27x_freqs, 251 ARRAY_SIZE(pxa27x_freqs)); 252 } 253 254 static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate, 255 unsigned long parent_rate) 256 { 257 int i; 258 259 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate); 260 for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++) 261 if (pxa27x_freqs[i].cpll == rate) 262 break; 263 264 if (i >= ARRAY_SIZE(pxa27x_freqs)) 265 return -EINVAL; 266 267 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, MDREFR, CCCR); 268 return 0; 269 } 270 271 PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" }; 272 RATE_OPS(clk_pxa27x_cpll, "cpll"); 273 274 static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw, 275 unsigned long parent_rate) 276 { 277 unsigned int l, osc_forced; 278 unsigned long ccsr = readl(CCSR); 279 unsigned long cccr = readl(CCCR); 280 281 l = ccsr & CCSR_L_MASK; 282 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 283 if (osc_forced) { 284 if (cccr & (1 << CCCR_LCD_26_BIT)) 285 return parent_rate * 2; 286 else 287 return parent_rate; 288 } 289 290 if (l <= 7) 291 return parent_rate; 292 if (l <= 16) 293 return parent_rate / 2; 294 return parent_rate / 4; 295 } 296 297 static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw) 298 { 299 unsigned int osc_forced; 300 unsigned long ccsr = readl(CCSR); 301 302 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 303 if (osc_forced) 304 return PXA_LCD_13Mhz; 305 else 306 return PXA_LCD_RUN; 307 } 308 309 PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" }; 310 MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base"); 311 312 static void __init pxa27x_register_plls(void) 313 { 314 clk_register_fixed_rate(NULL, "osc_13mhz", NULL, 315 CLK_GET_RATE_NOCACHE, 316 13 * MHz); 317 clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL, 318 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, 319 CLK_GET_RATE_NOCACHE, 320 32768 * KHz)); 321 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0); 322 clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1); 323 } 324 325 static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw) 326 { 327 unsigned long clkcfg; 328 unsigned int t, ht, osc_forced; 329 unsigned long ccsr = readl(CCSR); 330 331 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 332 if (osc_forced) 333 return PXA_CORE_13Mhz; 334 335 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 336 t = clkcfg & (1 << 0); 337 ht = clkcfg & (1 << 2); 338 339 if (ht || t) 340 return PXA_CORE_TURBO; 341 return PXA_CORE_RUN; 342 } 343 344 static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index) 345 { 346 if (index > PXA_CORE_TURBO) 347 return -EINVAL; 348 349 pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO); 350 351 return 0; 352 } 353 354 static int clk_pxa27x_core_determine_rate(struct clk_hw *hw, 355 struct clk_rate_request *req) 356 { 357 return __clk_mux_determine_rate(hw, req); 358 } 359 360 PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" }; 361 MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT); 362 363 static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw, 364 unsigned long parent_rate) 365 { 366 unsigned long ccsr = readl(CCSR); 367 unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT; 368 369 return (parent_rate / n2) * 2; 370 } 371 PARENTS(clk_pxa27x_run) = { "cpll" }; 372 RATE_RO_OPS(clk_pxa27x_run, "run"); 373 374 static void __init pxa27x_register_core(void) 375 { 376 clkdev_pxa_register(CLK_NONE, "cpll", NULL, 377 clk_register_clk_pxa27x_cpll()); 378 clkdev_pxa_register(CLK_NONE, "run", NULL, 379 clk_register_clk_pxa27x_run()); 380 clkdev_pxa_register(CLK_CORE, "core", NULL, 381 clk_register_clk_pxa27x_core()); 382 } 383 384 static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw, 385 unsigned long parent_rate) 386 { 387 unsigned long clkcfg; 388 unsigned int b, osc_forced; 389 unsigned long ccsr = readl(CCSR); 390 391 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 392 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 393 b = clkcfg & (1 << 3); 394 395 if (osc_forced) 396 return parent_rate; 397 if (b) 398 return parent_rate; 399 else 400 return parent_rate / 2; 401 } 402 403 static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw) 404 { 405 unsigned int osc_forced; 406 unsigned long ccsr = readl(CCSR); 407 408 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 409 if (osc_forced) 410 return PXA_BUS_13Mhz; 411 else 412 return PXA_BUS_RUN; 413 } 414 415 PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" }; 416 MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus"); 417 418 static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw, 419 unsigned long parent_rate) 420 { 421 unsigned int a, l, osc_forced; 422 unsigned long cccr = readl(CCCR); 423 unsigned long ccsr = readl(CCSR); 424 425 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 426 a = cccr & (1 << CCCR_A_BIT); 427 l = ccsr & CCSR_L_MASK; 428 429 if (osc_forced || a) 430 return parent_rate; 431 if (l <= 10) 432 return parent_rate; 433 if (l <= 20) 434 return parent_rate / 2; 435 return parent_rate / 4; 436 } 437 438 static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw) 439 { 440 unsigned int osc_forced, a; 441 unsigned long cccr = readl(CCCR); 442 unsigned long ccsr = readl(CCSR); 443 444 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 445 a = cccr & (1 << CCCR_A_BIT); 446 if (osc_forced) 447 return PXA_MEM_13Mhz; 448 if (a) 449 return PXA_MEM_SYSTEM_BUS; 450 else 451 return PXA_MEM_RUN; 452 } 453 454 PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" }; 455 MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory"); 456 457 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ 458 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent } 459 struct dummy_clk { 460 const char *con_id; 461 const char *dev_id; 462 const char *parent; 463 }; 464 static struct dummy_clk dummy_clks[] __initdata = { 465 DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"), 466 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"), 467 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"), 468 }; 469 470 static void __init pxa27x_dummy_clocks_init(void) 471 { 472 struct clk *clk; 473 struct dummy_clk *d; 474 const char *name; 475 int i; 476 477 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) { 478 d = &dummy_clks[i]; 479 name = d->dev_id ? d->dev_id : d->con_id; 480 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1); 481 clk_register_clkdev(clk, d->con_id, d->dev_id); 482 } 483 } 484 485 static void __init pxa27x_base_clocks_init(void) 486 { 487 pxa27x_register_plls(); 488 pxa27x_register_core(); 489 clkdev_pxa_register(CLK_NONE, "system_bus", NULL, 490 clk_register_clk_pxa27x_system_bus()); 491 clkdev_pxa_register(CLK_NONE, "memory", NULL, 492 clk_register_clk_pxa27x_memory()); 493 clk_register_clk_pxa27x_lcd_base(); 494 } 495 496 int __init pxa27x_clocks_init(void) 497 { 498 pxa27x_base_clocks_init(); 499 pxa27x_dummy_clocks_init(); 500 return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks)); 501 } 502 503 static void __init pxa27x_dt_clocks_init(struct device_node *np) 504 { 505 pxa27x_clocks_init(); 506 clk_pxa_dt_common_init(np); 507 } 508 CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init); 509