1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Marvell PXA25x family clocks 4 * 5 * Copyright (C) 2014 Robert Jarzmik 6 * 7 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c. 8 * 9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this 10 * should go away. 11 */ 12 #include <linux/clk-provider.h> 13 #include <linux/clk.h> 14 #include <linux/clkdev.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <mach/pxa2xx-regs.h> 18 #include <mach/smemc.h> 19 20 #include <dt-bindings/clock/pxa-clock.h> 21 #include "clk-pxa.h" 22 23 #define KHz 1000 24 #define MHz (1000 * 1000) 25 26 enum { 27 PXA_CORE_RUN = 0, 28 PXA_CORE_TURBO, 29 }; 30 31 #define PXA25x_CLKCFG(T) \ 32 (CLKCFG_FCS | \ 33 ((T) ? CLKCFG_TURBO : 0)) 34 #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L) 35 36 #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3) 37 #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3) 38 39 /* Define the refresh period in mSec for the SDRAM and the number of rows */ 40 #define SDRAM_TREF 64 /* standard 64ms SDRAM */ 41 42 /* 43 * Various clock factors driven by the CCCR register. 44 */ 45 46 /* Crystal Frequency to Memory Frequency Multiplier (L) */ 47 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; 48 49 /* Memory Frequency to Run Mode Frequency Multiplier (M) */ 50 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; 51 52 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ 53 /* Note: we store the value N * 2 here. */ 54 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; 55 56 static const char * const get_freq_khz[] = { 57 "core", "run", "cpll", "memory" 58 }; 59 60 static int get_sdram_rows(void) 61 { 62 static int sdram_rows; 63 unsigned int drac2 = 0, drac0 = 0; 64 u32 mdcnfg; 65 66 if (sdram_rows) 67 return sdram_rows; 68 69 mdcnfg = readl_relaxed(MDCNFG); 70 71 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) 72 drac2 = MDCNFG_DRAC2(mdcnfg); 73 74 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1)) 75 drac0 = MDCNFG_DRAC0(mdcnfg); 76 77 sdram_rows = 1 << (11 + max(drac0, drac2)); 78 return sdram_rows; 79 } 80 81 static u32 mdrefr_dri(unsigned int freq_khz) 82 { 83 u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows(); 84 85 return interval / 32; 86 } 87 88 /* 89 * Get the clock frequency as reflected by CCCR and the turbo flag. 90 * We assume these values have been applied via a fcs. 91 * If info is not 0 we also display the current settings. 92 */ 93 unsigned int pxa25x_get_clk_frequency_khz(int info) 94 { 95 struct clk *clk; 96 unsigned long clks[5]; 97 int i; 98 99 for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) { 100 clk = clk_get(NULL, get_freq_khz[i]); 101 if (IS_ERR(clk)) { 102 clks[i] = 0; 103 } else { 104 clks[i] = clk_get_rate(clk); 105 clk_put(clk); 106 } 107 } 108 109 if (info) { 110 pr_info("Run Mode clock: %ld.%02ldMHz\n", 111 clks[1] / 1000000, (clks[1] % 1000000) / 10000); 112 pr_info("Turbo Mode clock: %ld.%02ldMHz\n", 113 clks[2] / 1000000, (clks[2] % 1000000) / 10000); 114 pr_info("Memory clock: %ld.%02ldMHz\n", 115 clks[3] / 1000000, (clks[3] % 1000000) / 10000); 116 } 117 118 return (unsigned int)clks[0] / KHz; 119 } 120 121 static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw, 122 unsigned long parent_rate) 123 { 124 unsigned long cccr = readl(CCCR); 125 unsigned int m = M_clk_mult[(cccr >> 5) & 0x03]; 126 127 return parent_rate / m; 128 } 129 PARENTS(clk_pxa25x_memory) = { "run" }; 130 RATE_RO_OPS(clk_pxa25x_memory, "memory"); 131 132 PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" }; 133 PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" }; 134 PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" }; 135 136 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \ 137 bit, is_lp, flags) \ 138 PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \ 139 is_lp, CKEN, CKEN_ ## bit, flags) 140 #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ 141 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \ 142 div_hp, bit, NULL, 0) 143 #define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\ 144 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \ 145 div_hp, bit, NULL, 0) 146 #define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ 147 PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \ 148 div_hp, bit, NULL, 0) 149 150 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ 151 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 152 CKEN, CKEN_ ## bit, 0) 153 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ 154 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 155 CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED) 156 157 static struct desc_clk_cken pxa25x_clocks[] __initdata = { 158 PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0), 159 PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0), 160 PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0), 161 PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5), 162 PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1), 163 PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1), 164 PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1), 165 PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1), 166 PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0), 167 PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0), 168 PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0), 169 PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0), 170 PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0), 171 PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0), 172 PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0), 173 174 PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0), 175 PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC, 176 clk_pxa25x_memory_parents, 0), 177 }; 178 179 /* 180 * In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where : 181 * - freq_cpll = n * m * L * 3.6864 MHz 182 * - n = N2 / 2 183 * - m = 2^(M - 1), where 1 <= M <= 3 184 * - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L] 185 */ 186 static struct pxa2xx_freq pxa25x_freqs[] = { 187 /* CPU MEMBUS CCCR DIV2 CCLKCFG */ 188 { 99532800, 99500, PXA25x_CCCR(2, 1, 1), 1, PXA25x_CLKCFG(1)}, 189 {199065600, 99500, PXA25x_CCCR(4, 1, 1), 0, PXA25x_CLKCFG(1)}, 190 {298598400, 99500, PXA25x_CCCR(3, 2, 1), 0, PXA25x_CLKCFG(1)}, 191 {398131200, 99500, PXA25x_CCCR(4, 2, 1), 0, PXA25x_CLKCFG(1)}, 192 }; 193 194 static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw) 195 { 196 unsigned long clkcfg; 197 unsigned int t; 198 199 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 200 t = clkcfg & (1 << 0); 201 if (t) 202 return PXA_CORE_TURBO; 203 return PXA_CORE_RUN; 204 } 205 206 static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index) 207 { 208 if (index > PXA_CORE_TURBO) 209 return -EINVAL; 210 211 pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO); 212 213 return 0; 214 } 215 216 static int clk_pxa25x_core_determine_rate(struct clk_hw *hw, 217 struct clk_rate_request *req) 218 { 219 return __clk_mux_determine_rate(hw, req); 220 } 221 222 PARENTS(clk_pxa25x_core) = { "run", "cpll" }; 223 MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT); 224 225 static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw, 226 unsigned long parent_rate) 227 { 228 unsigned long cccr = readl(CCCR); 229 unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 230 231 return (parent_rate / n2) * 2; 232 } 233 PARENTS(clk_pxa25x_run) = { "cpll" }; 234 RATE_RO_OPS(clk_pxa25x_run, "run"); 235 236 static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw, 237 unsigned long parent_rate) 238 { 239 unsigned long clkcfg, cccr = readl(CCCR); 240 unsigned int l, m, n2, t; 241 242 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 243 t = clkcfg & (1 << 0); 244 l = L_clk_mult[(cccr >> 0) & 0x1f]; 245 m = M_clk_mult[(cccr >> 5) & 0x03]; 246 n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 247 248 return m * l * n2 * parent_rate / 2; 249 } 250 251 static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw, 252 struct clk_rate_request *req) 253 { 254 return pxa2xx_determine_rate(req, pxa25x_freqs, 255 ARRAY_SIZE(pxa25x_freqs)); 256 } 257 258 static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate, 259 unsigned long parent_rate) 260 { 261 int i; 262 263 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate); 264 for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++) 265 if (pxa25x_freqs[i].cpll == rate) 266 break; 267 268 if (i >= ARRAY_SIZE(pxa25x_freqs)) 269 return -EINVAL; 270 271 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, MDREFR, CCCR); 272 273 return 0; 274 } 275 PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" }; 276 RATE_OPS(clk_pxa25x_cpll, "cpll"); 277 278 static void __init pxa25x_register_core(void) 279 { 280 clkdev_pxa_register(CLK_NONE, "cpll", NULL, 281 clk_register_clk_pxa25x_cpll()); 282 clkdev_pxa_register(CLK_NONE, "run", NULL, 283 clk_register_clk_pxa25x_run()); 284 clkdev_pxa_register(CLK_CORE, "core", NULL, 285 clk_register_clk_pxa25x_core()); 286 } 287 288 static void __init pxa25x_register_plls(void) 289 { 290 clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL, 291 CLK_GET_RATE_NOCACHE, 3686400); 292 clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL, 293 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, 294 CLK_GET_RATE_NOCACHE, 295 32768)); 296 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0); 297 clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz", 298 0, 26, 1); 299 clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz", 300 0, 40, 1); 301 } 302 303 static void __init pxa25x_base_clocks_init(void) 304 { 305 pxa25x_register_plls(); 306 pxa25x_register_core(); 307 clkdev_pxa_register(CLK_NONE, "system_bus", NULL, 308 clk_register_clk_pxa25x_memory()); 309 } 310 311 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ 312 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent } 313 struct dummy_clk { 314 const char *con_id; 315 const char *dev_id; 316 const char *parent; 317 }; 318 static struct dummy_clk dummy_clks[] __initdata = { 319 DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"), 320 DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"), 321 DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"), 322 DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"), 323 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"), 324 DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"), 325 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"), 326 }; 327 328 static void __init pxa25x_dummy_clocks_init(void) 329 { 330 struct clk *clk; 331 struct dummy_clk *d; 332 const char *name; 333 int i; 334 335 /* 336 * All pinctrl logic has been wiped out of the clock driver, especially 337 * for gpio11 and gpio12 outputs. Machine code should ensure proper pin 338 * control (ie. pxa2xx_mfp_config() invocation). 339 */ 340 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) { 341 d = &dummy_clks[i]; 342 name = d->dev_id ? d->dev_id : d->con_id; 343 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1); 344 clk_register_clkdev(clk, d->con_id, d->dev_id); 345 } 346 } 347 348 int __init pxa25x_clocks_init(void) 349 { 350 pxa25x_base_clocks_init(); 351 pxa25x_dummy_clocks_init(); 352 return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks)); 353 } 354 355 static void __init pxa25x_dt_clocks_init(struct device_node *np) 356 { 357 pxa25x_clocks_init(); 358 clk_pxa_dt_common_init(np); 359 } 360 CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks", 361 pxa25x_dt_clocks_init); 362