1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Marvell PXA25x family clocks 4 * 5 * Copyright (C) 2014 Robert Jarzmik 6 * 7 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c. 8 * 9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this 10 * should go away. 11 */ 12 #include <linux/clk-provider.h> 13 #include <linux/clk.h> 14 #include <linux/clkdev.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/soc/pxa/smemc.h> 18 19 #include <dt-bindings/clock/pxa-clock.h> 20 #include "clk-pxa.h" 21 #include "clk-pxa2xx.h" 22 23 #define KHz 1000 24 #define MHz (1000 * 1000) 25 26 enum { 27 PXA_CORE_RUN = 0, 28 PXA_CORE_TURBO, 29 }; 30 31 #define PXA25x_CLKCFG(T) \ 32 (CLKCFG_FCS | \ 33 ((T) ? CLKCFG_TURBO : 0)) 34 #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L) 35 36 /* Define the refresh period in mSec for the SDRAM and the number of rows */ 37 #define SDRAM_TREF 64 /* standard 64ms SDRAM */ 38 39 /* 40 * Various clock factors driven by the CCCR register. 41 */ 42 static void __iomem *clk_regs; 43 44 /* Crystal Frequency to Memory Frequency Multiplier (L) */ 45 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; 46 47 /* Memory Frequency to Run Mode Frequency Multiplier (M) */ 48 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; 49 50 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ 51 /* Note: we store the value N * 2 here. */ 52 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; 53 54 static const char * const get_freq_khz[] = { 55 "core", "run", "cpll", "memory" 56 }; 57 58 static u32 mdrefr_dri(unsigned int freq_khz) 59 { 60 u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows(); 61 62 return interval / 32; 63 } 64 65 /* 66 * Get the clock frequency as reflected by CCCR and the turbo flag. 67 * We assume these values have been applied via a fcs. 68 * If info is not 0 we also display the current settings. 69 */ 70 unsigned int pxa25x_get_clk_frequency_khz(int info) 71 { 72 struct clk *clk; 73 unsigned long clks[5]; 74 int i; 75 76 for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) { 77 clk = clk_get(NULL, get_freq_khz[i]); 78 if (IS_ERR(clk)) { 79 clks[i] = 0; 80 } else { 81 clks[i] = clk_get_rate(clk); 82 clk_put(clk); 83 } 84 } 85 86 if (info) { 87 pr_info("Run Mode clock: %ld.%02ldMHz\n", 88 clks[1] / 1000000, (clks[1] % 1000000) / 10000); 89 pr_info("Turbo Mode clock: %ld.%02ldMHz\n", 90 clks[2] / 1000000, (clks[2] % 1000000) / 10000); 91 pr_info("Memory clock: %ld.%02ldMHz\n", 92 clks[3] / 1000000, (clks[3] % 1000000) / 10000); 93 } 94 95 return (unsigned int)clks[0] / KHz; 96 } 97 98 static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw, 99 unsigned long parent_rate) 100 { 101 unsigned long cccr = readl(clk_regs + CCCR); 102 unsigned int m = M_clk_mult[(cccr >> 5) & 0x03]; 103 104 return parent_rate / m; 105 } 106 PARENTS(clk_pxa25x_memory) = { "run" }; 107 RATE_RO_OPS(clk_pxa25x_memory, "memory"); 108 109 PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" }; 110 PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" }; 111 PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" }; 112 113 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \ 114 bit, is_lp, flags) \ 115 PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \ 116 is_lp, CKEN, CKEN_ ## bit, flags) 117 #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ 118 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \ 119 div_hp, bit, NULL, 0) 120 #define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\ 121 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \ 122 div_hp, bit, NULL, 0) 123 #define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ 124 PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \ 125 div_hp, bit, NULL, 0) 126 127 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ 128 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 129 CKEN, CKEN_ ## bit, 0) 130 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ 131 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 132 CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED) 133 134 static struct desc_clk_cken pxa25x_clocks[] __initdata = { 135 PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0), 136 PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0), 137 PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0), 138 PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5), 139 PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1), 140 PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1), 141 PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1), 142 PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1), 143 PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0), 144 PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0), 145 PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0), 146 PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0), 147 PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0), 148 PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0), 149 PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0), 150 151 PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0), 152 PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC, 153 clk_pxa25x_memory_parents, 0), 154 }; 155 156 /* 157 * In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where : 158 * - freq_cpll = n * m * L * 3.6864 MHz 159 * - n = N2 / 2 160 * - m = 2^(M - 1), where 1 <= M <= 3 161 * - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L] 162 */ 163 static struct pxa2xx_freq pxa25x_freqs[] = { 164 /* CPU MEMBUS CCCR DIV2 CCLKCFG */ 165 { 99532800, 99500, PXA25x_CCCR(2, 1, 1), 1, PXA25x_CLKCFG(1)}, 166 {199065600, 99500, PXA25x_CCCR(4, 1, 1), 0, PXA25x_CLKCFG(1)}, 167 {298598400, 99500, PXA25x_CCCR(3, 2, 1), 0, PXA25x_CLKCFG(1)}, 168 {398131200, 99500, PXA25x_CCCR(4, 2, 1), 0, PXA25x_CLKCFG(1)}, 169 }; 170 171 static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw) 172 { 173 unsigned long clkcfg; 174 unsigned int t; 175 176 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 177 t = clkcfg & (1 << 0); 178 if (t) 179 return PXA_CORE_TURBO; 180 return PXA_CORE_RUN; 181 } 182 183 static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index) 184 { 185 if (index > PXA_CORE_TURBO) 186 return -EINVAL; 187 188 pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO); 189 190 return 0; 191 } 192 193 static int clk_pxa25x_core_determine_rate(struct clk_hw *hw, 194 struct clk_rate_request *req) 195 { 196 return __clk_mux_determine_rate(hw, req); 197 } 198 199 PARENTS(clk_pxa25x_core) = { "run", "cpll" }; 200 MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT); 201 202 static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw, 203 unsigned long parent_rate) 204 { 205 unsigned long cccr = readl(clk_regs + CCCR); 206 unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 207 208 return (parent_rate / n2) * 2; 209 } 210 PARENTS(clk_pxa25x_run) = { "cpll" }; 211 RATE_RO_OPS(clk_pxa25x_run, "run"); 212 213 static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw, 214 unsigned long parent_rate) 215 { 216 unsigned long clkcfg, cccr = readl(clk_regs + CCCR); 217 unsigned int l, m, n2, t; 218 219 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 220 t = clkcfg & (1 << 0); 221 l = L_clk_mult[(cccr >> 0) & 0x1f]; 222 m = M_clk_mult[(cccr >> 5) & 0x03]; 223 n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 224 225 return m * l * n2 * parent_rate / 2; 226 } 227 228 static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw, 229 struct clk_rate_request *req) 230 { 231 return pxa2xx_determine_rate(req, pxa25x_freqs, 232 ARRAY_SIZE(pxa25x_freqs)); 233 } 234 235 static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate, 236 unsigned long parent_rate) 237 { 238 int i; 239 240 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate); 241 for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++) 242 if (pxa25x_freqs[i].cpll == rate) 243 break; 244 245 if (i >= ARRAY_SIZE(pxa25x_freqs)) 246 return -EINVAL; 247 248 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR); 249 250 return 0; 251 } 252 PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" }; 253 RATE_OPS(clk_pxa25x_cpll, "cpll"); 254 255 static void __init pxa25x_register_core(void) 256 { 257 clkdev_pxa_register(CLK_NONE, "cpll", NULL, 258 clk_register_clk_pxa25x_cpll()); 259 clkdev_pxa_register(CLK_NONE, "run", NULL, 260 clk_register_clk_pxa25x_run()); 261 clkdev_pxa_register(CLK_CORE, "core", NULL, 262 clk_register_clk_pxa25x_core()); 263 } 264 265 static void __init pxa25x_register_plls(void) 266 { 267 clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL, 268 CLK_GET_RATE_NOCACHE, 3686400); 269 clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL, 270 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, 271 CLK_GET_RATE_NOCACHE, 272 32768)); 273 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0); 274 clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz", 275 0, 26, 1); 276 clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz", 277 0, 40, 1); 278 } 279 280 static void __init pxa25x_base_clocks_init(void) 281 { 282 pxa25x_register_plls(); 283 pxa25x_register_core(); 284 clkdev_pxa_register(CLK_NONE, "system_bus", NULL, 285 clk_register_clk_pxa25x_memory()); 286 } 287 288 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ 289 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent } 290 struct dummy_clk { 291 const char *con_id; 292 const char *dev_id; 293 const char *parent; 294 }; 295 static struct dummy_clk dummy_clks[] __initdata = { 296 DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"), 297 DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"), 298 DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"), 299 DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"), 300 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"), 301 DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"), 302 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"), 303 }; 304 305 static void __init pxa25x_dummy_clocks_init(void) 306 { 307 struct clk *clk; 308 struct dummy_clk *d; 309 const char *name; 310 int i; 311 312 /* 313 * All pinctrl logic has been wiped out of the clock driver, especially 314 * for gpio11 and gpio12 outputs. Machine code should ensure proper pin 315 * control (ie. pxa2xx_mfp_config() invocation). 316 */ 317 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) { 318 d = &dummy_clks[i]; 319 name = d->dev_id ? d->dev_id : d->con_id; 320 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1); 321 clk_register_clkdev(clk, d->con_id, d->dev_id); 322 } 323 } 324 325 int __init pxa25x_clocks_init(void __iomem *regs) 326 { 327 clk_regs = regs; 328 pxa25x_base_clocks_init(); 329 pxa25x_dummy_clocks_init(); 330 return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks), clk_regs); 331 } 332 333 static void __init pxa25x_dt_clocks_init(struct device_node *np) 334 { 335 pxa25x_clocks_init(ioremap(0x41300000ul, 0x10)); 336 clk_pxa_dt_common_init(np); 337 } 338 CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks", 339 pxa25x_dt_clocks_init); 340