1 /* 2 * Marvell PXA25x family clocks 3 * 4 * Copyright (C) 2014 Robert Jarzmik 5 * 6 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this 13 * should go away. 14 */ 15 #include <linux/clk-provider.h> 16 #include <linux/clk.h> 17 #include <linux/clkdev.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <mach/pxa2xx-regs.h> 21 22 #include <dt-bindings/clock/pxa-clock.h> 23 #include "clk-pxa.h" 24 25 #define KHz 1000 26 #define MHz (1000 * 1000) 27 28 enum { 29 PXA_CORE_RUN = 0, 30 PXA_CORE_TURBO, 31 }; 32 33 /* 34 * Various clock factors driven by the CCCR register. 35 */ 36 37 /* Crystal Frequency to Memory Frequency Multiplier (L) */ 38 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; 39 40 /* Memory Frequency to Run Mode Frequency Multiplier (M) */ 41 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; 42 43 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ 44 /* Note: we store the value N * 2 here. */ 45 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; 46 47 static const char * const get_freq_khz[] = { 48 "core", "run", "cpll", "memory" 49 }; 50 51 /* 52 * Get the clock frequency as reflected by CCCR and the turbo flag. 53 * We assume these values have been applied via a fcs. 54 * If info is not 0 we also display the current settings. 55 */ 56 unsigned int pxa25x_get_clk_frequency_khz(int info) 57 { 58 struct clk *clk; 59 unsigned long clks[5]; 60 int i; 61 62 for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) { 63 clk = clk_get(NULL, get_freq_khz[i]); 64 if (IS_ERR(clk)) { 65 clks[i] = 0; 66 } else { 67 clks[i] = clk_get_rate(clk); 68 clk_put(clk); 69 } 70 } 71 72 if (info) { 73 pr_info("Run Mode clock: %ld.%02ldMHz\n", 74 clks[1] / 1000000, (clks[1] % 1000000) / 10000); 75 pr_info("Turbo Mode clock: %ld.%02ldMHz\n", 76 clks[2] / 1000000, (clks[2] % 1000000) / 10000); 77 pr_info("Memory clock: %ld.%02ldMHz\n", 78 clks[3] / 1000000, (clks[3] % 1000000) / 10000); 79 } 80 81 return (unsigned int)clks[0] / KHz; 82 } 83 84 static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw, 85 unsigned long parent_rate) 86 { 87 unsigned long cccr = readl(CCCR); 88 unsigned int m = M_clk_mult[(cccr >> 5) & 0x03]; 89 90 return parent_rate / m; 91 } 92 PARENTS(clk_pxa25x_memory) = { "run" }; 93 RATE_RO_OPS(clk_pxa25x_memory, "memory"); 94 95 PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" }; 96 PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" }; 97 PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" }; 98 99 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \ 100 bit, is_lp, flags) \ 101 PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \ 102 is_lp, CKEN, CKEN_ ## bit, flags) 103 #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ 104 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \ 105 div_hp, bit, NULL, 0) 106 #define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\ 107 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \ 108 div_hp, bit, NULL, 0) 109 #define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ 110 PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \ 111 div_hp, bit, NULL, 0) 112 113 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ 114 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 115 CKEN, CKEN_ ## bit, 0) 116 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ 117 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 118 CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED) 119 120 static struct desc_clk_cken pxa25x_clocks[] __initdata = { 121 PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0), 122 PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0), 123 PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0), 124 PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5), 125 PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1), 126 PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1), 127 PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1), 128 PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1), 129 PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0), 130 PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0), 131 PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0), 132 PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0), 133 PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0), 134 PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0), 135 PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0), 136 137 PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0), 138 PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC, 139 clk_pxa25x_memory_parents, 0), 140 }; 141 142 static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw) 143 { 144 unsigned long clkcfg; 145 unsigned int t; 146 147 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 148 t = clkcfg & (1 << 0); 149 if (t) 150 return PXA_CORE_TURBO; 151 return PXA_CORE_RUN; 152 } 153 154 static unsigned long clk_pxa25x_core_get_rate(struct clk_hw *hw, 155 unsigned long parent_rate) 156 { 157 return parent_rate; 158 } 159 PARENTS(clk_pxa25x_core) = { "run", "cpll" }; 160 MUX_RO_RATE_RO_OPS(clk_pxa25x_core, "core"); 161 162 static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw, 163 unsigned long parent_rate) 164 { 165 unsigned long cccr = readl(CCCR); 166 unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 167 168 return (parent_rate / n2) * 2; 169 } 170 PARENTS(clk_pxa25x_run) = { "cpll" }; 171 RATE_RO_OPS(clk_pxa25x_run, "run"); 172 173 static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw, 174 unsigned long parent_rate) 175 { 176 unsigned long clkcfg, cccr = readl(CCCR); 177 unsigned int l, m, n2, t; 178 179 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 180 t = clkcfg & (1 << 0); 181 l = L_clk_mult[(cccr >> 0) & 0x1f]; 182 m = M_clk_mult[(cccr >> 5) & 0x03]; 183 n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 184 185 if (t) 186 return m * l * n2 * parent_rate / 2; 187 return m * l * parent_rate; 188 } 189 PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" }; 190 RATE_RO_OPS(clk_pxa25x_cpll, "cpll"); 191 192 static void __init pxa25x_register_core(void) 193 { 194 clk_register_clk_pxa25x_cpll(); 195 clk_register_clk_pxa25x_run(); 196 clkdev_pxa_register(CLK_CORE, "core", NULL, 197 clk_register_clk_pxa25x_core()); 198 } 199 200 static void __init pxa25x_register_plls(void) 201 { 202 clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL, 203 CLK_GET_RATE_NOCACHE, 3686400); 204 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, 205 CLK_GET_RATE_NOCACHE, 32768); 206 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0); 207 clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz", 208 0, 26, 1); 209 clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz", 210 0, 40, 1); 211 } 212 213 static void __init pxa25x_base_clocks_init(void) 214 { 215 pxa25x_register_plls(); 216 pxa25x_register_core(); 217 clk_register_clk_pxa25x_memory(); 218 } 219 220 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ 221 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent } 222 struct dummy_clk { 223 const char *con_id; 224 const char *dev_id; 225 const char *parent; 226 }; 227 static struct dummy_clk dummy_clks[] __initdata = { 228 DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"), 229 DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"), 230 DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"), 231 DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"), 232 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"), 233 DUMMY_CLK("OSTIMER0", NULL, "osc_32_768khz"), 234 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"), 235 }; 236 237 static void __init pxa25x_dummy_clocks_init(void) 238 { 239 struct clk *clk; 240 struct dummy_clk *d; 241 const char *name; 242 int i; 243 244 /* 245 * All pinctrl logic has been wiped out of the clock driver, especially 246 * for gpio11 and gpio12 outputs. Machine code should ensure proper pin 247 * control (ie. pxa2xx_mfp_config() invocation). 248 */ 249 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) { 250 d = &dummy_clks[i]; 251 name = d->dev_id ? d->dev_id : d->con_id; 252 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1); 253 clk_register_clkdev(clk, d->con_id, d->dev_id); 254 } 255 } 256 257 int __init pxa25x_clocks_init(void) 258 { 259 pxa25x_base_clocks_init(); 260 pxa25x_dummy_clocks_init(); 261 return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks)); 262 } 263 264 static void __init pxa25x_dt_clocks_init(struct device_node *np) 265 { 266 pxa25x_clocks_init(); 267 clk_pxa_dt_common_init(np); 268 } 269 CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks", 270 pxa25x_dt_clocks_init); 271