1 /* 2 * Copyright 2015 Vladimir Zapolskiy <vz@mleia.com> 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of_address.h> 15 #include <linux/regmap.h> 16 17 #include <dt-bindings/clock/lpc32xx-clock.h> 18 19 #undef pr_fmt 20 #define pr_fmt(fmt) "%s: " fmt, __func__ 21 22 /* Common bitfield definitions for x397 PLL (lock), USB PLL and HCLK PLL */ 23 #define PLL_CTRL_ENABLE BIT(16) 24 #define PLL_CTRL_BYPASS BIT(15) 25 #define PLL_CTRL_DIRECT BIT(14) 26 #define PLL_CTRL_FEEDBACK BIT(13) 27 #define PLL_CTRL_POSTDIV (BIT(12)|BIT(11)) 28 #define PLL_CTRL_PREDIV (BIT(10)|BIT(9)) 29 #define PLL_CTRL_FEEDDIV (0xFF << 1) 30 #define PLL_CTRL_LOCK BIT(0) 31 32 /* Clock registers on System Control Block */ 33 #define LPC32XX_CLKPWR_DEBUG_CTRL 0x00 34 #define LPC32XX_CLKPWR_USB_DIV 0x1C 35 #define LPC32XX_CLKPWR_HCLKDIV_CTRL 0x40 36 #define LPC32XX_CLKPWR_PWR_CTRL 0x44 37 #define LPC32XX_CLKPWR_PLL397_CTRL 0x48 38 #define LPC32XX_CLKPWR_OSC_CTRL 0x4C 39 #define LPC32XX_CLKPWR_SYSCLK_CTRL 0x50 40 #define LPC32XX_CLKPWR_LCDCLK_CTRL 0x54 41 #define LPC32XX_CLKPWR_HCLKPLL_CTRL 0x58 42 #define LPC32XX_CLKPWR_ADCCLK_CTRL1 0x60 43 #define LPC32XX_CLKPWR_USB_CTRL 0x64 44 #define LPC32XX_CLKPWR_SSP_CTRL 0x78 45 #define LPC32XX_CLKPWR_I2S_CTRL 0x7C 46 #define LPC32XX_CLKPWR_MS_CTRL 0x80 47 #define LPC32XX_CLKPWR_MACCLK_CTRL 0x90 48 #define LPC32XX_CLKPWR_TEST_CLK_CTRL 0xA4 49 #define LPC32XX_CLKPWR_I2CCLK_CTRL 0xAC 50 #define LPC32XX_CLKPWR_KEYCLK_CTRL 0xB0 51 #define LPC32XX_CLKPWR_ADCCLK_CTRL 0xB4 52 #define LPC32XX_CLKPWR_PWMCLK_CTRL 0xB8 53 #define LPC32XX_CLKPWR_TIMCLK_CTRL 0xBC 54 #define LPC32XX_CLKPWR_TIMCLK_CTRL1 0xC0 55 #define LPC32XX_CLKPWR_SPI_CTRL 0xC4 56 #define LPC32XX_CLKPWR_FLASHCLK_CTRL 0xC8 57 #define LPC32XX_CLKPWR_UART3_CLK_CTRL 0xD0 58 #define LPC32XX_CLKPWR_UART4_CLK_CTRL 0xD4 59 #define LPC32XX_CLKPWR_UART5_CLK_CTRL 0xD8 60 #define LPC32XX_CLKPWR_UART6_CLK_CTRL 0xDC 61 #define LPC32XX_CLKPWR_IRDA_CLK_CTRL 0xE0 62 #define LPC32XX_CLKPWR_UART_CLK_CTRL 0xE4 63 #define LPC32XX_CLKPWR_DMA_CLK_CTRL 0xE8 64 65 /* Clock registers on USB controller */ 66 #define LPC32XX_USB_CLK_CTRL 0xF4 67 #define LPC32XX_USB_CLK_STS 0xF8 68 69 static struct regmap_config lpc32xx_scb_regmap_config = { 70 .reg_bits = 32, 71 .val_bits = 32, 72 .reg_stride = 4, 73 .val_format_endian = REGMAP_ENDIAN_LITTLE, 74 .max_register = 0x114, 75 .fast_io = true, 76 }; 77 78 static struct regmap *clk_regmap; 79 static void __iomem *usb_clk_vbase; 80 81 enum { 82 LPC32XX_USB_CLK_OTG = LPC32XX_USB_CLK_HOST + 1, 83 LPC32XX_USB_CLK_AHB, 84 85 LPC32XX_USB_CLK_MAX = LPC32XX_USB_CLK_AHB + 1, 86 }; 87 88 enum { 89 /* Start from the last defined clock in dt bindings */ 90 LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_PERIPH + 1, 91 LPC32XX_CLK_ADC_RTC, 92 LPC32XX_CLK_TEST1, 93 LPC32XX_CLK_TEST2, 94 95 /* System clocks, PLL 397x and HCLK PLL clocks */ 96 LPC32XX_CLK_OSC, 97 LPC32XX_CLK_SYS, 98 LPC32XX_CLK_PLL397X, 99 LPC32XX_CLK_HCLK_DIV_PERIPH, 100 LPC32XX_CLK_HCLK_DIV, 101 LPC32XX_CLK_HCLK, 102 LPC32XX_CLK_ARM, 103 LPC32XX_CLK_ARM_VFP, 104 105 /* USB clocks */ 106 LPC32XX_CLK_USB_PLL, 107 LPC32XX_CLK_USB_DIV, 108 LPC32XX_CLK_USB, 109 110 /* Only one control PWR_CTRL[10] for both muxes */ 111 LPC32XX_CLK_PERIPH_HCLK_MUX, 112 LPC32XX_CLK_PERIPH_ARM_MUX, 113 114 /* Only one control PWR_CTRL[2] for all three muxes */ 115 LPC32XX_CLK_SYSCLK_PERIPH_MUX, 116 LPC32XX_CLK_SYSCLK_HCLK_MUX, 117 LPC32XX_CLK_SYSCLK_ARM_MUX, 118 119 /* Two clock sources external to the driver */ 120 LPC32XX_CLK_XTAL_32K, 121 LPC32XX_CLK_XTAL, 122 123 /* Renumbered USB clocks, may have a parent from SCB table */ 124 LPC32XX_CLK_USB_OFFSET, 125 LPC32XX_CLK_USB_I2C = LPC32XX_USB_CLK_I2C + LPC32XX_CLK_USB_OFFSET, 126 LPC32XX_CLK_USB_DEV = LPC32XX_USB_CLK_DEVICE + LPC32XX_CLK_USB_OFFSET, 127 LPC32XX_CLK_USB_HOST = LPC32XX_USB_CLK_HOST + LPC32XX_CLK_USB_OFFSET, 128 LPC32XX_CLK_USB_OTG = LPC32XX_USB_CLK_OTG + LPC32XX_CLK_USB_OFFSET, 129 LPC32XX_CLK_USB_AHB = LPC32XX_USB_CLK_AHB + LPC32XX_CLK_USB_OFFSET, 130 131 /* Stub for composite clocks */ 132 LPC32XX_CLK__NULL, 133 134 /* Subclocks of composite clocks, clocks above are for CCF */ 135 LPC32XX_CLK_PWM1_MUX, 136 LPC32XX_CLK_PWM1_DIV, 137 LPC32XX_CLK_PWM1_GATE, 138 LPC32XX_CLK_PWM2_MUX, 139 LPC32XX_CLK_PWM2_DIV, 140 LPC32XX_CLK_PWM2_GATE, 141 LPC32XX_CLK_UART3_MUX, 142 LPC32XX_CLK_UART3_DIV, 143 LPC32XX_CLK_UART3_GATE, 144 LPC32XX_CLK_UART4_MUX, 145 LPC32XX_CLK_UART4_DIV, 146 LPC32XX_CLK_UART4_GATE, 147 LPC32XX_CLK_UART5_MUX, 148 LPC32XX_CLK_UART5_DIV, 149 LPC32XX_CLK_UART5_GATE, 150 LPC32XX_CLK_UART6_MUX, 151 LPC32XX_CLK_UART6_DIV, 152 LPC32XX_CLK_UART6_GATE, 153 LPC32XX_CLK_TEST1_MUX, 154 LPC32XX_CLK_TEST1_GATE, 155 LPC32XX_CLK_TEST2_MUX, 156 LPC32XX_CLK_TEST2_GATE, 157 LPC32XX_CLK_USB_DIV_DIV, 158 LPC32XX_CLK_USB_DIV_GATE, 159 LPC32XX_CLK_SD_DIV, 160 LPC32XX_CLK_SD_GATE, 161 LPC32XX_CLK_LCD_DIV, 162 LPC32XX_CLK_LCD_GATE, 163 164 LPC32XX_CLK_HW_MAX, 165 LPC32XX_CLK_MAX = LPC32XX_CLK_SYSCLK_ARM_MUX + 1, 166 LPC32XX_CLK_CCF_MAX = LPC32XX_CLK_USB_AHB + 1, 167 }; 168 169 static struct clk *clk[LPC32XX_CLK_MAX]; 170 static struct clk_onecell_data clk_data = { 171 .clks = clk, 172 .clk_num = LPC32XX_CLK_MAX, 173 }; 174 175 static struct clk *usb_clk[LPC32XX_USB_CLK_MAX]; 176 static struct clk_onecell_data usb_clk_data = { 177 .clks = usb_clk, 178 .clk_num = LPC32XX_USB_CLK_MAX, 179 }; 180 181 #define LPC32XX_CLK_PARENTS_MAX 5 182 183 struct clk_proto_t { 184 const char *name; 185 const u8 parents[LPC32XX_CLK_PARENTS_MAX]; 186 u8 num_parents; 187 unsigned long flags; 188 }; 189 190 #define CLK_PREFIX(LITERAL) LPC32XX_CLK_ ## LITERAL 191 #define NUMARGS(...) (sizeof((int[]){__VA_ARGS__})/sizeof(int)) 192 193 #define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...) \ 194 [CLK_PREFIX(_idx)] = { \ 195 .name = _name, \ 196 .flags = _flags, \ 197 .parents = { __VA_ARGS__ }, \ 198 .num_parents = NUMARGS(__VA_ARGS__), \ 199 } 200 201 static const struct clk_proto_t clk_proto[LPC32XX_CLK_CCF_MAX] __initconst = { 202 LPC32XX_CLK_DEFINE(XTAL, "xtal", 0x0), 203 LPC32XX_CLK_DEFINE(XTAL_32K, "xtal_32k", 0x0), 204 205 LPC32XX_CLK_DEFINE(RTC, "rtc", 0x0, LPC32XX_CLK_XTAL_32K), 206 LPC32XX_CLK_DEFINE(OSC, "osc", CLK_IGNORE_UNUSED, LPC32XX_CLK_XTAL), 207 LPC32XX_CLK_DEFINE(SYS, "sys", CLK_IGNORE_UNUSED, 208 LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X), 209 LPC32XX_CLK_DEFINE(PLL397X, "pll_397x", CLK_IGNORE_UNUSED, 210 LPC32XX_CLK_RTC), 211 LPC32XX_CLK_DEFINE(HCLK_PLL, "hclk_pll", CLK_IGNORE_UNUSED, 212 LPC32XX_CLK_SYS), 213 LPC32XX_CLK_DEFINE(HCLK_DIV_PERIPH, "hclk_div_periph", 214 CLK_IGNORE_UNUSED, LPC32XX_CLK_HCLK_PLL), 215 LPC32XX_CLK_DEFINE(HCLK_DIV, "hclk_div", CLK_IGNORE_UNUSED, 216 LPC32XX_CLK_HCLK_PLL), 217 LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED, 218 LPC32XX_CLK_PERIPH_HCLK_MUX), 219 LPC32XX_CLK_DEFINE(PERIPH, "pclk", CLK_IGNORE_UNUSED, 220 LPC32XX_CLK_SYSCLK_PERIPH_MUX), 221 LPC32XX_CLK_DEFINE(ARM, "arm", CLK_IGNORE_UNUSED, 222 LPC32XX_CLK_PERIPH_ARM_MUX), 223 224 LPC32XX_CLK_DEFINE(PERIPH_HCLK_MUX, "periph_hclk_mux", 225 CLK_IGNORE_UNUSED, 226 LPC32XX_CLK_SYSCLK_HCLK_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX), 227 LPC32XX_CLK_DEFINE(PERIPH_ARM_MUX, "periph_arm_mux", CLK_IGNORE_UNUSED, 228 LPC32XX_CLK_SYSCLK_ARM_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX), 229 LPC32XX_CLK_DEFINE(SYSCLK_PERIPH_MUX, "sysclk_periph_mux", 230 CLK_IGNORE_UNUSED, 231 LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV_PERIPH), 232 LPC32XX_CLK_DEFINE(SYSCLK_HCLK_MUX, "sysclk_hclk_mux", 233 CLK_IGNORE_UNUSED, 234 LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV), 235 LPC32XX_CLK_DEFINE(SYSCLK_ARM_MUX, "sysclk_arm_mux", CLK_IGNORE_UNUSED, 236 LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_PLL), 237 238 LPC32XX_CLK_DEFINE(ARM_VFP, "vfp9", CLK_IGNORE_UNUSED, 239 LPC32XX_CLK_ARM), 240 LPC32XX_CLK_DEFINE(USB_PLL, "usb_pll", 241 CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, LPC32XX_CLK_USB_DIV), 242 LPC32XX_CLK_DEFINE(USB_DIV, "usb_div", 0x0, LPC32XX_CLK_OSC), 243 LPC32XX_CLK_DEFINE(USB, "usb", 0x0, LPC32XX_CLK_USB_PLL), 244 LPC32XX_CLK_DEFINE(DMA, "dma", 0x0, LPC32XX_CLK_HCLK), 245 LPC32XX_CLK_DEFINE(MLC, "mlc", 0x0, LPC32XX_CLK_HCLK), 246 LPC32XX_CLK_DEFINE(SLC, "slc", 0x0, LPC32XX_CLK_HCLK), 247 LPC32XX_CLK_DEFINE(LCD, "lcd", 0x0, LPC32XX_CLK_HCLK), 248 LPC32XX_CLK_DEFINE(MAC, "mac", 0x0, LPC32XX_CLK_HCLK), 249 LPC32XX_CLK_DEFINE(SD, "sd", 0x0, LPC32XX_CLK_ARM), 250 LPC32XX_CLK_DEFINE(DDRAM, "ddram", CLK_GET_RATE_NOCACHE, 251 LPC32XX_CLK_SYSCLK_ARM_MUX), 252 LPC32XX_CLK_DEFINE(SSP0, "ssp0", 0x0, LPC32XX_CLK_HCLK), 253 LPC32XX_CLK_DEFINE(SSP1, "ssp1", 0x0, LPC32XX_CLK_HCLK), 254 255 /* 256 * CLK_GET_RATE_NOCACHE is needed, if UART clock is disabled, its 257 * divider register does not contain information about selected rate. 258 */ 259 LPC32XX_CLK_DEFINE(UART3, "uart3", CLK_GET_RATE_NOCACHE, 260 LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK), 261 LPC32XX_CLK_DEFINE(UART4, "uart4", CLK_GET_RATE_NOCACHE, 262 LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK), 263 LPC32XX_CLK_DEFINE(UART5, "uart5", CLK_GET_RATE_NOCACHE, 264 LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK), 265 LPC32XX_CLK_DEFINE(UART6, "uart6", CLK_GET_RATE_NOCACHE, 266 LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK), 267 LPC32XX_CLK_DEFINE(IRDA, "irda", 0x0, LPC32XX_CLK_PERIPH), 268 LPC32XX_CLK_DEFINE(I2C1, "i2c1", 0x0, LPC32XX_CLK_HCLK), 269 LPC32XX_CLK_DEFINE(I2C2, "i2c2", 0x0, LPC32XX_CLK_HCLK), 270 LPC32XX_CLK_DEFINE(TIMER0, "timer0", 0x0, LPC32XX_CLK_PERIPH), 271 LPC32XX_CLK_DEFINE(TIMER1, "timer1", 0x0, LPC32XX_CLK_PERIPH), 272 LPC32XX_CLK_DEFINE(TIMER2, "timer2", 0x0, LPC32XX_CLK_PERIPH), 273 LPC32XX_CLK_DEFINE(TIMER3, "timer3", 0x0, LPC32XX_CLK_PERIPH), 274 LPC32XX_CLK_DEFINE(TIMER4, "timer4", 0x0, LPC32XX_CLK_PERIPH), 275 LPC32XX_CLK_DEFINE(TIMER5, "timer5", 0x0, LPC32XX_CLK_PERIPH), 276 LPC32XX_CLK_DEFINE(WDOG, "watchdog", 0x0, LPC32XX_CLK_PERIPH), 277 LPC32XX_CLK_DEFINE(I2S0, "i2s0", 0x0, LPC32XX_CLK_HCLK), 278 LPC32XX_CLK_DEFINE(I2S1, "i2s1", 0x0, LPC32XX_CLK_HCLK), 279 LPC32XX_CLK_DEFINE(SPI1, "spi1", 0x0, LPC32XX_CLK_HCLK), 280 LPC32XX_CLK_DEFINE(SPI2, "spi2", 0x0, LPC32XX_CLK_HCLK), 281 LPC32XX_CLK_DEFINE(MCPWM, "mcpwm", 0x0, LPC32XX_CLK_HCLK), 282 LPC32XX_CLK_DEFINE(HSTIMER, "hstimer", 0x0, LPC32XX_CLK_PERIPH), 283 LPC32XX_CLK_DEFINE(KEY, "key", 0x0, LPC32XX_CLK_RTC), 284 LPC32XX_CLK_DEFINE(PWM1, "pwm1", 0x0, 285 LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH), 286 LPC32XX_CLK_DEFINE(PWM2, "pwm2", 0x0, 287 LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH), 288 LPC32XX_CLK_DEFINE(ADC, "adc", 0x0, 289 LPC32XX_CLK_ADC_RTC, LPC32XX_CLK_ADC_DIV), 290 LPC32XX_CLK_DEFINE(ADC_DIV, "adc_div", 0x0, LPC32XX_CLK_PERIPH), 291 LPC32XX_CLK_DEFINE(ADC_RTC, "adc_rtc", 0x0, LPC32XX_CLK_RTC), 292 LPC32XX_CLK_DEFINE(TEST1, "test1", 0x0, 293 LPC32XX_CLK_PERIPH, LPC32XX_CLK_RTC, LPC32XX_CLK_OSC), 294 LPC32XX_CLK_DEFINE(TEST2, "test2", 0x0, 295 LPC32XX_CLK_HCLK, LPC32XX_CLK_PERIPH, LPC32XX_CLK_USB, 296 LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X), 297 298 /* USB controller clocks */ 299 LPC32XX_CLK_DEFINE(USB_AHB, "usb_ahb", 0x0, LPC32XX_CLK_USB), 300 LPC32XX_CLK_DEFINE(USB_OTG, "usb_otg", 0x0, LPC32XX_CLK_USB_AHB), 301 LPC32XX_CLK_DEFINE(USB_I2C, "usb_i2c", 0x0, LPC32XX_CLK_USB_AHB), 302 LPC32XX_CLK_DEFINE(USB_DEV, "usb_dev", 0x0, LPC32XX_CLK_USB_OTG), 303 LPC32XX_CLK_DEFINE(USB_HOST, "usb_host", 0x0, LPC32XX_CLK_USB_OTG), 304 }; 305 306 struct lpc32xx_clk { 307 struct clk_hw hw; 308 u32 reg; 309 u32 enable; 310 u32 enable_mask; 311 u32 disable; 312 u32 disable_mask; 313 u32 busy; 314 u32 busy_mask; 315 }; 316 317 enum clk_pll_mode { 318 PLL_UNKNOWN, 319 PLL_DIRECT, 320 PLL_BYPASS, 321 PLL_DIRECT_BYPASS, 322 PLL_INTEGER, 323 PLL_NON_INTEGER, 324 }; 325 326 struct lpc32xx_pll_clk { 327 struct clk_hw hw; 328 u32 reg; 329 u32 enable; 330 unsigned long m_div; 331 unsigned long n_div; 332 unsigned long p_div; 333 enum clk_pll_mode mode; 334 }; 335 336 struct lpc32xx_usb_clk { 337 struct clk_hw hw; 338 u32 ctrl_enable; 339 u32 ctrl_disable; 340 u32 ctrl_mask; 341 u32 enable; 342 u32 busy; 343 }; 344 345 struct lpc32xx_clk_mux { 346 struct clk_hw hw; 347 u32 reg; 348 u32 mask; 349 u8 shift; 350 u32 *table; 351 u8 flags; 352 }; 353 354 struct lpc32xx_clk_div { 355 struct clk_hw hw; 356 u32 reg; 357 u8 shift; 358 u8 width; 359 const struct clk_div_table *table; 360 u8 flags; 361 }; 362 363 struct lpc32xx_clk_gate { 364 struct clk_hw hw; 365 u32 reg; 366 u8 bit_idx; 367 u8 flags; 368 }; 369 370 #define to_lpc32xx_clk(_hw) container_of(_hw, struct lpc32xx_clk, hw) 371 #define to_lpc32xx_pll_clk(_hw) container_of(_hw, struct lpc32xx_pll_clk, hw) 372 #define to_lpc32xx_usb_clk(_hw) container_of(_hw, struct lpc32xx_usb_clk, hw) 373 #define to_lpc32xx_mux(_hw) container_of(_hw, struct lpc32xx_clk_mux, hw) 374 #define to_lpc32xx_div(_hw) container_of(_hw, struct lpc32xx_clk_div, hw) 375 #define to_lpc32xx_gate(_hw) container_of(_hw, struct lpc32xx_clk_gate, hw) 376 377 static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max) 378 { 379 return (val0 >= (val1 * min) && val0 <= (val1 * max)); 380 } 381 382 static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk) 383 { 384 return readl(usb_clk_vbase + LPC32XX_USB_CLK_STS); 385 } 386 387 static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val) 388 { 389 writel(val, usb_clk_vbase + LPC32XX_USB_CLK_CTRL); 390 } 391 392 static int clk_mask_enable(struct clk_hw *hw) 393 { 394 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); 395 u32 val; 396 397 regmap_read(clk_regmap, clk->reg, &val); 398 399 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy) 400 return -EBUSY; 401 402 return regmap_update_bits(clk_regmap, clk->reg, 403 clk->enable_mask, clk->enable); 404 } 405 406 static void clk_mask_disable(struct clk_hw *hw) 407 { 408 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); 409 410 regmap_update_bits(clk_regmap, clk->reg, 411 clk->disable_mask, clk->disable); 412 } 413 414 static int clk_mask_is_enabled(struct clk_hw *hw) 415 { 416 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); 417 u32 val; 418 419 regmap_read(clk_regmap, clk->reg, &val); 420 421 return ((val & clk->enable_mask) == clk->enable); 422 } 423 424 static const struct clk_ops clk_mask_ops = { 425 .enable = clk_mask_enable, 426 .disable = clk_mask_disable, 427 .is_enabled = clk_mask_is_enabled, 428 }; 429 430 static int clk_pll_enable(struct clk_hw *hw) 431 { 432 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); 433 u32 val, count; 434 435 regmap_update_bits(clk_regmap, clk->reg, clk->enable, clk->enable); 436 437 for (count = 0; count < 1000; count++) { 438 regmap_read(clk_regmap, clk->reg, &val); 439 if (val & PLL_CTRL_LOCK) 440 break; 441 } 442 443 if (val & PLL_CTRL_LOCK) 444 return 0; 445 446 return -ETIMEDOUT; 447 } 448 449 static void clk_pll_disable(struct clk_hw *hw) 450 { 451 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); 452 453 regmap_update_bits(clk_regmap, clk->reg, clk->enable, 0x0); 454 } 455 456 static int clk_pll_is_enabled(struct clk_hw *hw) 457 { 458 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); 459 u32 val; 460 461 regmap_read(clk_regmap, clk->reg, &val); 462 463 val &= clk->enable | PLL_CTRL_LOCK; 464 if (val == (clk->enable | PLL_CTRL_LOCK)) 465 return 1; 466 467 return 0; 468 } 469 470 static unsigned long clk_pll_397x_recalc_rate(struct clk_hw *hw, 471 unsigned long parent_rate) 472 { 473 return parent_rate * 397; 474 } 475 476 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 477 unsigned long parent_rate) 478 { 479 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); 480 bool is_direct, is_bypass, is_feedback; 481 unsigned long rate, cco_rate, ref_rate; 482 u32 val; 483 484 regmap_read(clk_regmap, clk->reg, &val); 485 is_direct = val & PLL_CTRL_DIRECT; 486 is_bypass = val & PLL_CTRL_BYPASS; 487 is_feedback = val & PLL_CTRL_FEEDBACK; 488 489 clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1; 490 clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1; 491 clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1; 492 493 if (is_direct && is_bypass) { 494 clk->p_div = 0; 495 clk->mode = PLL_DIRECT_BYPASS; 496 return parent_rate; 497 } 498 if (is_bypass) { 499 clk->mode = PLL_BYPASS; 500 return parent_rate / (1 << clk->p_div); 501 } 502 if (is_direct) { 503 clk->p_div = 0; 504 clk->mode = PLL_DIRECT; 505 } 506 507 ref_rate = parent_rate / clk->n_div; 508 rate = cco_rate = ref_rate * clk->m_div; 509 510 if (!is_direct) { 511 if (is_feedback) { 512 cco_rate *= (1 << clk->p_div); 513 clk->mode = PLL_INTEGER; 514 } else { 515 rate /= (1 << clk->p_div); 516 clk->mode = PLL_NON_INTEGER; 517 } 518 } 519 520 pr_debug("%s: %lu: 0x%x: %d/%d/%d, %lu/%lu/%d => %lu\n", 521 clk_hw_get_name(hw), 522 parent_rate, val, is_direct, is_bypass, is_feedback, 523 clk->n_div, clk->m_div, (1 << clk->p_div), rate); 524 525 if (clk_pll_is_enabled(hw) && 526 !(pll_is_valid(parent_rate, 1, 1000000, 20000000) 527 && pll_is_valid(cco_rate, 1, 156000000, 320000000) 528 && pll_is_valid(ref_rate, 1, 1000000, 27000000))) 529 pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu", 530 clk_hw_get_name(hw), 531 parent_rate, cco_rate, ref_rate); 532 533 return rate; 534 } 535 536 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 537 unsigned long parent_rate) 538 { 539 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); 540 u32 val; 541 unsigned long new_rate; 542 543 /* Validate PLL clock parameters computed on round rate stage */ 544 switch (clk->mode) { 545 case PLL_DIRECT: 546 val = PLL_CTRL_DIRECT; 547 val |= (clk->m_div - 1) << 1; 548 val |= (clk->n_div - 1) << 9; 549 new_rate = (parent_rate * clk->m_div) / clk->n_div; 550 break; 551 case PLL_BYPASS: 552 val = PLL_CTRL_BYPASS; 553 val |= (clk->p_div - 1) << 11; 554 new_rate = parent_rate / (1 << (clk->p_div)); 555 break; 556 case PLL_DIRECT_BYPASS: 557 val = PLL_CTRL_DIRECT | PLL_CTRL_BYPASS; 558 new_rate = parent_rate; 559 break; 560 case PLL_INTEGER: 561 val = PLL_CTRL_FEEDBACK; 562 val |= (clk->m_div - 1) << 1; 563 val |= (clk->n_div - 1) << 9; 564 val |= (clk->p_div - 1) << 11; 565 new_rate = (parent_rate * clk->m_div) / clk->n_div; 566 break; 567 case PLL_NON_INTEGER: 568 val = 0x0; 569 val |= (clk->m_div - 1) << 1; 570 val |= (clk->n_div - 1) << 9; 571 val |= (clk->p_div - 1) << 11; 572 new_rate = (parent_rate * clk->m_div) / 573 (clk->n_div * (1 << clk->p_div)); 574 break; 575 default: 576 return -EINVAL; 577 } 578 579 /* Sanity check that round rate is equal to the requested one */ 580 if (new_rate != rate) 581 return -EINVAL; 582 583 return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val); 584 } 585 586 static long clk_hclk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 587 unsigned long *parent_rate) 588 { 589 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); 590 u64 m_i, o = rate, i = *parent_rate, d = (u64)rate << 6; 591 u64 m = 0, n = 0, p = 0; 592 int p_i, n_i; 593 594 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); 595 596 if (rate > 266500000) 597 return -EINVAL; 598 599 /* Have to check all 20 possibilities to find the minimal M */ 600 for (p_i = 4; p_i >= 0; p_i--) { 601 for (n_i = 4; n_i > 0; n_i--) { 602 m_i = div64_u64(o * n_i * (1 << p_i), i); 603 604 /* Check for valid PLL parameter constraints */ 605 if (!(m_i && m_i <= 256 606 && pll_is_valid(i, n_i, 1000000, 27000000) 607 && pll_is_valid(i * m_i * (1 << p_i), n_i, 608 156000000, 320000000))) 609 continue; 610 611 /* Store some intermediate valid parameters */ 612 if (o * n_i * (1 << p_i) - i * m_i <= d) { 613 m = m_i; 614 n = n_i; 615 p = p_i; 616 d = o * n_i * (1 << p_i) - i * m_i; 617 } 618 } 619 } 620 621 if (d == (u64)rate << 6) { 622 pr_err("%s: %lu: no valid PLL parameters are found\n", 623 clk_hw_get_name(hw), rate); 624 return -EINVAL; 625 } 626 627 clk->m_div = m; 628 clk->n_div = n; 629 clk->p_div = p; 630 631 /* Set only direct or non-integer mode of PLL */ 632 if (!p) 633 clk->mode = PLL_DIRECT; 634 else 635 clk->mode = PLL_NON_INTEGER; 636 637 o = div64_u64(i * m, n * (1 << p)); 638 639 if (!d) 640 pr_debug("%s: %lu: found exact match: %llu/%llu/%llu\n", 641 clk_hw_get_name(hw), rate, m, n, p); 642 else 643 pr_debug("%s: %lu: found closest: %llu/%llu/%llu - %llu\n", 644 clk_hw_get_name(hw), rate, m, n, p, o); 645 646 return o; 647 } 648 649 static long clk_usb_pll_round_rate(struct clk_hw *hw, unsigned long rate, 650 unsigned long *parent_rate) 651 { 652 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); 653 struct clk_hw *usb_div_hw, *osc_hw; 654 u64 d_i, n_i, m, o; 655 656 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); 657 658 /* 659 * The only supported USB clock is 48MHz, with PLL internal constraints 660 * on Fclkin, Fcco and Fref this implies that Fcco must be 192MHz 661 * and post-divider must be 4, this slightly simplifies calculation of 662 * USB divider, USB PLL N and M parameters. 663 */ 664 if (rate != 48000000) 665 return -EINVAL; 666 667 /* USB divider clock */ 668 usb_div_hw = clk_hw_get_parent_by_index(hw, 0); 669 if (!usb_div_hw) 670 return -EINVAL; 671 672 /* Main oscillator clock */ 673 osc_hw = clk_hw_get_parent_by_index(usb_div_hw, 0); 674 if (!osc_hw) 675 return -EINVAL; 676 o = clk_hw_get_rate(osc_hw); /* must be in range 1..20 MHz */ 677 678 /* Check if valid USB divider and USB PLL parameters exists */ 679 for (d_i = 16; d_i >= 1; d_i--) { 680 for (n_i = 1; n_i <= 4; n_i++) { 681 m = div64_u64(192000000 * d_i * n_i, o); 682 if (!(m && m <= 256 683 && m * o == 192000000 * d_i * n_i 684 && pll_is_valid(o, d_i, 1000000, 20000000) 685 && pll_is_valid(o, d_i * n_i, 1000000, 27000000))) 686 continue; 687 688 clk->n_div = n_i; 689 clk->m_div = m; 690 clk->p_div = 2; 691 clk->mode = PLL_NON_INTEGER; 692 *parent_rate = div64_u64(o, d_i); 693 694 return rate; 695 } 696 } 697 698 return -EINVAL; 699 } 700 701 #define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _rr) \ 702 static const struct clk_ops clk_ ##_name ## _ops = { \ 703 .enable = clk_pll_enable, \ 704 .disable = clk_pll_disable, \ 705 .is_enabled = clk_pll_is_enabled, \ 706 .recalc_rate = _rc, \ 707 .set_rate = _sr, \ 708 .round_rate = _rr, \ 709 } 710 711 LPC32XX_DEFINE_PLL_OPS(pll_397x, clk_pll_397x_recalc_rate, NULL, NULL); 712 LPC32XX_DEFINE_PLL_OPS(hclk_pll, clk_pll_recalc_rate, 713 clk_pll_set_rate, clk_hclk_pll_round_rate); 714 LPC32XX_DEFINE_PLL_OPS(usb_pll, clk_pll_recalc_rate, 715 clk_pll_set_rate, clk_usb_pll_round_rate); 716 717 static int clk_ddram_is_enabled(struct clk_hw *hw) 718 { 719 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); 720 u32 val; 721 722 regmap_read(clk_regmap, clk->reg, &val); 723 val &= clk->enable_mask | clk->busy_mask; 724 725 return (val == (BIT(7) | BIT(0)) || 726 val == (BIT(8) | BIT(1))); 727 } 728 729 static int clk_ddram_enable(struct clk_hw *hw) 730 { 731 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); 732 u32 val, hclk_div; 733 734 regmap_read(clk_regmap, clk->reg, &val); 735 hclk_div = val & clk->busy_mask; 736 737 /* 738 * DDRAM clock must be 2 times higher than HCLK, 739 * this implies DDRAM clock can not be enabled, 740 * if HCLK clock rate is equal to ARM clock rate 741 */ 742 if (hclk_div == 0x0 || hclk_div == (BIT(1) | BIT(0))) 743 return -EINVAL; 744 745 return regmap_update_bits(clk_regmap, clk->reg, 746 clk->enable_mask, hclk_div << 7); 747 } 748 749 static unsigned long clk_ddram_recalc_rate(struct clk_hw *hw, 750 unsigned long parent_rate) 751 { 752 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); 753 u32 val; 754 755 if (!clk_ddram_is_enabled(hw)) 756 return 0; 757 758 regmap_read(clk_regmap, clk->reg, &val); 759 val &= clk->enable_mask; 760 761 return parent_rate / (val >> 7); 762 } 763 764 static const struct clk_ops clk_ddram_ops = { 765 .enable = clk_ddram_enable, 766 .disable = clk_mask_disable, 767 .is_enabled = clk_ddram_is_enabled, 768 .recalc_rate = clk_ddram_recalc_rate, 769 }; 770 771 static unsigned long lpc32xx_clk_uart_recalc_rate(struct clk_hw *hw, 772 unsigned long parent_rate) 773 { 774 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); 775 u32 val, x, y; 776 777 regmap_read(clk_regmap, clk->reg, &val); 778 x = (val & 0xFF00) >> 8; 779 y = val & 0xFF; 780 781 if (x && y) 782 return (parent_rate * x) / y; 783 else 784 return 0; 785 } 786 787 static const struct clk_ops lpc32xx_uart_div_ops = { 788 .recalc_rate = lpc32xx_clk_uart_recalc_rate, 789 }; 790 791 static const struct clk_div_table clk_hclk_div_table[] = { 792 { .val = 0, .div = 1 }, 793 { .val = 1, .div = 2 }, 794 { .val = 2, .div = 4 }, 795 { }, 796 }; 797 798 static u32 test1_mux_table[] = { 0, 1, 2, }; 799 static u32 test2_mux_table[] = { 0, 1, 2, 5, 7, }; 800 801 static int clk_usb_enable(struct clk_hw *hw) 802 { 803 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw); 804 u32 val, ctrl_val, count; 805 806 pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable); 807 808 if (clk->ctrl_mask) { 809 regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val); 810 regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, 811 clk->ctrl_mask, clk->ctrl_enable); 812 } 813 814 val = lpc32xx_usb_clk_read(clk); 815 if (clk->busy && (val & clk->busy) == clk->busy) { 816 if (clk->ctrl_mask) 817 regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, 818 ctrl_val); 819 return -EBUSY; 820 } 821 822 val |= clk->enable; 823 lpc32xx_usb_clk_write(clk, val); 824 825 for (count = 0; count < 1000; count++) { 826 val = lpc32xx_usb_clk_read(clk); 827 if ((val & clk->enable) == clk->enable) 828 break; 829 } 830 831 if ((val & clk->enable) == clk->enable) 832 return 0; 833 834 if (clk->ctrl_mask) 835 regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, ctrl_val); 836 837 return -ETIMEDOUT; 838 } 839 840 static void clk_usb_disable(struct clk_hw *hw) 841 { 842 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw); 843 u32 val = lpc32xx_usb_clk_read(clk); 844 845 val &= ~clk->enable; 846 lpc32xx_usb_clk_write(clk, val); 847 848 if (clk->ctrl_mask) 849 regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, 850 clk->ctrl_mask, clk->ctrl_disable); 851 } 852 853 static int clk_usb_is_enabled(struct clk_hw *hw) 854 { 855 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw); 856 u32 ctrl_val, val; 857 858 if (clk->ctrl_mask) { 859 regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val); 860 if ((ctrl_val & clk->ctrl_mask) != clk->ctrl_enable) 861 return 0; 862 } 863 864 val = lpc32xx_usb_clk_read(clk); 865 866 return ((val & clk->enable) == clk->enable); 867 } 868 869 static unsigned long clk_usb_i2c_recalc_rate(struct clk_hw *hw, 870 unsigned long parent_rate) 871 { 872 return clk_get_rate(clk[LPC32XX_CLK_PERIPH]); 873 } 874 875 static const struct clk_ops clk_usb_ops = { 876 .enable = clk_usb_enable, 877 .disable = clk_usb_disable, 878 .is_enabled = clk_usb_is_enabled, 879 }; 880 881 static const struct clk_ops clk_usb_i2c_ops = { 882 .enable = clk_usb_enable, 883 .disable = clk_usb_disable, 884 .is_enabled = clk_usb_is_enabled, 885 .recalc_rate = clk_usb_i2c_recalc_rate, 886 }; 887 888 static int clk_gate_enable(struct clk_hw *hw) 889 { 890 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw); 891 u32 mask = BIT(clk->bit_idx); 892 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask); 893 894 return regmap_update_bits(clk_regmap, clk->reg, mask, val); 895 } 896 897 static void clk_gate_disable(struct clk_hw *hw) 898 { 899 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw); 900 u32 mask = BIT(clk->bit_idx); 901 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0); 902 903 regmap_update_bits(clk_regmap, clk->reg, mask, val); 904 } 905 906 static int clk_gate_is_enabled(struct clk_hw *hw) 907 { 908 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw); 909 u32 val; 910 bool is_set; 911 912 regmap_read(clk_regmap, clk->reg, &val); 913 is_set = val & BIT(clk->bit_idx); 914 915 return (clk->flags & CLK_GATE_SET_TO_DISABLE ? !is_set : is_set); 916 } 917 918 static const struct clk_ops lpc32xx_clk_gate_ops = { 919 .enable = clk_gate_enable, 920 .disable = clk_gate_disable, 921 .is_enabled = clk_gate_is_enabled, 922 }; 923 924 #define div_mask(width) ((1 << (width)) - 1) 925 926 static unsigned int _get_table_div(const struct clk_div_table *table, 927 unsigned int val) 928 { 929 const struct clk_div_table *clkt; 930 931 for (clkt = table; clkt->div; clkt++) 932 if (clkt->val == val) 933 return clkt->div; 934 return 0; 935 } 936 937 static unsigned int _get_div(const struct clk_div_table *table, 938 unsigned int val, unsigned long flags, u8 width) 939 { 940 if (flags & CLK_DIVIDER_ONE_BASED) 941 return val; 942 if (table) 943 return _get_table_div(table, val); 944 return val + 1; 945 } 946 947 static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, 948 unsigned long parent_rate) 949 { 950 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); 951 unsigned int val; 952 953 regmap_read(clk_regmap, divider->reg, &val); 954 955 val >>= divider->shift; 956 val &= div_mask(divider->width); 957 958 return divider_recalc_rate(hw, parent_rate, val, divider->table, 959 divider->flags); 960 } 961 962 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, 963 unsigned long *prate) 964 { 965 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); 966 unsigned int bestdiv; 967 968 /* if read only, just return current value */ 969 if (divider->flags & CLK_DIVIDER_READ_ONLY) { 970 regmap_read(clk_regmap, divider->reg, &bestdiv); 971 bestdiv >>= divider->shift; 972 bestdiv &= div_mask(divider->width); 973 bestdiv = _get_div(divider->table, bestdiv, divider->flags, 974 divider->width); 975 return DIV_ROUND_UP(*prate, bestdiv); 976 } 977 978 return divider_round_rate(hw, rate, prate, divider->table, 979 divider->width, divider->flags); 980 } 981 982 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 983 unsigned long parent_rate) 984 { 985 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); 986 unsigned int value; 987 988 value = divider_get_val(rate, parent_rate, divider->table, 989 divider->width, divider->flags); 990 991 return regmap_update_bits(clk_regmap, divider->reg, 992 div_mask(divider->width) << divider->shift, 993 value << divider->shift); 994 } 995 996 static const struct clk_ops lpc32xx_clk_divider_ops = { 997 .recalc_rate = clk_divider_recalc_rate, 998 .round_rate = clk_divider_round_rate, 999 .set_rate = clk_divider_set_rate, 1000 }; 1001 1002 static u8 clk_mux_get_parent(struct clk_hw *hw) 1003 { 1004 struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw); 1005 u32 num_parents = clk_hw_get_num_parents(hw); 1006 u32 val; 1007 1008 regmap_read(clk_regmap, mux->reg, &val); 1009 val >>= mux->shift; 1010 val &= mux->mask; 1011 1012 if (mux->table) { 1013 u32 i; 1014 1015 for (i = 0; i < num_parents; i++) 1016 if (mux->table[i] == val) 1017 return i; 1018 return -EINVAL; 1019 } 1020 1021 if (val >= num_parents) 1022 return -EINVAL; 1023 1024 return val; 1025 } 1026 1027 static int clk_mux_set_parent(struct clk_hw *hw, u8 index) 1028 { 1029 struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw); 1030 1031 if (mux->table) 1032 index = mux->table[index]; 1033 1034 return regmap_update_bits(clk_regmap, mux->reg, 1035 mux->mask << mux->shift, index << mux->shift); 1036 } 1037 1038 static const struct clk_ops lpc32xx_clk_mux_ro_ops = { 1039 .get_parent = clk_mux_get_parent, 1040 }; 1041 1042 static const struct clk_ops lpc32xx_clk_mux_ops = { 1043 .get_parent = clk_mux_get_parent, 1044 .set_parent = clk_mux_set_parent, 1045 .determine_rate = __clk_mux_determine_rate, 1046 }; 1047 1048 enum lpc32xx_clk_type { 1049 CLK_FIXED, 1050 CLK_MUX, 1051 CLK_DIV, 1052 CLK_GATE, 1053 CLK_COMPOSITE, 1054 CLK_LPC32XX, 1055 CLK_LPC32XX_PLL, 1056 CLK_LPC32XX_USB, 1057 }; 1058 1059 struct clk_hw_proto0 { 1060 const struct clk_ops *ops; 1061 union { 1062 struct lpc32xx_pll_clk pll; 1063 struct lpc32xx_clk clk; 1064 struct lpc32xx_usb_clk usb_clk; 1065 struct lpc32xx_clk_mux mux; 1066 struct lpc32xx_clk_div div; 1067 struct lpc32xx_clk_gate gate; 1068 }; 1069 }; 1070 1071 struct clk_hw_proto1 { 1072 struct clk_hw_proto0 *mux; 1073 struct clk_hw_proto0 *div; 1074 struct clk_hw_proto0 *gate; 1075 }; 1076 1077 struct clk_hw_proto { 1078 enum lpc32xx_clk_type type; 1079 1080 union { 1081 struct clk_fixed_rate f; 1082 struct clk_hw_proto0 hw0; 1083 struct clk_hw_proto1 hw1; 1084 }; 1085 }; 1086 1087 #define LPC32XX_DEFINE_FIXED(_idx, _rate, _flags) \ 1088 [CLK_PREFIX(_idx)] = { \ 1089 .type = CLK_FIXED, \ 1090 { \ 1091 .f = { \ 1092 .fixed_rate = (_rate), \ 1093 .flags = (_flags), \ 1094 }, \ 1095 }, \ 1096 } 1097 1098 #define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \ 1099 [CLK_PREFIX(_idx)] = { \ 1100 .type = CLK_LPC32XX_PLL, \ 1101 { \ 1102 .hw0 = { \ 1103 .ops = &clk_ ##_name ## _ops, \ 1104 { \ 1105 .pll = { \ 1106 .reg = LPC32XX_CLKPWR_ ## _reg, \ 1107 .enable = (_enable), \ 1108 }, \ 1109 }, \ 1110 }, \ 1111 }, \ 1112 } 1113 1114 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ 1115 [CLK_PREFIX(_idx)] = { \ 1116 .type = CLK_MUX, \ 1117 { \ 1118 .hw0 = { \ 1119 .ops = (_flags & CLK_MUX_READ_ONLY ? \ 1120 &lpc32xx_clk_mux_ro_ops : \ 1121 &lpc32xx_clk_mux_ops), \ 1122 { \ 1123 .mux = { \ 1124 .reg = LPC32XX_CLKPWR_ ## _reg, \ 1125 .mask = (_mask), \ 1126 .shift = (_shift), \ 1127 .table = (_table), \ 1128 .flags = (_flags), \ 1129 }, \ 1130 }, \ 1131 }, \ 1132 }, \ 1133 } 1134 1135 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ 1136 [CLK_PREFIX(_idx)] = { \ 1137 .type = CLK_DIV, \ 1138 { \ 1139 .hw0 = { \ 1140 .ops = &lpc32xx_clk_divider_ops, \ 1141 { \ 1142 .div = { \ 1143 .reg = LPC32XX_CLKPWR_ ## _reg, \ 1144 .shift = (_shift), \ 1145 .width = (_width), \ 1146 .table = (_table), \ 1147 .flags = (_flags), \ 1148 }, \ 1149 }, \ 1150 }, \ 1151 }, \ 1152 } 1153 1154 #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \ 1155 [CLK_PREFIX(_idx)] = { \ 1156 .type = CLK_GATE, \ 1157 { \ 1158 .hw0 = { \ 1159 .ops = &lpc32xx_clk_gate_ops, \ 1160 { \ 1161 .gate = { \ 1162 .reg = LPC32XX_CLKPWR_ ## _reg, \ 1163 .bit_idx = (_bit), \ 1164 .flags = (_flags), \ 1165 }, \ 1166 }, \ 1167 }, \ 1168 }, \ 1169 } 1170 1171 #define LPC32XX_DEFINE_CLK(_idx, _reg, _e, _em, _d, _dm, _b, _bm, _ops) \ 1172 [CLK_PREFIX(_idx)] = { \ 1173 .type = CLK_LPC32XX, \ 1174 { \ 1175 .hw0 = { \ 1176 .ops = &(_ops), \ 1177 { \ 1178 .clk = { \ 1179 .reg = LPC32XX_CLKPWR_ ## _reg, \ 1180 .enable = (_e), \ 1181 .enable_mask = (_em), \ 1182 .disable = (_d), \ 1183 .disable_mask = (_dm), \ 1184 .busy = (_b), \ 1185 .busy_mask = (_bm), \ 1186 }, \ 1187 }, \ 1188 }, \ 1189 }, \ 1190 } 1191 1192 #define LPC32XX_DEFINE_USB(_idx, _ce, _cd, _cm, _e, _b, _ops) \ 1193 [CLK_PREFIX(_idx)] = { \ 1194 .type = CLK_LPC32XX_USB, \ 1195 { \ 1196 .hw0 = { \ 1197 .ops = &(_ops), \ 1198 { \ 1199 .usb_clk = { \ 1200 .ctrl_enable = (_ce), \ 1201 .ctrl_disable = (_cd), \ 1202 .ctrl_mask = (_cm), \ 1203 .enable = (_e), \ 1204 .busy = (_b), \ 1205 } \ 1206 }, \ 1207 } \ 1208 }, \ 1209 } 1210 1211 #define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \ 1212 [CLK_PREFIX(_idx)] = { \ 1213 .type = CLK_COMPOSITE, \ 1214 { \ 1215 .hw1 = { \ 1216 .mux = (CLK_PREFIX(_mux) == LPC32XX_CLK__NULL ? NULL : \ 1217 &clk_hw_proto[CLK_PREFIX(_mux)].hw0), \ 1218 .div = (CLK_PREFIX(_div) == LPC32XX_CLK__NULL ? NULL : \ 1219 &clk_hw_proto[CLK_PREFIX(_div)].hw0), \ 1220 .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\ 1221 &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \ 1222 }, \ 1223 }, \ 1224 } 1225 1226 static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = { 1227 LPC32XX_DEFINE_FIXED(RTC, 32768, 0), 1228 LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)), 1229 LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE), 1230 LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE), 1231 LPC32XX_DEFINE_GATE(OSC, OSC_CTRL, 0, CLK_GATE_SET_TO_DISABLE), 1232 LPC32XX_DEFINE_GATE(USB, USB_CTRL, 18, 0), 1233 1234 LPC32XX_DEFINE_DIV(HCLK_DIV_PERIPH, HCLKDIV_CTRL, 2, 5, NULL, 1235 CLK_DIVIDER_READ_ONLY), 1236 LPC32XX_DEFINE_DIV(HCLK_DIV, HCLKDIV_CTRL, 0, 2, clk_hclk_div_table, 1237 CLK_DIVIDER_READ_ONLY), 1238 1239 /* Register 3 read-only muxes with a single control PWR_CTRL[2] */ 1240 LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL, 1241 CLK_MUX_READ_ONLY), 1242 LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL, 1243 CLK_MUX_READ_ONLY), 1244 LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL, 1245 CLK_MUX_READ_ONLY), 1246 /* Register 2 read-only muxes with a single control PWR_CTRL[10] */ 1247 LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL, 1248 CLK_MUX_READ_ONLY), 1249 LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL, 1250 CLK_MUX_READ_ONLY), 1251 1252 /* 3 always on gates with a single control PWR_CTRL[0] same as OSC */ 1253 LPC32XX_DEFINE_GATE(PERIPH, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE), 1254 LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE), 1255 LPC32XX_DEFINE_GATE(ARM, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE), 1256 1257 LPC32XX_DEFINE_GATE(ARM_VFP, DEBUG_CTRL, 4, 0), 1258 LPC32XX_DEFINE_GATE(DMA, DMA_CLK_CTRL, 0, 0), 1259 LPC32XX_DEFINE_CLK(DDRAM, HCLKDIV_CTRL, 0x0, BIT(8) | BIT(7), 1260 0x0, BIT(8) | BIT(7), 0x0, BIT(1) | BIT(0), clk_ddram_ops), 1261 1262 LPC32XX_DEFINE_GATE(TIMER0, TIMCLK_CTRL1, 2, 0), 1263 LPC32XX_DEFINE_GATE(TIMER1, TIMCLK_CTRL1, 3, 0), 1264 LPC32XX_DEFINE_GATE(TIMER2, TIMCLK_CTRL1, 4, 0), 1265 LPC32XX_DEFINE_GATE(TIMER3, TIMCLK_CTRL1, 5, 0), 1266 LPC32XX_DEFINE_GATE(TIMER4, TIMCLK_CTRL1, 0, 0), 1267 LPC32XX_DEFINE_GATE(TIMER5, TIMCLK_CTRL1, 1, 0), 1268 1269 LPC32XX_DEFINE_GATE(SSP0, SSP_CTRL, 0, 0), 1270 LPC32XX_DEFINE_GATE(SSP1, SSP_CTRL, 1, 0), 1271 LPC32XX_DEFINE_GATE(SPI1, SPI_CTRL, 0, 0), 1272 LPC32XX_DEFINE_GATE(SPI2, SPI_CTRL, 4, 0), 1273 LPC32XX_DEFINE_GATE(I2S0, I2S_CTRL, 0, 0), 1274 LPC32XX_DEFINE_GATE(I2S1, I2S_CTRL, 1, 0), 1275 LPC32XX_DEFINE_GATE(I2C1, I2CCLK_CTRL, 0, 0), 1276 LPC32XX_DEFINE_GATE(I2C2, I2CCLK_CTRL, 1, 0), 1277 LPC32XX_DEFINE_GATE(WDOG, TIMCLK_CTRL, 0, 0), 1278 LPC32XX_DEFINE_GATE(HSTIMER, TIMCLK_CTRL, 1, 0), 1279 1280 LPC32XX_DEFINE_GATE(KEY, KEYCLK_CTRL, 0, 0), 1281 LPC32XX_DEFINE_GATE(MCPWM, TIMCLK_CTRL1, 6, 0), 1282 1283 LPC32XX_DEFINE_MUX(PWM1_MUX, PWMCLK_CTRL, 1, 0x1, NULL, 0), 1284 LPC32XX_DEFINE_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL, 1285 CLK_DIVIDER_ONE_BASED), 1286 LPC32XX_DEFINE_GATE(PWM1_GATE, PWMCLK_CTRL, 0, 0), 1287 LPC32XX_DEFINE_COMPOSITE(PWM1, PWM1_MUX, PWM1_DIV, PWM1_GATE), 1288 1289 LPC32XX_DEFINE_MUX(PWM2_MUX, PWMCLK_CTRL, 3, 0x1, NULL, 0), 1290 LPC32XX_DEFINE_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL, 1291 CLK_DIVIDER_ONE_BASED), 1292 LPC32XX_DEFINE_GATE(PWM2_GATE, PWMCLK_CTRL, 2, 0), 1293 LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE), 1294 1295 LPC32XX_DEFINE_MUX(UART3_MUX, UART3_CLK_CTRL, 16, 0x1, NULL, 0), 1296 LPC32XX_DEFINE_CLK(UART3_DIV, UART3_CLK_CTRL, 1297 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), 1298 LPC32XX_DEFINE_GATE(UART3_GATE, UART_CLK_CTRL, 0, 0), 1299 LPC32XX_DEFINE_COMPOSITE(UART3, UART3_MUX, UART3_DIV, UART3_GATE), 1300 1301 LPC32XX_DEFINE_MUX(UART4_MUX, UART4_CLK_CTRL, 16, 0x1, NULL, 0), 1302 LPC32XX_DEFINE_CLK(UART4_DIV, UART4_CLK_CTRL, 1303 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), 1304 LPC32XX_DEFINE_GATE(UART4_GATE, UART_CLK_CTRL, 1, 0), 1305 LPC32XX_DEFINE_COMPOSITE(UART4, UART4_MUX, UART4_DIV, UART4_GATE), 1306 1307 LPC32XX_DEFINE_MUX(UART5_MUX, UART5_CLK_CTRL, 16, 0x1, NULL, 0), 1308 LPC32XX_DEFINE_CLK(UART5_DIV, UART5_CLK_CTRL, 1309 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), 1310 LPC32XX_DEFINE_GATE(UART5_GATE, UART_CLK_CTRL, 2, 0), 1311 LPC32XX_DEFINE_COMPOSITE(UART5, UART5_MUX, UART5_DIV, UART5_GATE), 1312 1313 LPC32XX_DEFINE_MUX(UART6_MUX, UART6_CLK_CTRL, 16, 0x1, NULL, 0), 1314 LPC32XX_DEFINE_CLK(UART6_DIV, UART6_CLK_CTRL, 1315 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), 1316 LPC32XX_DEFINE_GATE(UART6_GATE, UART_CLK_CTRL, 3, 0), 1317 LPC32XX_DEFINE_COMPOSITE(UART6, UART6_MUX, UART6_DIV, UART6_GATE), 1318 1319 LPC32XX_DEFINE_CLK(IRDA, IRDA_CLK_CTRL, 1320 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), 1321 1322 LPC32XX_DEFINE_MUX(TEST1_MUX, TEST_CLK_CTRL, 5, 0x3, 1323 test1_mux_table, 0), 1324 LPC32XX_DEFINE_GATE(TEST1_GATE, TEST_CLK_CTRL, 4, 0), 1325 LPC32XX_DEFINE_COMPOSITE(TEST1, TEST1_MUX, _NULL, TEST1_GATE), 1326 1327 LPC32XX_DEFINE_MUX(TEST2_MUX, TEST_CLK_CTRL, 1, 0x7, 1328 test2_mux_table, 0), 1329 LPC32XX_DEFINE_GATE(TEST2_GATE, TEST_CLK_CTRL, 0, 0), 1330 LPC32XX_DEFINE_COMPOSITE(TEST2, TEST2_MUX, _NULL, TEST2_GATE), 1331 1332 LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY), 1333 1334 LPC32XX_DEFINE_DIV(USB_DIV_DIV, USB_DIV, 0, 4, NULL, 0), 1335 LPC32XX_DEFINE_GATE(USB_DIV_GATE, USB_CTRL, 17, 0), 1336 LPC32XX_DEFINE_COMPOSITE(USB_DIV, _NULL, USB_DIV_DIV, USB_DIV_GATE), 1337 1338 LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED), 1339 LPC32XX_DEFINE_CLK(SD_GATE, MS_CTRL, BIT(5) | BIT(9), BIT(5) | BIT(9), 1340 0x0, BIT(5) | BIT(9), 0x0, 0x0, clk_mask_ops), 1341 LPC32XX_DEFINE_COMPOSITE(SD, _NULL, SD_DIV, SD_GATE), 1342 1343 LPC32XX_DEFINE_DIV(LCD_DIV, LCDCLK_CTRL, 0, 5, NULL, 0), 1344 LPC32XX_DEFINE_GATE(LCD_GATE, LCDCLK_CTRL, 5, 0), 1345 LPC32XX_DEFINE_COMPOSITE(LCD, _NULL, LCD_DIV, LCD_GATE), 1346 1347 LPC32XX_DEFINE_CLK(MAC, MACCLK_CTRL, 1348 BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0), 1349 BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0), 1350 0x0, 0x0, clk_mask_ops), 1351 LPC32XX_DEFINE_CLK(SLC, FLASHCLK_CTRL, 1352 BIT(2) | BIT(0), BIT(2) | BIT(0), 0x0, 1353 BIT(0), BIT(1), BIT(2) | BIT(1), clk_mask_ops), 1354 LPC32XX_DEFINE_CLK(MLC, FLASHCLK_CTRL, 1355 BIT(1), BIT(2) | BIT(1), 0x0, BIT(1), 1356 BIT(2) | BIT(0), BIT(2) | BIT(0), clk_mask_ops), 1357 /* 1358 * ADC/TS clock unfortunately cannot be registered as a composite one 1359 * due to a different connection of gate, div and mux, e.g. gating it 1360 * won't mean that the clock is off, if peripheral clock is its parent: 1361 * 1362 * rtc-->[gate]-->| | 1363 * | mux |--> adc/ts 1364 * pclk-->[div]-->| | 1365 * 1366 * Constraints: 1367 * ADC --- resulting clock must be <= 4.5 MHz 1368 * TS --- resulting clock must be <= 400 KHz 1369 */ 1370 LPC32XX_DEFINE_DIV(ADC_DIV, ADCCLK_CTRL1, 0, 8, NULL, 0), 1371 LPC32XX_DEFINE_GATE(ADC_RTC, ADCCLK_CTRL, 0, 0), 1372 LPC32XX_DEFINE_MUX(ADC, ADCCLK_CTRL1, 8, 0x1, NULL, 0), 1373 1374 /* USB controller clocks */ 1375 LPC32XX_DEFINE_USB(USB_AHB, 1376 BIT(24), 0x0, BIT(24), BIT(4), 0, clk_usb_ops), 1377 LPC32XX_DEFINE_USB(USB_OTG, 1378 0x0, 0x0, 0x0, BIT(3), 0, clk_usb_ops), 1379 LPC32XX_DEFINE_USB(USB_I2C, 1380 0x0, BIT(23), BIT(23), BIT(2), 0, clk_usb_i2c_ops), 1381 LPC32XX_DEFINE_USB(USB_DEV, 1382 BIT(22), 0x0, BIT(22), BIT(1), BIT(0), clk_usb_ops), 1383 LPC32XX_DEFINE_USB(USB_HOST, 1384 BIT(21), 0x0, BIT(21), BIT(0), BIT(1), clk_usb_ops), 1385 }; 1386 1387 static struct clk * __init lpc32xx_clk_register(u32 id) 1388 { 1389 const struct clk_proto_t *lpc32xx_clk = &clk_proto[id]; 1390 struct clk_hw_proto *clk_hw = &clk_hw_proto[id]; 1391 const char *parents[LPC32XX_CLK_PARENTS_MAX]; 1392 struct clk *clk; 1393 unsigned int i; 1394 1395 for (i = 0; i < lpc32xx_clk->num_parents; i++) 1396 parents[i] = clk_proto[lpc32xx_clk->parents[i]].name; 1397 1398 pr_debug("%s: derived from '%s', clock type %d\n", lpc32xx_clk->name, 1399 parents[0], clk_hw->type); 1400 1401 switch (clk_hw->type) { 1402 case CLK_LPC32XX: 1403 case CLK_LPC32XX_PLL: 1404 case CLK_LPC32XX_USB: 1405 case CLK_MUX: 1406 case CLK_DIV: 1407 case CLK_GATE: 1408 { 1409 struct clk_init_data clk_init = { 1410 .name = lpc32xx_clk->name, 1411 .parent_names = parents, 1412 .num_parents = lpc32xx_clk->num_parents, 1413 .flags = lpc32xx_clk->flags, 1414 .ops = clk_hw->hw0.ops, 1415 }; 1416 struct clk_hw *hw; 1417 1418 if (clk_hw->type == CLK_LPC32XX) 1419 hw = &clk_hw->hw0.clk.hw; 1420 else if (clk_hw->type == CLK_LPC32XX_PLL) 1421 hw = &clk_hw->hw0.pll.hw; 1422 else if (clk_hw->type == CLK_LPC32XX_USB) 1423 hw = &clk_hw->hw0.usb_clk.hw; 1424 else if (clk_hw->type == CLK_MUX) 1425 hw = &clk_hw->hw0.mux.hw; 1426 else if (clk_hw->type == CLK_DIV) 1427 hw = &clk_hw->hw0.div.hw; 1428 else if (clk_hw->type == CLK_GATE) 1429 hw = &clk_hw->hw0.gate.hw; 1430 else 1431 return ERR_PTR(-EINVAL); 1432 1433 hw->init = &clk_init; 1434 clk = clk_register(NULL, hw); 1435 break; 1436 } 1437 case CLK_COMPOSITE: 1438 { 1439 struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL; 1440 const struct clk_ops *mops = NULL, *dops = NULL, *gops = NULL; 1441 struct clk_hw_proto0 *mux0, *div0, *gate0; 1442 1443 mux0 = clk_hw->hw1.mux; 1444 div0 = clk_hw->hw1.div; 1445 gate0 = clk_hw->hw1.gate; 1446 if (mux0) { 1447 mops = mux0->ops; 1448 mux_hw = &mux0->clk.hw; 1449 } 1450 if (div0) { 1451 dops = div0->ops; 1452 div_hw = &div0->clk.hw; 1453 } 1454 if (gate0) { 1455 gops = gate0->ops; 1456 gate_hw = &gate0->clk.hw; 1457 } 1458 1459 clk = clk_register_composite(NULL, lpc32xx_clk->name, 1460 parents, lpc32xx_clk->num_parents, 1461 mux_hw, mops, div_hw, dops, 1462 gate_hw, gops, lpc32xx_clk->flags); 1463 break; 1464 } 1465 case CLK_FIXED: 1466 { 1467 struct clk_fixed_rate *fixed = &clk_hw->f; 1468 1469 clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name, 1470 parents[0], fixed->flags, fixed->fixed_rate); 1471 break; 1472 } 1473 default: 1474 clk = ERR_PTR(-EINVAL); 1475 } 1476 1477 return clk; 1478 } 1479 1480 static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate) 1481 { 1482 u32 val; 1483 1484 regmap_read(clk_regmap, reg, &val); 1485 1486 if (!(val & div_mask)) { 1487 val &= ~gate; 1488 val |= BIT(__ffs(div_mask)); 1489 } 1490 1491 regmap_update_bits(clk_regmap, reg, gate | div_mask, val); 1492 } 1493 1494 static void __init lpc32xx_clk_init(struct device_node *np) 1495 { 1496 unsigned int i; 1497 struct clk *clk_osc, *clk_32k; 1498 void __iomem *base = NULL; 1499 1500 /* Ensure that parent clocks are available and valid */ 1501 clk_32k = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL_32K].name); 1502 if (IS_ERR(clk_32k)) { 1503 pr_err("failed to find external 32KHz clock: %ld\n", 1504 PTR_ERR(clk_32k)); 1505 return; 1506 } 1507 if (clk_get_rate(clk_32k) != 32768) { 1508 pr_err("invalid clock rate of external 32KHz oscillator"); 1509 return; 1510 } 1511 1512 clk_osc = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL].name); 1513 if (IS_ERR(clk_osc)) { 1514 pr_err("failed to find external main oscillator clock: %ld\n", 1515 PTR_ERR(clk_osc)); 1516 return; 1517 } 1518 1519 base = of_iomap(np, 0); 1520 if (!base) { 1521 pr_err("failed to map system control block registers\n"); 1522 return; 1523 } 1524 1525 clk_regmap = regmap_init_mmio(NULL, base, &lpc32xx_scb_regmap_config); 1526 if (IS_ERR(clk_regmap)) { 1527 pr_err("failed to regmap system control block: %ld\n", 1528 PTR_ERR(clk_regmap)); 1529 iounmap(base); 1530 return; 1531 } 1532 1533 /* 1534 * Divider part of PWM and MS clocks requires a quirk to avoid 1535 * a misinterpretation of formally valid zero value in register 1536 * bitfield, which indicates another clock gate. Instead of 1537 * adding complexity to a gate clock ensure that zero value in 1538 * divider clock is never met in runtime. 1539 */ 1540 lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf0, BIT(0)); 1541 lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf00, BIT(2)); 1542 lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_MS_CTRL, 0xf, BIT(5) | BIT(9)); 1543 1544 for (i = 1; i < LPC32XX_CLK_MAX; i++) { 1545 clk[i] = lpc32xx_clk_register(i); 1546 if (IS_ERR(clk[i])) { 1547 pr_err("failed to register %s clock: %ld\n", 1548 clk_proto[i].name, PTR_ERR(clk[i])); 1549 clk[i] = NULL; 1550 } 1551 } 1552 1553 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 1554 1555 /* Set 48MHz rate of USB PLL clock */ 1556 clk_set_rate(clk[LPC32XX_CLK_USB_PLL], 48000000); 1557 1558 /* These two clocks must be always on independently on consumers */ 1559 clk_prepare_enable(clk[LPC32XX_CLK_ARM]); 1560 clk_prepare_enable(clk[LPC32XX_CLK_HCLK]); 1561 1562 /* Enable ARM VFP by default */ 1563 clk_prepare_enable(clk[LPC32XX_CLK_ARM_VFP]); 1564 1565 /* Disable enabled by default clocks for NAND MLC and SLC */ 1566 clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_SLC].hw0.clk.hw); 1567 clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_MLC].hw0.clk.hw); 1568 } 1569 CLK_OF_DECLARE(lpc32xx_clk, "nxp,lpc3220-clk", lpc32xx_clk_init); 1570 1571 static void __init lpc32xx_usb_clk_init(struct device_node *np) 1572 { 1573 unsigned int i; 1574 1575 usb_clk_vbase = of_iomap(np, 0); 1576 if (!usb_clk_vbase) { 1577 pr_err("failed to map address range\n"); 1578 return; 1579 } 1580 1581 for (i = 1; i < LPC32XX_USB_CLK_MAX; i++) { 1582 usb_clk[i] = lpc32xx_clk_register(i + LPC32XX_CLK_USB_OFFSET); 1583 if (IS_ERR(usb_clk[i])) { 1584 pr_err("failed to register %s clock: %ld\n", 1585 clk_proto[i].name, PTR_ERR(usb_clk[i])); 1586 usb_clk[i] = NULL; 1587 } 1588 } 1589 1590 of_clk_add_provider(np, of_clk_src_onecell_get, &usb_clk_data); 1591 } 1592 CLK_OF_DECLARE(lpc32xx_usb_clk, "nxp,lpc3220-usb-clk", lpc32xx_usb_clk_init); 1593