1 /*
2  * Clk driver for NXP LPC18xx/LPC43xx Clock Control Unit (CCU)
3  *
4  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2. This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/kernel.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 
19 #include <dt-bindings/clock/lpc18xx-ccu.h>
20 
21 /* Bit defines for CCU branch configuration register */
22 #define LPC18XX_CCU_RUN		BIT(0)
23 #define LPC18XX_CCU_AUTO	BIT(1)
24 #define LPC18XX_CCU_DIV		BIT(5)
25 #define LPC18XX_CCU_DIVSTAT	BIT(27)
26 
27 /* CCU branch feature bits */
28 #define CCU_BRANCH_IS_BUS	BIT(0)
29 #define CCU_BRANCH_HAVE_DIV2	BIT(1)
30 
31 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
32 
33 struct lpc18xx_branch_clk_data {
34 	const char **name;
35 	int num;
36 };
37 
38 struct lpc18xx_clk_branch {
39 	const char *base_name;
40 	const char *name;
41 	u16 offset;
42 	u16 flags;
43 	struct clk *clk;
44 	struct clk_gate gate;
45 };
46 
47 static struct lpc18xx_clk_branch clk_branches[] = {
48 	{"base_apb3_clk", "apb3_bus",		CLK_APB3_BUS,		CCU_BRANCH_IS_BUS},
49 	{"base_apb3_clk", "apb3_i2c1",		CLK_APB3_I2C1,		0},
50 	{"base_apb3_clk", "apb3_dac",		CLK_APB3_DAC,		0},
51 	{"base_apb3_clk", "apb3_adc0",		CLK_APB3_ADC0,		0},
52 	{"base_apb3_clk", "apb3_adc1",		CLK_APB3_ADC1,		0},
53 	{"base_apb3_clk", "apb3_can0",		CLK_APB3_CAN0,		0},
54 
55 	{"base_apb1_clk", "apb1_bus",		CLK_APB1_BUS,		CCU_BRANCH_IS_BUS},
56 	{"base_apb1_clk", "apb1_mc_pwm",	CLK_APB1_MOTOCON_PWM,	0},
57 	{"base_apb1_clk", "apb1_i2c0",		CLK_APB1_I2C0,		0},
58 	{"base_apb1_clk", "apb1_i2s",		CLK_APB1_I2S,		0},
59 	{"base_apb1_clk", "apb1_can1",		CLK_APB1_CAN1,		0},
60 
61 	{"base_spifi_clk", "spifi",		CLK_SPIFI,		0},
62 
63 	{"base_cpu_clk", "cpu_bus",		CLK_CPU_BUS,		CCU_BRANCH_IS_BUS},
64 	{"base_cpu_clk", "cpu_spifi",		CLK_CPU_SPIFI,		0},
65 	{"base_cpu_clk", "cpu_gpio",		CLK_CPU_GPIO,		0},
66 	{"base_cpu_clk", "cpu_lcd",		CLK_CPU_LCD,		0},
67 	{"base_cpu_clk", "cpu_ethernet",	CLK_CPU_ETHERNET,	0},
68 	{"base_cpu_clk", "cpu_usb0",		CLK_CPU_USB0,		0},
69 	{"base_cpu_clk", "cpu_emc",		CLK_CPU_EMC,		0},
70 	{"base_cpu_clk", "cpu_sdio",		CLK_CPU_SDIO,		0},
71 	{"base_cpu_clk", "cpu_dma",		CLK_CPU_DMA,		0},
72 	{"base_cpu_clk", "cpu_core",		CLK_CPU_CORE,		0},
73 	{"base_cpu_clk", "cpu_sct",		CLK_CPU_SCT,		0},
74 	{"base_cpu_clk", "cpu_usb1",		CLK_CPU_USB1,		0},
75 	{"base_cpu_clk", "cpu_emcdiv",		CLK_CPU_EMCDIV,		CCU_BRANCH_HAVE_DIV2},
76 	{"base_cpu_clk", "cpu_flasha",		CLK_CPU_FLASHA,		CCU_BRANCH_HAVE_DIV2},
77 	{"base_cpu_clk", "cpu_flashb",		CLK_CPU_FLASHB,		CCU_BRANCH_HAVE_DIV2},
78 	{"base_cpu_clk", "cpu_m0app",		CLK_CPU_M0APP,		CCU_BRANCH_HAVE_DIV2},
79 	{"base_cpu_clk", "cpu_adchs",		CLK_CPU_ADCHS,		CCU_BRANCH_HAVE_DIV2},
80 	{"base_cpu_clk", "cpu_eeprom",		CLK_CPU_EEPROM,		CCU_BRANCH_HAVE_DIV2},
81 	{"base_cpu_clk", "cpu_wwdt",		CLK_CPU_WWDT,		0},
82 	{"base_cpu_clk", "cpu_uart0",		CLK_CPU_UART0,		0},
83 	{"base_cpu_clk", "cpu_uart1",		CLK_CPU_UART1,		0},
84 	{"base_cpu_clk", "cpu_ssp0",		CLK_CPU_SSP0,		0},
85 	{"base_cpu_clk", "cpu_timer0",		CLK_CPU_TIMER0,		0},
86 	{"base_cpu_clk", "cpu_timer1",		CLK_CPU_TIMER1,		0},
87 	{"base_cpu_clk", "cpu_scu",		CLK_CPU_SCU,		0},
88 	{"base_cpu_clk", "cpu_creg",		CLK_CPU_CREG,		0},
89 	{"base_cpu_clk", "cpu_ritimer",		CLK_CPU_RITIMER,	0},
90 	{"base_cpu_clk", "cpu_uart2",		CLK_CPU_UART2,		0},
91 	{"base_cpu_clk", "cpu_uart3",		CLK_CPU_UART3,		0},
92 	{"base_cpu_clk", "cpu_timer2",		CLK_CPU_TIMER2,		0},
93 	{"base_cpu_clk", "cpu_timer3",		CLK_CPU_TIMER3,		0},
94 	{"base_cpu_clk", "cpu_ssp1",		CLK_CPU_SSP1,		0},
95 	{"base_cpu_clk", "cpu_qei",		CLK_CPU_QEI,		0},
96 
97 	{"base_periph_clk", "periph_bus",	CLK_PERIPH_BUS,		CCU_BRANCH_IS_BUS},
98 	{"base_periph_clk", "periph_core",	CLK_PERIPH_CORE,	0},
99 	{"base_periph_clk", "periph_sgpio",	CLK_PERIPH_SGPIO,	0},
100 
101 	{"base_usb0_clk",  "usb0",		CLK_USB0,		0},
102 	{"base_usb1_clk",  "usb1",		CLK_USB1,		0},
103 	{"base_spi_clk",   "spi",		CLK_SPI,		0},
104 	{"base_adchs_clk", "adchs",		CLK_ADCHS,		0},
105 
106 	{"base_audio_clk", "audio",		CLK_AUDIO,		0},
107 	{"base_uart3_clk", "apb2_uart3",	CLK_APB2_UART3,		0},
108 	{"base_uart2_clk", "apb2_uart2",	CLK_APB2_UART2,		0},
109 	{"base_uart1_clk", "apb0_uart1",	CLK_APB0_UART1,		0},
110 	{"base_uart0_clk", "apb0_uart0",	CLK_APB0_UART0,		0},
111 	{"base_ssp1_clk",  "apb2_ssp1",		CLK_APB2_SSP1,		0},
112 	{"base_ssp0_clk",  "apb0_ssp0",		CLK_APB0_SSP0,		0},
113 	{"base_sdio_clk",  "sdio",		CLK_SDIO,		0},
114 };
115 
116 static struct clk *lpc18xx_ccu_branch_clk_get(struct of_phandle_args *clkspec,
117 					      void *data)
118 {
119 	struct lpc18xx_branch_clk_data *clk_data = data;
120 	unsigned int offset = clkspec->args[0];
121 	int i, j;
122 
123 	for (i = 0; i < ARRAY_SIZE(clk_branches); i++) {
124 		if (clk_branches[i].offset != offset)
125 			continue;
126 
127 		for (j = 0; j < clk_data->num; j++) {
128 			if (!strcmp(clk_branches[i].base_name, clk_data->name[j]))
129 				return clk_branches[i].clk;
130 		}
131 	}
132 
133 	pr_err("%s: invalid clock offset %d\n", __func__, offset);
134 
135 	return ERR_PTR(-EINVAL);
136 }
137 
138 static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
139 {
140 	struct clk_gate *gate = to_clk_gate(hw);
141 	u32 val;
142 
143 	/*
144 	 * Divider field is write only, so divider stat field must
145 	 * be read so divider field can be set accordingly.
146 	 */
147 	val = clk_readl(gate->reg);
148 	if (val & LPC18XX_CCU_DIVSTAT)
149 		val |= LPC18XX_CCU_DIV;
150 
151 	if (enable) {
152 		val |= LPC18XX_CCU_RUN;
153 	} else {
154 		/*
155 		 * To safely disable a branch clock a squence of two separate
156 		 * writes must be used. First write should set the AUTO bit
157 		 * and the next write should clear the RUN bit.
158 		 */
159 		val |= LPC18XX_CCU_AUTO;
160 		clk_writel(val, gate->reg);
161 
162 		val &= ~LPC18XX_CCU_RUN;
163 	}
164 
165 	clk_writel(val, gate->reg);
166 
167 	return 0;
168 }
169 
170 static int lpc18xx_ccu_gate_enable(struct clk_hw *hw)
171 {
172 	return lpc18xx_ccu_gate_endisable(hw, true);
173 }
174 
175 static void lpc18xx_ccu_gate_disable(struct clk_hw *hw)
176 {
177 	lpc18xx_ccu_gate_endisable(hw, false);
178 }
179 
180 static int lpc18xx_ccu_gate_is_enabled(struct clk_hw *hw)
181 {
182 	struct clk_gate *gate = to_clk_gate(hw);
183 
184 	return clk_readl(gate->reg) & LPC18XX_CCU_RUN;
185 }
186 
187 static const struct clk_ops lpc18xx_ccu_gate_ops = {
188 	.enable		= lpc18xx_ccu_gate_enable,
189 	.disable	= lpc18xx_ccu_gate_disable,
190 	.is_enabled	= lpc18xx_ccu_gate_is_enabled,
191 };
192 
193 static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *branch,
194 						 void __iomem *reg_base,
195 						 const char *parent)
196 {
197 	const struct clk_ops *div_ops = NULL;
198 	struct clk_divider *div = NULL;
199 	struct clk_hw *div_hw = NULL;
200 
201 	if (branch->flags & CCU_BRANCH_HAVE_DIV2) {
202 		div = kzalloc(sizeof(*div), GFP_KERNEL);
203 		if (!div)
204 			return;
205 
206 		div->reg = branch->offset + reg_base;
207 		div->flags = CLK_DIVIDER_READ_ONLY;
208 		div->shift = 27;
209 		div->width = 1;
210 
211 		div_hw = &div->hw;
212 		div_ops = &clk_divider_ops;
213 	}
214 
215 	branch->gate.reg = branch->offset + reg_base;
216 	branch->gate.bit_idx = 0;
217 
218 	branch->clk = clk_register_composite(NULL, branch->name, &parent, 1,
219 					     NULL, NULL,
220 					     div_hw, div_ops,
221 					     &branch->gate.hw, &lpc18xx_ccu_gate_ops, 0);
222 	if (IS_ERR(branch->clk)) {
223 		kfree(div);
224 		pr_warn("%s: failed to register %s\n", __func__, branch->name);
225 		return;
226 	}
227 
228 	/* Grab essential branch clocks for CPU and SDRAM */
229 	switch (branch->offset) {
230 	case CLK_CPU_EMC:
231 	case CLK_CPU_CORE:
232 	case CLK_CPU_CREG:
233 	case CLK_CPU_EMCDIV:
234 		clk_prepare_enable(branch->clk);
235 	}
236 }
237 
238 static void lpc18xx_ccu_register_branch_clks(void __iomem *reg_base,
239 					     const char *base_name)
240 {
241 	const char *parent = base_name;
242 	int i;
243 
244 	for (i = 0; i < ARRAY_SIZE(clk_branches); i++) {
245 		if (strcmp(clk_branches[i].base_name, base_name))
246 			continue;
247 
248 		lpc18xx_ccu_register_branch_gate_div(&clk_branches[i], reg_base,
249 						     parent);
250 
251 		if (clk_branches[i].flags & CCU_BRANCH_IS_BUS)
252 			parent = clk_branches[i].name;
253 	}
254 }
255 
256 static void __init lpc18xx_ccu_init(struct device_node *np)
257 {
258 	struct lpc18xx_branch_clk_data *clk_data;
259 	void __iomem *reg_base;
260 	int i, ret;
261 
262 	reg_base = of_iomap(np, 0);
263 	if (!reg_base) {
264 		pr_warn("%s: failed to map address range\n", __func__);
265 		return;
266 	}
267 
268 	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
269 	if (!clk_data)
270 		return;
271 
272 	clk_data->num = of_property_count_strings(np, "clock-names");
273 	clk_data->name = kcalloc(clk_data->num, sizeof(char *), GFP_KERNEL);
274 	if (!clk_data->name) {
275 		kfree(clk_data);
276 		return;
277 	}
278 
279 	for (i = 0; i < clk_data->num; i++) {
280 		ret = of_property_read_string_index(np, "clock-names", i,
281 						    &clk_data->name[i]);
282 		if (ret) {
283 			pr_warn("%s: failed to get clock name at idx %d\n",
284 				__func__, i);
285 			continue;
286 		}
287 
288 		lpc18xx_ccu_register_branch_clks(reg_base, clk_data->name[i]);
289 	}
290 
291 	of_clk_add_provider(np, lpc18xx_ccu_branch_clk_get, clk_data);
292 }
293 CLK_OF_DECLARE(lpc18xx_ccu, "nxp,lpc1850-ccu", lpc18xx_ccu_init);
294