1 /*
2  * Clk driver for NXP LPC18xx/LPC43xx Clock Control Unit (CCU)
3  *
4  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2. This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/kernel.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 
19 #include <dt-bindings/clock/lpc18xx-ccu.h>
20 
21 /* Bit defines for CCU branch configuration register */
22 #define LPC18XX_CCU_RUN		BIT(0)
23 #define LPC18XX_CCU_AUTO	BIT(1)
24 #define LPC18XX_CCU_DIV		BIT(5)
25 #define LPC18XX_CCU_DIVSTAT	BIT(27)
26 
27 /* CCU branch feature bits */
28 #define CCU_BRANCH_IS_BUS	BIT(0)
29 #define CCU_BRANCH_HAVE_DIV2	BIT(1)
30 
31 struct lpc18xx_branch_clk_data {
32 	const char **name;
33 	int num;
34 };
35 
36 struct lpc18xx_clk_branch {
37 	const char *base_name;
38 	const char *name;
39 	u16 offset;
40 	u16 flags;
41 	struct clk *clk;
42 	struct clk_gate gate;
43 };
44 
45 static struct lpc18xx_clk_branch clk_branches[] = {
46 	{"base_apb3_clk", "apb3_bus",		CLK_APB3_BUS,		CCU_BRANCH_IS_BUS},
47 	{"base_apb3_clk", "apb3_i2c1",		CLK_APB3_I2C1,		0},
48 	{"base_apb3_clk", "apb3_dac",		CLK_APB3_DAC,		0},
49 	{"base_apb3_clk", "apb3_adc0",		CLK_APB3_ADC0,		0},
50 	{"base_apb3_clk", "apb3_adc1",		CLK_APB3_ADC1,		0},
51 	{"base_apb3_clk", "apb3_can0",		CLK_APB3_CAN0,		0},
52 
53 	{"base_apb1_clk", "apb1_bus",		CLK_APB1_BUS,		CCU_BRANCH_IS_BUS},
54 	{"base_apb1_clk", "apb1_mc_pwm",	CLK_APB1_MOTOCON_PWM,	0},
55 	{"base_apb1_clk", "apb1_i2c0",		CLK_APB1_I2C0,		0},
56 	{"base_apb1_clk", "apb1_i2s",		CLK_APB1_I2S,		0},
57 	{"base_apb1_clk", "apb1_can1",		CLK_APB1_CAN1,		0},
58 
59 	{"base_spifi_clk", "spifi",		CLK_SPIFI,		0},
60 
61 	{"base_cpu_clk", "cpu_bus",		CLK_CPU_BUS,		CCU_BRANCH_IS_BUS},
62 	{"base_cpu_clk", "cpu_spifi",		CLK_CPU_SPIFI,		0},
63 	{"base_cpu_clk", "cpu_gpio",		CLK_CPU_GPIO,		0},
64 	{"base_cpu_clk", "cpu_lcd",		CLK_CPU_LCD,		0},
65 	{"base_cpu_clk", "cpu_ethernet",	CLK_CPU_ETHERNET,	0},
66 	{"base_cpu_clk", "cpu_usb0",		CLK_CPU_USB0,		0},
67 	{"base_cpu_clk", "cpu_emc",		CLK_CPU_EMC,		0},
68 	{"base_cpu_clk", "cpu_sdio",		CLK_CPU_SDIO,		0},
69 	{"base_cpu_clk", "cpu_dma",		CLK_CPU_DMA,		0},
70 	{"base_cpu_clk", "cpu_core",		CLK_CPU_CORE,		0},
71 	{"base_cpu_clk", "cpu_sct",		CLK_CPU_SCT,		0},
72 	{"base_cpu_clk", "cpu_usb1",		CLK_CPU_USB1,		0},
73 	{"base_cpu_clk", "cpu_emcdiv",		CLK_CPU_EMCDIV,		CCU_BRANCH_HAVE_DIV2},
74 	{"base_cpu_clk", "cpu_flasha",		CLK_CPU_FLASHA,		CCU_BRANCH_HAVE_DIV2},
75 	{"base_cpu_clk", "cpu_flashb",		CLK_CPU_FLASHB,		CCU_BRANCH_HAVE_DIV2},
76 	{"base_cpu_clk", "cpu_m0app",		CLK_CPU_M0APP,		CCU_BRANCH_HAVE_DIV2},
77 	{"base_cpu_clk", "cpu_adchs",		CLK_CPU_ADCHS,		CCU_BRANCH_HAVE_DIV2},
78 	{"base_cpu_clk", "cpu_eeprom",		CLK_CPU_EEPROM,		CCU_BRANCH_HAVE_DIV2},
79 	{"base_cpu_clk", "cpu_wwdt",		CLK_CPU_WWDT,		0},
80 	{"base_cpu_clk", "cpu_uart0",		CLK_CPU_UART0,		0},
81 	{"base_cpu_clk", "cpu_uart1",		CLK_CPU_UART1,		0},
82 	{"base_cpu_clk", "cpu_ssp0",		CLK_CPU_SSP0,		0},
83 	{"base_cpu_clk", "cpu_timer0",		CLK_CPU_TIMER0,		0},
84 	{"base_cpu_clk", "cpu_timer1",		CLK_CPU_TIMER1,		0},
85 	{"base_cpu_clk", "cpu_scu",		CLK_CPU_SCU,		0},
86 	{"base_cpu_clk", "cpu_creg",		CLK_CPU_CREG,		0},
87 	{"base_cpu_clk", "cpu_ritimer",		CLK_CPU_RITIMER,	0},
88 	{"base_cpu_clk", "cpu_uart2",		CLK_CPU_UART2,		0},
89 	{"base_cpu_clk", "cpu_uart3",		CLK_CPU_UART3,		0},
90 	{"base_cpu_clk", "cpu_timer2",		CLK_CPU_TIMER2,		0},
91 	{"base_cpu_clk", "cpu_timer3",		CLK_CPU_TIMER3,		0},
92 	{"base_cpu_clk", "cpu_ssp1",		CLK_CPU_SSP1,		0},
93 	{"base_cpu_clk", "cpu_qei",		CLK_CPU_QEI,		0},
94 
95 	{"base_periph_clk", "periph_bus",	CLK_PERIPH_BUS,		CCU_BRANCH_IS_BUS},
96 	{"base_periph_clk", "periph_core",	CLK_PERIPH_CORE,	0},
97 	{"base_periph_clk", "periph_sgpio",	CLK_PERIPH_SGPIO,	0},
98 
99 	{"base_usb0_clk",  "usb0",		CLK_USB0,		0},
100 	{"base_usb1_clk",  "usb1",		CLK_USB1,		0},
101 	{"base_spi_clk",   "spi",		CLK_SPI,		0},
102 	{"base_adchs_clk", "adchs",		CLK_ADCHS,		0},
103 
104 	{"base_audio_clk", "audio",		CLK_AUDIO,		0},
105 	{"base_uart3_clk", "apb2_uart3",	CLK_APB2_UART3,		0},
106 	{"base_uart2_clk", "apb2_uart2",	CLK_APB2_UART2,		0},
107 	{"base_uart1_clk", "apb0_uart1",	CLK_APB0_UART1,		0},
108 	{"base_uart0_clk", "apb0_uart0",	CLK_APB0_UART0,		0},
109 	{"base_ssp1_clk",  "apb2_ssp1",		CLK_APB2_SSP1,		0},
110 	{"base_ssp0_clk",  "apb0_ssp0",		CLK_APB0_SSP0,		0},
111 	{"base_sdio_clk",  "sdio",		CLK_SDIO,		0},
112 };
113 
114 static struct clk *lpc18xx_ccu_branch_clk_get(struct of_phandle_args *clkspec,
115 					      void *data)
116 {
117 	struct lpc18xx_branch_clk_data *clk_data = data;
118 	unsigned int offset = clkspec->args[0];
119 	int i, j;
120 
121 	for (i = 0; i < ARRAY_SIZE(clk_branches); i++) {
122 		if (clk_branches[i].offset != offset)
123 			continue;
124 
125 		for (j = 0; j < clk_data->num; j++) {
126 			if (!strcmp(clk_branches[i].base_name, clk_data->name[j]))
127 				return clk_branches[i].clk;
128 		}
129 	}
130 
131 	pr_err("%s: invalid clock offset %d\n", __func__, offset);
132 
133 	return ERR_PTR(-EINVAL);
134 }
135 
136 static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
137 {
138 	struct clk_gate *gate = to_clk_gate(hw);
139 	u32 val;
140 
141 	/*
142 	 * Divider field is write only, so divider stat field must
143 	 * be read so divider field can be set accordingly.
144 	 */
145 	val = clk_readl(gate->reg);
146 	if (val & LPC18XX_CCU_DIVSTAT)
147 		val |= LPC18XX_CCU_DIV;
148 
149 	if (enable) {
150 		val |= LPC18XX_CCU_RUN;
151 	} else {
152 		/*
153 		 * To safely disable a branch clock a squence of two separate
154 		 * writes must be used. First write should set the AUTO bit
155 		 * and the next write should clear the RUN bit.
156 		 */
157 		val |= LPC18XX_CCU_AUTO;
158 		clk_writel(val, gate->reg);
159 
160 		val &= ~LPC18XX_CCU_RUN;
161 	}
162 
163 	clk_writel(val, gate->reg);
164 
165 	return 0;
166 }
167 
168 static int lpc18xx_ccu_gate_enable(struct clk_hw *hw)
169 {
170 	return lpc18xx_ccu_gate_endisable(hw, true);
171 }
172 
173 static void lpc18xx_ccu_gate_disable(struct clk_hw *hw)
174 {
175 	lpc18xx_ccu_gate_endisable(hw, false);
176 }
177 
178 static int lpc18xx_ccu_gate_is_enabled(struct clk_hw *hw)
179 {
180 	const struct clk_hw *parent;
181 
182 	/*
183 	 * The branch clock registers are only accessible
184 	 * if the base (parent) clock is enabled. Register
185 	 * access with a disabled base clock will hang the
186 	 * system.
187 	 */
188 	parent = clk_hw_get_parent(hw);
189 	if (!parent)
190 		return 0;
191 
192 	if (!clk_hw_is_enabled(parent))
193 		return 0;
194 
195 	return clk_gate_ops.is_enabled(hw);
196 }
197 
198 static const struct clk_ops lpc18xx_ccu_gate_ops = {
199 	.enable		= lpc18xx_ccu_gate_enable,
200 	.disable	= lpc18xx_ccu_gate_disable,
201 	.is_enabled	= lpc18xx_ccu_gate_is_enabled,
202 };
203 
204 static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *branch,
205 						 void __iomem *reg_base,
206 						 const char *parent)
207 {
208 	const struct clk_ops *div_ops = NULL;
209 	struct clk_divider *div = NULL;
210 	struct clk_hw *div_hw = NULL;
211 
212 	if (branch->flags & CCU_BRANCH_HAVE_DIV2) {
213 		div = kzalloc(sizeof(*div), GFP_KERNEL);
214 		if (!div)
215 			return;
216 
217 		div->reg = branch->offset + reg_base;
218 		div->flags = CLK_DIVIDER_READ_ONLY;
219 		div->shift = 27;
220 		div->width = 1;
221 
222 		div_hw = &div->hw;
223 		div_ops = &clk_divider_ro_ops;
224 	}
225 
226 	branch->gate.reg = branch->offset + reg_base;
227 	branch->gate.bit_idx = 0;
228 
229 	branch->clk = clk_register_composite(NULL, branch->name, &parent, 1,
230 					     NULL, NULL,
231 					     div_hw, div_ops,
232 					     &branch->gate.hw, &lpc18xx_ccu_gate_ops, 0);
233 	if (IS_ERR(branch->clk)) {
234 		kfree(div);
235 		pr_warn("%s: failed to register %s\n", __func__, branch->name);
236 		return;
237 	}
238 
239 	/* Grab essential branch clocks for CPU and SDRAM */
240 	switch (branch->offset) {
241 	case CLK_CPU_EMC:
242 	case CLK_CPU_CORE:
243 	case CLK_CPU_CREG:
244 	case CLK_CPU_EMCDIV:
245 		clk_prepare_enable(branch->clk);
246 	}
247 }
248 
249 static void lpc18xx_ccu_register_branch_clks(void __iomem *reg_base,
250 					     const char *base_name)
251 {
252 	const char *parent = base_name;
253 	int i;
254 
255 	for (i = 0; i < ARRAY_SIZE(clk_branches); i++) {
256 		if (strcmp(clk_branches[i].base_name, base_name))
257 			continue;
258 
259 		lpc18xx_ccu_register_branch_gate_div(&clk_branches[i], reg_base,
260 						     parent);
261 
262 		if (clk_branches[i].flags & CCU_BRANCH_IS_BUS)
263 			parent = clk_branches[i].name;
264 	}
265 }
266 
267 static void __init lpc18xx_ccu_init(struct device_node *np)
268 {
269 	struct lpc18xx_branch_clk_data *clk_data;
270 	void __iomem *reg_base;
271 	int i, ret;
272 
273 	reg_base = of_iomap(np, 0);
274 	if (!reg_base) {
275 		pr_warn("%s: failed to map address range\n", __func__);
276 		return;
277 	}
278 
279 	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
280 	if (!clk_data) {
281 		iounmap(reg_base);
282 		return;
283 	}
284 
285 	clk_data->num = of_property_count_strings(np, "clock-names");
286 	clk_data->name = kcalloc(clk_data->num, sizeof(char *), GFP_KERNEL);
287 	if (!clk_data->name) {
288 		iounmap(reg_base);
289 		kfree(clk_data);
290 		return;
291 	}
292 
293 	for (i = 0; i < clk_data->num; i++) {
294 		ret = of_property_read_string_index(np, "clock-names", i,
295 						    &clk_data->name[i]);
296 		if (ret) {
297 			pr_warn("%s: failed to get clock name at idx %d\n",
298 				__func__, i);
299 			continue;
300 		}
301 
302 		lpc18xx_ccu_register_branch_clks(reg_base, clk_data->name[i]);
303 	}
304 
305 	of_clk_add_provider(np, lpc18xx_ccu_branch_clk_get, clk_data);
306 }
307 CLK_OF_DECLARE(lpc18xx_ccu, "nxp,lpc1850-ccu", lpc18xx_ccu_init);
308