1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/err.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include "clk.h" 20 21 static void __iomem *clkctrl; 22 static void __iomem *digctrl; 23 24 #define CLKCTRL clkctrl 25 #define DIGCTRL digctrl 26 27 #define PLLCTRL0 (CLKCTRL + 0x0000) 28 #define CPU (CLKCTRL + 0x0020) 29 #define HBUS (CLKCTRL + 0x0030) 30 #define XBUS (CLKCTRL + 0x0040) 31 #define XTAL (CLKCTRL + 0x0050) 32 #define PIX (CLKCTRL + 0x0060) 33 #define SSP (CLKCTRL + 0x0070) 34 #define GPMI (CLKCTRL + 0x0080) 35 #define SPDIF (CLKCTRL + 0x0090) 36 #define EMI (CLKCTRL + 0x00a0) 37 #define SAIF (CLKCTRL + 0x00c0) 38 #define TV (CLKCTRL + 0x00d0) 39 #define ETM (CLKCTRL + 0x00e0) 40 #define FRAC (CLKCTRL + 0x00f0) 41 #define CLKSEQ (CLKCTRL + 0x0110) 42 43 #define BP_CPU_INTERRUPT_WAIT 12 44 #define BP_CLKSEQ_BYPASS_SAIF 0 45 #define BP_CLKSEQ_BYPASS_SSP 5 46 #define BP_SAIF_DIV_FRAC_EN 16 47 #define BP_FRAC_IOFRAC 24 48 49 static void __init clk_misc_init(void) 50 { 51 u32 val; 52 53 /* Gate off cpu clock in WFI for power saving */ 54 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); 55 56 /* Clear BYPASS for SAIF */ 57 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR); 58 59 /* SAIF has to use frac div for functional operation */ 60 val = readl_relaxed(SAIF); 61 val |= 1 << BP_SAIF_DIV_FRAC_EN; 62 writel_relaxed(val, SAIF); 63 64 /* 65 * Source ssp clock from ref_io than ref_xtal, 66 * as ref_xtal only provides 24 MHz as maximum. 67 */ 68 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR); 69 70 /* 71 * 480 MHz seems too high to be ssp clock source directly, 72 * so set frac to get a 288 MHz ref_io. 73 */ 74 writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR); 75 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); 76 } 77 78 static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; 79 static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; 80 static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; 81 static const char *sel_io[] __initconst = { "ref_io", "ref_xtal", }; 82 static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; 83 static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; 84 85 enum imx23_clk { 86 ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel, 87 lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll, 88 cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll, 89 emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div, 90 clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif, 91 lcdif, etm, usb, usb_phy, 92 clk_max 93 }; 94 95 static struct clk *clks[clk_max]; 96 static struct clk_onecell_data clk_data; 97 98 static enum imx23_clk clks_init_on[] __initdata = { 99 cpu, hbus, xbus, emi, uart, 100 }; 101 102 int __init mx23_clocks_init(void) 103 { 104 struct device_node *np; 105 u32 i; 106 107 np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); 108 digctrl = of_iomap(np, 0); 109 WARN_ON(!digctrl); 110 111 np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl"); 112 clkctrl = of_iomap(np, 0); 113 WARN_ON(!clkctrl); 114 115 clk_misc_init(); 116 117 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); 118 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); 119 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); 120 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); 121 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); 122 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); 123 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); 124 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); 125 clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); 126 clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io)); 127 clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels)); 128 clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); 129 clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); 130 clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); 131 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); 132 clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29); 133 clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); 134 clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29); 135 clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29); 136 clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); 137 clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); 138 clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); 139 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29); 140 clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29); 141 clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); 142 clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); 143 clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16); 144 clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4); 145 clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); 146 clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28); 147 clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); 148 clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30); 149 clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); 150 clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31); 151 clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); 152 clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); 153 clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); 154 clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31); 155 clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31); 156 clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); 157 clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2); 158 clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock); 159 160 for (i = 0; i < ARRAY_SIZE(clks); i++) 161 if (IS_ERR(clks[i])) { 162 pr_err("i.MX23 clk %d: register failed with %ld\n", 163 i, PTR_ERR(clks[i])); 164 return PTR_ERR(clks[i]); 165 } 166 167 clk_data.clks = clks; 168 clk_data.clk_num = ARRAY_SIZE(clks); 169 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 170 171 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 172 clk_prepare_enable(clks[clks_init_on[i]]); 173 174 return 0; 175 } 176