1 /* 2 * Marvell Dove SoC clocks 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Andrew Lunn <andrew@lunn.ch> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include "common.h" 20 #include "dove-divider.h" 21 22 /* 23 * Core Clocks 24 * 25 * Dove PLL sample-at-reset configuration 26 * 27 * SAR0[8:5] : CPU frequency 28 * 5 = 1000 MHz 29 * 6 = 933 MHz 30 * 7 = 933 MHz 31 * 8 = 800 MHz 32 * 9 = 800 MHz 33 * 10 = 800 MHz 34 * 11 = 1067 MHz 35 * 12 = 667 MHz 36 * 13 = 533 MHz 37 * 14 = 400 MHz 38 * 15 = 333 MHz 39 * others reserved. 40 * 41 * SAR0[11:9] : CPU to L2 Clock divider ratio 42 * 0 = (1/1) * CPU 43 * 2 = (1/2) * CPU 44 * 4 = (1/3) * CPU 45 * 6 = (1/4) * CPU 46 * others reserved. 47 * 48 * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio 49 * 0 = (1/1) * CPU 50 * 2 = (1/2) * CPU 51 * 3 = (2/5) * CPU 52 * 4 = (1/3) * CPU 53 * 6 = (1/4) * CPU 54 * 8 = (1/5) * CPU 55 * 10 = (1/6) * CPU 56 * 12 = (1/7) * CPU 57 * 14 = (1/8) * CPU 58 * 15 = (1/10) * CPU 59 * others reserved. 60 * 61 * SAR0[24:23] : TCLK frequency 62 * 0 = 166 MHz 63 * 1 = 125 MHz 64 * others reserved. 65 */ 66 67 #define SAR_DOVE_CPU_FREQ 5 68 #define SAR_DOVE_CPU_FREQ_MASK 0xf 69 #define SAR_DOVE_L2_RATIO 9 70 #define SAR_DOVE_L2_RATIO_MASK 0x7 71 #define SAR_DOVE_DDR_RATIO 12 72 #define SAR_DOVE_DDR_RATIO_MASK 0xf 73 #define SAR_DOVE_TCLK_FREQ 23 74 #define SAR_DOVE_TCLK_FREQ_MASK 0x3 75 76 enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR }; 77 78 static const struct coreclk_ratio dove_coreclk_ratios[] __initconst = { 79 { .id = DOVE_CPU_TO_L2, .name = "l2clk", }, 80 { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", } 81 }; 82 83 static const u32 dove_tclk_freqs[] __initconst = { 84 166666667, 85 125000000, 86 0, 0 87 }; 88 89 static u32 __init dove_get_tclk_freq(void __iomem *sar) 90 { 91 u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & 92 SAR_DOVE_TCLK_FREQ_MASK; 93 return dove_tclk_freqs[opt]; 94 } 95 96 static const u32 dove_cpu_freqs[] __initconst = { 97 0, 0, 0, 0, 0, 98 1000000000, 99 933333333, 933333333, 100 800000000, 800000000, 800000000, 101 1066666667, 102 666666667, 103 533333333, 104 400000000, 105 333333333 106 }; 107 108 static u32 __init dove_get_cpu_freq(void __iomem *sar) 109 { 110 u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & 111 SAR_DOVE_CPU_FREQ_MASK; 112 return dove_cpu_freqs[opt]; 113 } 114 115 static const int dove_cpu_l2_ratios[8][2] __initconst = { 116 { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 }, 117 { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 } 118 }; 119 120 static const int dove_cpu_ddr_ratios[16][2] __initconst = { 121 { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 }, 122 { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }, 123 { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 }, 124 { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 } 125 }; 126 127 static void __init dove_get_clk_ratio( 128 void __iomem *sar, int id, int *mult, int *div) 129 { 130 switch (id) { 131 case DOVE_CPU_TO_L2: 132 { 133 u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & 134 SAR_DOVE_L2_RATIO_MASK; 135 *mult = dove_cpu_l2_ratios[opt][0]; 136 *div = dove_cpu_l2_ratios[opt][1]; 137 break; 138 } 139 case DOVE_CPU_TO_DDR: 140 { 141 u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & 142 SAR_DOVE_DDR_RATIO_MASK; 143 *mult = dove_cpu_ddr_ratios[opt][0]; 144 *div = dove_cpu_ddr_ratios[opt][1]; 145 break; 146 } 147 } 148 } 149 150 static const struct coreclk_soc_desc dove_coreclks = { 151 .get_tclk_freq = dove_get_tclk_freq, 152 .get_cpu_freq = dove_get_cpu_freq, 153 .get_clk_ratio = dove_get_clk_ratio, 154 .ratios = dove_coreclk_ratios, 155 .num_ratios = ARRAY_SIZE(dove_coreclk_ratios), 156 }; 157 158 /* 159 * Clock Gating Control 160 */ 161 162 static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = { 163 { "usb0", NULL, 0, 0 }, 164 { "usb1", NULL, 1, 0 }, 165 { "ge", "gephy", 2, 0 }, 166 { "sata", NULL, 3, 0 }, 167 { "pex0", NULL, 4, 0 }, 168 { "pex1", NULL, 5, 0 }, 169 { "sdio0", NULL, 8, 0 }, 170 { "sdio1", NULL, 9, 0 }, 171 { "nand", NULL, 10, 0 }, 172 { "camera", NULL, 11, 0 }, 173 { "i2s0", NULL, 12, 0 }, 174 { "i2s1", NULL, 13, 0 }, 175 { "crypto", NULL, 15, 0 }, 176 { "ac97", NULL, 21, 0 }, 177 { "pdma", NULL, 22, 0 }, 178 { "xor0", NULL, 23, 0 }, 179 { "xor1", NULL, 24, 0 }, 180 { "gephy", NULL, 30, 0 }, 181 { } 182 }; 183 184 static void __init dove_clk_init(struct device_node *np) 185 { 186 struct device_node *cgnp = 187 of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock"); 188 struct device_node *ddnp = 189 of_find_compatible_node(NULL, NULL, "marvell,dove-divider-clock"); 190 191 mvebu_coreclk_setup(np, &dove_coreclks); 192 193 if (ddnp) 194 dove_divider_clk_init(ddnp); 195 196 if (cgnp) 197 mvebu_clk_gating_setup(cgnp, dove_gating_desc); 198 } 199 CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init); 200