1 /*
2  * Marvell Armada CP110 System Controller
3  *
4  * Copyright (C) 2016 Marvell
5  *
6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 
13 /*
14  * CP110 has 5 core clocks:
15  *
16  *  - APLL		(1 Ghz)
17  *    - PPv2 core	(1/3 APLL)
18  *    - EIP		(1/2 APLL)
19  *      - Core		(1/2 EIP)
20  *
21  *  - NAND clock, which is either:
22  *    - Equal to the core clock
23  *    - 2/5 APLL
24  *
25  * CP110 has 32 gatable clocks, for the various peripherals in the
26  * IP. They have fairly complicated parent/child relationships.
27  */
28 
29 #define pr_fmt(fmt) "cp110-system-controller: " fmt
30 
31 #include <linux/clk-provider.h>
32 #include <linux/mfd/syscon.h>
33 #include <linux/init.h>
34 #include <linux/of.h>
35 #include <linux/of_address.h>
36 #include <linux/platform_device.h>
37 #include <linux/regmap.h>
38 #include <linux/slab.h>
39 
40 #define CP110_PM_CLOCK_GATING_REG	0x220
41 #define CP110_NAND_FLASH_CLK_CTRL_REG	0x700
42 #define    NF_CLOCK_SEL_400_MASK	BIT(0)
43 
44 enum {
45 	CP110_CLK_TYPE_CORE,
46 	CP110_CLK_TYPE_GATABLE,
47 };
48 
49 #define CP110_MAX_CORE_CLOCKS		5
50 #define CP110_MAX_GATABLE_CLOCKS	32
51 
52 #define CP110_CLK_NUM \
53 	(CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS)
54 
55 #define CP110_CORE_APLL			0
56 #define CP110_CORE_PPV2			1
57 #define CP110_CORE_EIP			2
58 #define CP110_CORE_CORE			3
59 #define CP110_CORE_NAND			4
60 
61 /* A number of gatable clocks need special handling */
62 #define CP110_GATE_AUDIO		0
63 #define CP110_GATE_COMM_UNIT		1
64 #define CP110_GATE_NAND			2
65 #define CP110_GATE_PPV2			3
66 #define CP110_GATE_SDIO			4
67 #define CP110_GATE_XOR1			7
68 #define CP110_GATE_XOR0			8
69 #define CP110_GATE_PCIE_X1_0		11
70 #define CP110_GATE_PCIE_X1_1		12
71 #define CP110_GATE_PCIE_X4		13
72 #define CP110_GATE_PCIE_XOR		14
73 #define CP110_GATE_SATA			15
74 #define CP110_GATE_SATA_USB		16
75 #define CP110_GATE_MAIN			17
76 #define CP110_GATE_SDMMC		18
77 #define CP110_GATE_SLOW_IO		21
78 #define CP110_GATE_USB3H0		22
79 #define CP110_GATE_USB3H1		23
80 #define CP110_GATE_USB3DEV		24
81 #define CP110_GATE_EIP150		25
82 #define CP110_GATE_EIP197		26
83 
84 struct cp110_gate_clk {
85 	struct clk_hw hw;
86 	struct regmap *regmap;
87 	u8 bit_idx;
88 };
89 
90 #define to_cp110_gate_clk(hw) container_of(hw, struct cp110_gate_clk, hw)
91 
92 static int cp110_gate_enable(struct clk_hw *hw)
93 {
94 	struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
95 
96 	regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
97 			   BIT(gate->bit_idx), BIT(gate->bit_idx));
98 
99 	return 0;
100 }
101 
102 static void cp110_gate_disable(struct clk_hw *hw)
103 {
104 	struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
105 
106 	regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
107 			   BIT(gate->bit_idx), 0);
108 }
109 
110 static int cp110_gate_is_enabled(struct clk_hw *hw)
111 {
112 	struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
113 	u32 val;
114 
115 	regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val);
116 
117 	return val & BIT(gate->bit_idx);
118 }
119 
120 static const struct clk_ops cp110_gate_ops = {
121 	.enable = cp110_gate_enable,
122 	.disable = cp110_gate_disable,
123 	.is_enabled = cp110_gate_is_enabled,
124 };
125 
126 static struct clk_hw *cp110_register_gate(const char *name,
127 					  const char *parent_name,
128 					  struct regmap *regmap, u8 bit_idx)
129 {
130 	struct cp110_gate_clk *gate;
131 	struct clk_hw *hw;
132 	struct clk_init_data init;
133 	int ret;
134 
135 	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
136 	if (!gate)
137 		return ERR_PTR(-ENOMEM);
138 
139 	memset(&init, 0, sizeof(init));
140 
141 	init.name = name;
142 	init.ops = &cp110_gate_ops;
143 	init.parent_names = &parent_name;
144 	init.num_parents = 1;
145 
146 	gate->regmap = regmap;
147 	gate->bit_idx = bit_idx;
148 	gate->hw.init = &init;
149 
150 	hw = &gate->hw;
151 	ret = clk_hw_register(NULL, hw);
152 	if (ret) {
153 		kfree(gate);
154 		hw = ERR_PTR(ret);
155 	}
156 
157 	return hw;
158 }
159 
160 static void cp110_unregister_gate(struct clk_hw *hw)
161 {
162 	clk_hw_unregister(hw);
163 	kfree(to_cp110_gate_clk(hw));
164 }
165 
166 static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
167 				       void *data)
168 {
169 	struct clk_hw_onecell_data *clk_data = data;
170 	unsigned int type = clkspec->args[0];
171 	unsigned int idx = clkspec->args[1];
172 
173 	if (type == CP110_CLK_TYPE_CORE) {
174 		if (idx > CP110_MAX_CORE_CLOCKS)
175 			return ERR_PTR(-EINVAL);
176 		return clk_data->hws[idx];
177 	} else if (type == CP110_CLK_TYPE_GATABLE) {
178 		if (idx > CP110_MAX_GATABLE_CLOCKS)
179 			return ERR_PTR(-EINVAL);
180 		return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx];
181 	}
182 
183 	return ERR_PTR(-EINVAL);
184 }
185 
186 static int cp110_syscon_clk_probe(struct platform_device *pdev)
187 {
188 	struct regmap *regmap;
189 	struct device_node *np = pdev->dev.of_node;
190 	const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name;
191 	struct clk_hw_onecell_data *cp110_clk_data;
192 	struct clk_hw *hw, **cp110_clks;
193 	u32 nand_clk_ctrl;
194 	int i, ret;
195 
196 	regmap = syscon_node_to_regmap(np);
197 	if (IS_ERR(regmap))
198 		return PTR_ERR(regmap);
199 
200 	ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG,
201 			  &nand_clk_ctrl);
202 	if (ret)
203 		return ret;
204 
205 	cp110_clk_data = devm_kzalloc(&pdev->dev, sizeof(*cp110_clk_data) +
206 				      sizeof(struct clk_hw *) * CP110_CLK_NUM,
207 				      GFP_KERNEL);
208 	if (!cp110_clk_data)
209 		return -ENOMEM;
210 
211 	cp110_clks = cp110_clk_data->hws;
212 	cp110_clk_data->num = CP110_CLK_NUM;
213 
214 	/* Register the APLL which is the root of the hw tree */
215 	of_property_read_string_index(np, "core-clock-output-names",
216 				      CP110_CORE_APLL, &apll_name);
217 	hw = clk_hw_register_fixed_rate(NULL, apll_name, NULL, 0,
218 					1000 * 1000 * 1000);
219 	if (IS_ERR(hw)) {
220 		ret = PTR_ERR(hw);
221 		goto fail0;
222 	}
223 
224 	cp110_clks[CP110_CORE_APLL] = hw;
225 
226 	/* PPv2 is APLL/3 */
227 	of_property_read_string_index(np, "core-clock-output-names",
228 				      CP110_CORE_PPV2, &ppv2_name);
229 	hw = clk_hw_register_fixed_factor(NULL, ppv2_name, apll_name, 0, 1, 3);
230 	if (IS_ERR(hw)) {
231 		ret = PTR_ERR(hw);
232 		goto fail1;
233 	}
234 
235 	cp110_clks[CP110_CORE_PPV2] = hw;
236 
237 	/* EIP clock is APLL/2 */
238 	of_property_read_string_index(np, "core-clock-output-names",
239 				      CP110_CORE_EIP, &eip_name);
240 	hw = clk_hw_register_fixed_factor(NULL, eip_name, apll_name, 0, 1, 2);
241 	if (IS_ERR(hw)) {
242 		ret = PTR_ERR(hw);
243 		goto fail2;
244 	}
245 
246 	cp110_clks[CP110_CORE_EIP] = hw;
247 
248 	/* Core clock is EIP/2 */
249 	of_property_read_string_index(np, "core-clock-output-names",
250 				      CP110_CORE_CORE, &core_name);
251 	hw = clk_hw_register_fixed_factor(NULL, core_name, eip_name, 0, 1, 2);
252 	if (IS_ERR(hw)) {
253 		ret = PTR_ERR(hw);
254 		goto fail3;
255 	}
256 
257 	cp110_clks[CP110_CORE_CORE] = hw;
258 
259 	/* NAND can be either APLL/2.5 or core clock */
260 	of_property_read_string_index(np, "core-clock-output-names",
261 				      CP110_CORE_NAND, &nand_name);
262 	if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
263 		hw = clk_hw_register_fixed_factor(NULL, nand_name,
264 						   apll_name, 0, 2, 5);
265 	else
266 		hw = clk_hw_register_fixed_factor(NULL, nand_name,
267 						   core_name, 0, 1, 1);
268 	if (IS_ERR(hw)) {
269 		ret = PTR_ERR(hw);
270 		goto fail4;
271 	}
272 
273 	cp110_clks[CP110_CORE_NAND] = hw;
274 
275 	for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
276 		const char *parent, *name;
277 		int ret;
278 
279 		ret = of_property_read_string_index(np,
280 						    "gate-clock-output-names",
281 						    i, &name);
282 		/* Reached the end of the list? */
283 		if (ret < 0)
284 			break;
285 
286 		if (!strcmp(name, "none"))
287 			continue;
288 
289 		switch (i) {
290 		case CP110_GATE_AUDIO:
291 		case CP110_GATE_COMM_UNIT:
292 		case CP110_GATE_EIP150:
293 		case CP110_GATE_EIP197:
294 		case CP110_GATE_SLOW_IO:
295 			of_property_read_string_index(np,
296 						      "gate-clock-output-names",
297 						      CP110_GATE_MAIN, &parent);
298 			break;
299 		case CP110_GATE_NAND:
300 			parent = nand_name;
301 			break;
302 		case CP110_GATE_PPV2:
303 			parent = ppv2_name;
304 			break;
305 		case CP110_GATE_SDIO:
306 			of_property_read_string_index(np,
307 						      "gate-clock-output-names",
308 						      CP110_GATE_SDMMC, &parent);
309 			break;
310 		case CP110_GATE_XOR1:
311 		case CP110_GATE_XOR0:
312 		case CP110_GATE_PCIE_X1_0:
313 		case CP110_GATE_PCIE_X1_1:
314 		case CP110_GATE_PCIE_X4:
315 			of_property_read_string_index(np,
316 						      "gate-clock-output-names",
317 						      CP110_GATE_PCIE_XOR, &parent);
318 			break;
319 		case CP110_GATE_SATA:
320 		case CP110_GATE_USB3H0:
321 		case CP110_GATE_USB3H1:
322 		case CP110_GATE_USB3DEV:
323 			of_property_read_string_index(np,
324 						      "gate-clock-output-names",
325 						      CP110_GATE_SATA_USB, &parent);
326 			break;
327 		default:
328 			parent = core_name;
329 			break;
330 		}
331 
332 		hw = cp110_register_gate(name, parent, regmap, i);
333 		if (IS_ERR(hw)) {
334 			ret = PTR_ERR(hw);
335 			goto fail_gate;
336 		}
337 
338 		cp110_clks[CP110_MAX_CORE_CLOCKS + i] = hw;
339 	}
340 
341 	ret = of_clk_add_hw_provider(np, cp110_of_clk_get, cp110_clk_data);
342 	if (ret)
343 		goto fail_clk_add;
344 
345 	platform_set_drvdata(pdev, cp110_clks);
346 
347 	return 0;
348 
349 fail_clk_add:
350 fail_gate:
351 	for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
352 		hw = cp110_clks[CP110_MAX_CORE_CLOCKS + i];
353 
354 		if (hw)
355 			cp110_unregister_gate(hw);
356 	}
357 
358 	clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
359 fail4:
360 	clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
361 fail3:
362 	clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_EIP]);
363 fail2:
364 	clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
365 fail1:
366 	clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_APLL]);
367 fail0:
368 	return ret;
369 }
370 
371 static const struct of_device_id cp110_syscon_of_match[] = {
372 	{ .compatible = "marvell,cp110-system-controller0", },
373 	{ }
374 };
375 
376 static struct platform_driver cp110_syscon_driver = {
377 	.probe = cp110_syscon_clk_probe,
378 	.driver		= {
379 		.name	= "marvell-cp110-system-controller0",
380 		.of_match_table = cp110_syscon_of_match,
381 		.suppress_bind_attrs = true,
382 	},
383 };
384 builtin_platform_driver(cp110_syscon_driver);
385