1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Marvell Armada CP110 System Controller 4 * 5 * Copyright (C) 2016 Marvell 6 * 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * 9 */ 10 11 /* 12 * CP110 has 6 core clocks: 13 * 14 * - PLL0 (1 Ghz) 15 * - PPv2 core (1/3 PLL0) 16 * - x2 Core (1/2 PLL0) 17 * - Core (1/2 x2 Core) 18 * - SDIO (2/5 PLL0) 19 * 20 * - NAND clock, which is either: 21 * - Equal to SDIO clock 22 * - 2/5 PLL0 23 * 24 * CP110 has 32 gateable clocks, for the various peripherals in the IP. 25 */ 26 27 #define pr_fmt(fmt) "cp110-system-controller: " fmt 28 29 #include <linux/clk-provider.h> 30 #include <linux/mfd/syscon.h> 31 #include <linux/init.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/platform_device.h> 35 #include <linux/regmap.h> 36 #include <linux/slab.h> 37 38 #define CP110_PM_CLOCK_GATING_REG 0x220 39 #define CP110_NAND_FLASH_CLK_CTRL_REG 0x700 40 #define NF_CLOCK_SEL_400_MASK BIT(0) 41 42 enum { 43 CP110_CLK_TYPE_CORE, 44 CP110_CLK_TYPE_GATABLE, 45 }; 46 47 #define CP110_MAX_CORE_CLOCKS 6 48 #define CP110_MAX_GATABLE_CLOCKS 32 49 50 #define CP110_CLK_NUM \ 51 (CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS) 52 53 #define CP110_CORE_PLL0 0 54 #define CP110_CORE_PPV2 1 55 #define CP110_CORE_X2CORE 2 56 #define CP110_CORE_CORE 3 57 #define CP110_CORE_NAND 4 58 #define CP110_CORE_SDIO 5 59 60 /* A number of gateable clocks need special handling */ 61 #define CP110_GATE_AUDIO 0 62 #define CP110_GATE_COMM_UNIT 1 63 #define CP110_GATE_NAND 2 64 #define CP110_GATE_PPV2 3 65 #define CP110_GATE_SDIO 4 66 #define CP110_GATE_MG 5 67 #define CP110_GATE_MG_CORE 6 68 #define CP110_GATE_XOR1 7 69 #define CP110_GATE_XOR0 8 70 #define CP110_GATE_GOP_DP 9 71 #define CP110_GATE_PCIE_X1_0 11 72 #define CP110_GATE_PCIE_X1_1 12 73 #define CP110_GATE_PCIE_X4 13 74 #define CP110_GATE_PCIE_XOR 14 75 #define CP110_GATE_SATA 15 76 #define CP110_GATE_SATA_USB 16 77 #define CP110_GATE_MAIN 17 78 #define CP110_GATE_SDMMC_GOP 18 79 #define CP110_GATE_SLOW_IO 21 80 #define CP110_GATE_USB3H0 22 81 #define CP110_GATE_USB3H1 23 82 #define CP110_GATE_USB3DEV 24 83 #define CP110_GATE_EIP150 25 84 #define CP110_GATE_EIP197 26 85 86 static const char * const gate_base_names[] = { 87 [CP110_GATE_AUDIO] = "audio", 88 [CP110_GATE_COMM_UNIT] = "communit", 89 [CP110_GATE_NAND] = "nand", 90 [CP110_GATE_PPV2] = "ppv2", 91 [CP110_GATE_SDIO] = "sdio", 92 [CP110_GATE_MG] = "mg-domain", 93 [CP110_GATE_MG_CORE] = "mg-core", 94 [CP110_GATE_XOR1] = "xor1", 95 [CP110_GATE_XOR0] = "xor0", 96 [CP110_GATE_GOP_DP] = "gop-dp", 97 [CP110_GATE_PCIE_X1_0] = "pcie_x10", 98 [CP110_GATE_PCIE_X1_1] = "pcie_x11", 99 [CP110_GATE_PCIE_X4] = "pcie_x4", 100 [CP110_GATE_PCIE_XOR] = "pcie-xor", 101 [CP110_GATE_SATA] = "sata", 102 [CP110_GATE_SATA_USB] = "sata-usb", 103 [CP110_GATE_MAIN] = "main", 104 [CP110_GATE_SDMMC_GOP] = "sd-mmc-gop", 105 [CP110_GATE_SLOW_IO] = "slow-io", 106 [CP110_GATE_USB3H0] = "usb3h0", 107 [CP110_GATE_USB3H1] = "usb3h1", 108 [CP110_GATE_USB3DEV] = "usb3dev", 109 [CP110_GATE_EIP150] = "eip150", 110 [CP110_GATE_EIP197] = "eip197" 111 }; 112 113 struct cp110_gate_clk { 114 struct clk_hw hw; 115 struct regmap *regmap; 116 u8 bit_idx; 117 }; 118 119 #define to_cp110_gate_clk(hw) container_of(hw, struct cp110_gate_clk, hw) 120 121 static int cp110_gate_enable(struct clk_hw *hw) 122 { 123 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw); 124 125 regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG, 126 BIT(gate->bit_idx), BIT(gate->bit_idx)); 127 128 return 0; 129 } 130 131 static void cp110_gate_disable(struct clk_hw *hw) 132 { 133 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw); 134 135 regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG, 136 BIT(gate->bit_idx), 0); 137 } 138 139 static int cp110_gate_is_enabled(struct clk_hw *hw) 140 { 141 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw); 142 u32 val; 143 144 regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val); 145 146 return val & BIT(gate->bit_idx); 147 } 148 149 static const struct clk_ops cp110_gate_ops = { 150 .enable = cp110_gate_enable, 151 .disable = cp110_gate_disable, 152 .is_enabled = cp110_gate_is_enabled, 153 }; 154 155 static struct clk_hw *cp110_register_gate(const char *name, 156 const char *parent_name, 157 struct regmap *regmap, u8 bit_idx) 158 { 159 struct cp110_gate_clk *gate; 160 struct clk_hw *hw; 161 struct clk_init_data init; 162 int ret; 163 164 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 165 if (!gate) 166 return ERR_PTR(-ENOMEM); 167 168 memset(&init, 0, sizeof(init)); 169 170 init.name = name; 171 init.ops = &cp110_gate_ops; 172 init.parent_names = &parent_name; 173 init.num_parents = 1; 174 175 gate->regmap = regmap; 176 gate->bit_idx = bit_idx; 177 gate->hw.init = &init; 178 179 hw = &gate->hw; 180 ret = clk_hw_register(NULL, hw); 181 if (ret) { 182 kfree(gate); 183 hw = ERR_PTR(ret); 184 } 185 186 return hw; 187 } 188 189 static void cp110_unregister_gate(struct clk_hw *hw) 190 { 191 clk_hw_unregister(hw); 192 kfree(to_cp110_gate_clk(hw)); 193 } 194 195 static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec, 196 void *data) 197 { 198 struct clk_hw_onecell_data *clk_data = data; 199 unsigned int type = clkspec->args[0]; 200 unsigned int idx = clkspec->args[1]; 201 202 if (type == CP110_CLK_TYPE_CORE) { 203 if (idx >= CP110_MAX_CORE_CLOCKS) 204 return ERR_PTR(-EINVAL); 205 return clk_data->hws[idx]; 206 } else if (type == CP110_CLK_TYPE_GATABLE) { 207 if (idx >= CP110_MAX_GATABLE_CLOCKS) 208 return ERR_PTR(-EINVAL); 209 return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx]; 210 } 211 212 return ERR_PTR(-EINVAL); 213 } 214 215 static char *cp110_unique_name(struct device *dev, struct device_node *np, 216 const char *name) 217 { 218 const __be32 *reg; 219 u64 addr; 220 221 /* Do not create a name if there is no clock */ 222 if (!name) 223 return NULL; 224 225 reg = of_get_property(np, "reg", NULL); 226 addr = of_translate_address(np, reg); 227 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s", 228 (unsigned long long)addr, name); 229 } 230 231 static int cp110_syscon_common_probe(struct platform_device *pdev, 232 struct device_node *syscon_node) 233 { 234 struct regmap *regmap; 235 struct device *dev = &pdev->dev; 236 struct device_node *np = dev->of_node; 237 const char *ppv2_name, *pll0_name, *core_name, *x2core_name, *nand_name, 238 *sdio_name; 239 struct clk_hw_onecell_data *cp110_clk_data; 240 struct clk_hw *hw, **cp110_clks; 241 u32 nand_clk_ctrl; 242 int i, ret; 243 char *gate_name[ARRAY_SIZE(gate_base_names)]; 244 245 regmap = syscon_node_to_regmap(syscon_node); 246 if (IS_ERR(regmap)) 247 return PTR_ERR(regmap); 248 249 ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG, 250 &nand_clk_ctrl); 251 if (ret) 252 return ret; 253 254 cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) + 255 sizeof(struct clk_hw *) * CP110_CLK_NUM, 256 GFP_KERNEL); 257 if (!cp110_clk_data) 258 return -ENOMEM; 259 260 cp110_clks = cp110_clk_data->hws; 261 cp110_clk_data->num = CP110_CLK_NUM; 262 263 /* Register the PLL0 which is the root of the hw tree */ 264 pll0_name = cp110_unique_name(dev, syscon_node, "pll0"); 265 hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0, 266 1000 * 1000 * 1000); 267 if (IS_ERR(hw)) { 268 ret = PTR_ERR(hw); 269 goto fail_pll0; 270 } 271 272 cp110_clks[CP110_CORE_PLL0] = hw; 273 274 /* PPv2 is PLL0/3 */ 275 ppv2_name = cp110_unique_name(dev, syscon_node, "ppv2-core"); 276 hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3); 277 if (IS_ERR(hw)) { 278 ret = PTR_ERR(hw); 279 goto fail_ppv2; 280 } 281 282 cp110_clks[CP110_CORE_PPV2] = hw; 283 284 /* X2CORE clock is PLL0/2 */ 285 x2core_name = cp110_unique_name(dev, syscon_node, "x2core"); 286 hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name, 287 0, 1, 2); 288 if (IS_ERR(hw)) { 289 ret = PTR_ERR(hw); 290 goto fail_eip; 291 } 292 293 cp110_clks[CP110_CORE_X2CORE] = hw; 294 295 /* Core clock is X2CORE/2 */ 296 core_name = cp110_unique_name(dev, syscon_node, "core"); 297 hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name, 298 0, 1, 2); 299 if (IS_ERR(hw)) { 300 ret = PTR_ERR(hw); 301 goto fail_core; 302 } 303 304 cp110_clks[CP110_CORE_CORE] = hw; 305 /* NAND can be either PLL0/2.5 or core clock */ 306 nand_name = cp110_unique_name(dev, syscon_node, "nand-core"); 307 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK) 308 hw = clk_hw_register_fixed_factor(NULL, nand_name, 309 pll0_name, 0, 2, 5); 310 else 311 hw = clk_hw_register_fixed_factor(NULL, nand_name, 312 core_name, 0, 1, 1); 313 if (IS_ERR(hw)) { 314 ret = PTR_ERR(hw); 315 goto fail_nand; 316 } 317 318 cp110_clks[CP110_CORE_NAND] = hw; 319 320 /* SDIO clock is PLL0/2.5 */ 321 sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core"); 322 hw = clk_hw_register_fixed_factor(NULL, sdio_name, 323 pll0_name, 0, 2, 5); 324 if (IS_ERR(hw)) { 325 ret = PTR_ERR(hw); 326 goto fail_sdio; 327 } 328 329 cp110_clks[CP110_CORE_SDIO] = hw; 330 331 /* create the unique name for all the gate clocks */ 332 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) 333 gate_name[i] = cp110_unique_name(dev, syscon_node, 334 gate_base_names[i]); 335 336 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) { 337 const char *parent; 338 339 if (gate_name[i] == NULL) 340 continue; 341 342 switch (i) { 343 case CP110_GATE_NAND: 344 parent = nand_name; 345 break; 346 case CP110_GATE_MG: 347 case CP110_GATE_GOP_DP: 348 case CP110_GATE_PPV2: 349 parent = ppv2_name; 350 break; 351 case CP110_GATE_SDIO: 352 parent = sdio_name; 353 break; 354 case CP110_GATE_MAIN: 355 case CP110_GATE_PCIE_XOR: 356 case CP110_GATE_PCIE_X4: 357 case CP110_GATE_EIP150: 358 case CP110_GATE_EIP197: 359 parent = x2core_name; 360 break; 361 default: 362 parent = core_name; 363 break; 364 } 365 hw = cp110_register_gate(gate_name[i], parent, regmap, i); 366 367 if (IS_ERR(hw)) { 368 ret = PTR_ERR(hw); 369 goto fail_gate; 370 } 371 372 cp110_clks[CP110_MAX_CORE_CLOCKS + i] = hw; 373 } 374 375 ret = of_clk_add_hw_provider(np, cp110_of_clk_get, cp110_clk_data); 376 if (ret) 377 goto fail_clk_add; 378 379 platform_set_drvdata(pdev, cp110_clks); 380 381 return 0; 382 383 fail_clk_add: 384 fail_gate: 385 for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) { 386 hw = cp110_clks[CP110_MAX_CORE_CLOCKS + i]; 387 388 if (hw) 389 cp110_unregister_gate(hw); 390 } 391 392 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]); 393 fail_sdio: 394 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]); 395 fail_nand: 396 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]); 397 fail_core: 398 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_X2CORE]); 399 fail_eip: 400 clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]); 401 fail_ppv2: 402 clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_PLL0]); 403 fail_pll0: 404 return ret; 405 } 406 407 static int cp110_syscon_legacy_clk_probe(struct platform_device *pdev) 408 { 409 dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n"); 410 dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n"); 411 dev_warn(&pdev->dev, FW_WARN 412 "This binding won't be supported in future kernels\n"); 413 414 return cp110_syscon_common_probe(pdev, pdev->dev.of_node); 415 } 416 417 static int cp110_clk_probe(struct platform_device *pdev) 418 { 419 return cp110_syscon_common_probe(pdev, pdev->dev.of_node->parent); 420 } 421 422 static const struct of_device_id cp110_syscon_legacy_of_match[] = { 423 { .compatible = "marvell,cp110-system-controller0", }, 424 { } 425 }; 426 427 static struct platform_driver cp110_syscon_legacy_driver = { 428 .probe = cp110_syscon_legacy_clk_probe, 429 .driver = { 430 .name = "marvell-cp110-system-controller0", 431 .of_match_table = cp110_syscon_legacy_of_match, 432 .suppress_bind_attrs = true, 433 }, 434 }; 435 builtin_platform_driver(cp110_syscon_legacy_driver); 436 437 static const struct of_device_id cp110_clock_of_match[] = { 438 { .compatible = "marvell,cp110-clock", }, 439 { } 440 }; 441 442 static struct platform_driver cp110_clock_driver = { 443 .probe = cp110_clk_probe, 444 .driver = { 445 .name = "marvell-cp110-clock", 446 .of_match_table = cp110_clock_of_match, 447 .suppress_bind_attrs = true, 448 }, 449 }; 450 builtin_platform_driver(cp110_clock_driver); 451