1 /* 2 * Marvell EBU SoC common clock handling 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Andrew Lunn <andrew@lunn.ch> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/clk.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk-provider.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 23 #include "common.h" 24 25 /* 26 * Core Clocks 27 */ 28 29 static struct clk_onecell_data clk_data; 30 31 void __init mvebu_coreclk_setup(struct device_node *np, 32 const struct coreclk_soc_desc *desc) 33 { 34 const char *tclk_name = "tclk"; 35 const char *cpuclk_name = "cpuclk"; 36 void __iomem *base; 37 unsigned long rate; 38 int n; 39 40 base = of_iomap(np, 0); 41 if (WARN_ON(!base)) 42 return; 43 44 /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ 45 clk_data.clk_num = 2 + desc->num_ratios; 46 clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), 47 GFP_KERNEL); 48 if (WARN_ON(!clk_data.clks)) { 49 iounmap(base); 50 return; 51 } 52 53 /* Register TCLK */ 54 of_property_read_string_index(np, "clock-output-names", 0, 55 &tclk_name); 56 rate = desc->get_tclk_freq(base); 57 clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, 58 CLK_IS_ROOT, rate); 59 WARN_ON(IS_ERR(clk_data.clks[0])); 60 61 /* Register CPU clock */ 62 of_property_read_string_index(np, "clock-output-names", 1, 63 &cpuclk_name); 64 rate = desc->get_cpu_freq(base); 65 clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, 66 CLK_IS_ROOT, rate); 67 WARN_ON(IS_ERR(clk_data.clks[1])); 68 69 /* Register fixed-factor clocks derived from CPU clock */ 70 for (n = 0; n < desc->num_ratios; n++) { 71 const char *rclk_name = desc->ratios[n].name; 72 int mult, div; 73 74 of_property_read_string_index(np, "clock-output-names", 75 2+n, &rclk_name); 76 desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); 77 clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name, 78 cpuclk_name, 0, mult, div); 79 WARN_ON(IS_ERR(clk_data.clks[2+n])); 80 }; 81 82 /* SAR register isn't needed anymore */ 83 iounmap(base); 84 85 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 86 } 87 88 /* 89 * Clock Gating Control 90 */ 91 92 struct clk_gating_ctrl { 93 spinlock_t lock; 94 struct clk **gates; 95 int num_gates; 96 }; 97 98 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 99 100 static struct clk *clk_gating_get_src( 101 struct of_phandle_args *clkspec, void *data) 102 { 103 struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data; 104 int n; 105 106 if (clkspec->args_count < 1) 107 return ERR_PTR(-EINVAL); 108 109 for (n = 0; n < ctrl->num_gates; n++) { 110 struct clk_gate *gate = 111 to_clk_gate(__clk_get_hw(ctrl->gates[n])); 112 if (clkspec->args[0] == gate->bit_idx) 113 return ctrl->gates[n]; 114 } 115 return ERR_PTR(-ENODEV); 116 } 117 118 void __init mvebu_clk_gating_setup(struct device_node *np, 119 const struct clk_gating_soc_desc *desc) 120 { 121 struct clk_gating_ctrl *ctrl; 122 struct clk *clk; 123 void __iomem *base; 124 const char *default_parent = NULL; 125 int n; 126 127 base = of_iomap(np, 0); 128 if (WARN_ON(!base)) 129 return; 130 131 clk = of_clk_get(np, 0); 132 if (!IS_ERR(clk)) { 133 default_parent = __clk_get_name(clk); 134 clk_put(clk); 135 } 136 137 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 138 if (WARN_ON(!ctrl)) 139 goto ctrl_out; 140 141 spin_lock_init(&ctrl->lock); 142 143 /* Count, allocate, and register clock gates */ 144 for (n = 0; desc[n].name;) 145 n++; 146 147 ctrl->num_gates = n; 148 ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), 149 GFP_KERNEL); 150 if (WARN_ON(!ctrl->gates)) 151 goto gates_out; 152 153 for (n = 0; n < ctrl->num_gates; n++) { 154 const char *parent = 155 (desc[n].parent) ? desc[n].parent : default_parent; 156 ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, 157 desc[n].flags, base, desc[n].bit_idx, 158 0, &ctrl->lock); 159 WARN_ON(IS_ERR(ctrl->gates[n])); 160 } 161 162 of_clk_add_provider(np, clk_gating_get_src, ctrl); 163 164 return; 165 gates_out: 166 kfree(ctrl); 167 ctrl_out: 168 iounmap(base); 169 } 170