1 /* 2 * Marvell Armada AP806 System Controller 3 * 4 * Copyright (C) 2016 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #define pr_fmt(fmt) "ap806-system-controller: " fmt 14 15 #include <linux/clk-provider.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/init.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 23 #define AP806_SAR_REG 0x400 24 #define AP806_SAR_CLKFREQ_MODE_MASK 0x1f 25 26 #define AP806_CLK_NUM 5 27 28 static struct clk *ap806_clks[AP806_CLK_NUM]; 29 30 static struct clk_onecell_data ap806_clk_data = { 31 .clks = ap806_clks, 32 .clk_num = AP806_CLK_NUM, 33 }; 34 35 static int ap806_syscon_clk_probe(struct platform_device *pdev) 36 { 37 unsigned int freq_mode, cpuclk_freq; 38 const char *name, *fixedclk_name; 39 struct device_node *np = pdev->dev.of_node; 40 struct regmap *regmap; 41 u32 reg; 42 int ret; 43 44 regmap = syscon_node_to_regmap(np); 45 if (IS_ERR(regmap)) { 46 dev_err(&pdev->dev, "cannot get regmap\n"); 47 return PTR_ERR(regmap); 48 } 49 50 ret = regmap_read(regmap, AP806_SAR_REG, ®); 51 if (ret) { 52 dev_err(&pdev->dev, "cannot read from regmap\n"); 53 return ret; 54 } 55 56 freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK; 57 switch (freq_mode) { 58 case 0x0: 59 case 0x1: 60 cpuclk_freq = 2000; 61 break; 62 case 0x6: 63 case 0x7: 64 cpuclk_freq = 1800; 65 break; 66 case 0x4: 67 case 0xB: 68 case 0xD: 69 cpuclk_freq = 1600; 70 break; 71 case 0x1a: 72 cpuclk_freq = 1400; 73 break; 74 case 0x14: 75 case 0x17: 76 cpuclk_freq = 1300; 77 break; 78 case 0x19: 79 cpuclk_freq = 1200; 80 break; 81 case 0x13: 82 case 0x1d: 83 cpuclk_freq = 1000; 84 break; 85 case 0x1c: 86 cpuclk_freq = 800; 87 break; 88 case 0x1b: 89 cpuclk_freq = 600; 90 break; 91 default: 92 dev_err(&pdev->dev, "invalid SAR value\n"); 93 return -EINVAL; 94 } 95 96 /* Convert to hertz */ 97 cpuclk_freq *= 1000 * 1000; 98 99 /* CPU clocks depend on the Sample At Reset configuration */ 100 of_property_read_string_index(np, "clock-output-names", 101 0, &name); 102 ap806_clks[0] = clk_register_fixed_rate(&pdev->dev, name, NULL, 103 0, cpuclk_freq); 104 if (IS_ERR(ap806_clks[0])) { 105 ret = PTR_ERR(ap806_clks[0]); 106 goto fail0; 107 } 108 109 of_property_read_string_index(np, "clock-output-names", 110 1, &name); 111 ap806_clks[1] = clk_register_fixed_rate(&pdev->dev, name, NULL, 0, 112 cpuclk_freq); 113 if (IS_ERR(ap806_clks[1])) { 114 ret = PTR_ERR(ap806_clks[1]); 115 goto fail1; 116 } 117 118 /* Fixed clock is always 1200 Mhz */ 119 of_property_read_string_index(np, "clock-output-names", 120 2, &fixedclk_name); 121 ap806_clks[2] = clk_register_fixed_rate(&pdev->dev, fixedclk_name, NULL, 122 0, 1200 * 1000 * 1000); 123 if (IS_ERR(ap806_clks[2])) { 124 ret = PTR_ERR(ap806_clks[2]); 125 goto fail2; 126 } 127 128 /* MSS Clock is fixed clock divided by 6 */ 129 of_property_read_string_index(np, "clock-output-names", 130 3, &name); 131 ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name, 132 0, 1, 6); 133 if (IS_ERR(ap806_clks[3])) { 134 ret = PTR_ERR(ap806_clks[3]); 135 goto fail3; 136 } 137 138 /* eMMC Clock is fixed clock divided by 3 */ 139 if (of_property_read_string_index(np, "clock-output-names", 140 4, &name)) { 141 ap806_clk_data.clk_num--; 142 dev_warn(&pdev->dev, 143 "eMMC clock missing: update the device tree!\n"); 144 } else { 145 ap806_clks[4] = clk_register_fixed_factor(NULL, name, 146 fixedclk_name, 147 0, 1, 3); 148 if (IS_ERR(ap806_clks[4])) { 149 ret = PTR_ERR(ap806_clks[4]); 150 goto fail4; 151 } 152 } 153 154 of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); 155 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); 156 if (ret) 157 goto fail_clk_add; 158 159 return 0; 160 161 fail_clk_add: 162 clk_unregister_fixed_factor(ap806_clks[4]); 163 fail4: 164 clk_unregister_fixed_factor(ap806_clks[3]); 165 fail3: 166 clk_unregister_fixed_rate(ap806_clks[2]); 167 fail2: 168 clk_unregister_fixed_rate(ap806_clks[1]); 169 fail1: 170 clk_unregister_fixed_rate(ap806_clks[0]); 171 fail0: 172 return ret; 173 } 174 175 static const struct of_device_id ap806_syscon_of_match[] = { 176 { .compatible = "marvell,ap806-system-controller", }, 177 { } 178 }; 179 180 static struct platform_driver ap806_syscon_driver = { 181 .probe = ap806_syscon_clk_probe, 182 .driver = { 183 .name = "marvell-ap806-system-controller", 184 .of_match_table = ap806_syscon_of_match, 185 .suppress_bind_attrs = true, 186 }, 187 }; 188 builtin_platform_driver(ap806_syscon_driver); 189