1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * pxa910 clock framework source file 4 * 5 * Copyright (C) 2012 Marvell 6 * Chao Xie <xiechao.mail@gmail.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/spinlock.h> 12 #include <linux/io.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/of_address.h> 16 17 #include <dt-bindings/clock/marvell,pxa910.h> 18 19 #include "clk.h" 20 #include "reset.h" 21 22 #define APBC_RTC 0x28 23 #define APBC_TWSI0 0x2c 24 #define APBC_KPC 0x18 25 #define APBC_UART0 0x0 26 #define APBC_UART1 0x4 27 #define APBC_GPIO 0x8 28 #define APBC_PWM0 0xc 29 #define APBC_PWM1 0x10 30 #define APBC_PWM2 0x14 31 #define APBC_PWM3 0x18 32 #define APBC_SSP0 0x1c 33 #define APBC_SSP1 0x20 34 #define APBC_SSP2 0x4c 35 #define APBC_TIMER0 0x30 36 #define APBC_TIMER1 0x44 37 #define APBCP_TWSI1 0x28 38 #define APBCP_UART2 0x1c 39 #define APMU_SDH0 0x54 40 #define APMU_SDH1 0x58 41 #define APMU_USB 0x5c 42 #define APMU_DISP0 0x4c 43 #define APMU_CCIC0 0x50 44 #define APMU_DFC 0x60 45 #define MPMU_UART_PLL 0x14 46 47 struct pxa910_clk_unit { 48 struct mmp_clk_unit unit; 49 void __iomem *mpmu_base; 50 void __iomem *apmu_base; 51 void __iomem *apbc_base; 52 void __iomem *apbcp_base; 53 }; 54 55 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { 56 {PXA910_CLK_CLK32, "clk32", NULL, 0, 32768}, 57 {PXA910_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000}, 58 {PXA910_CLK_PLL1, "pll1", NULL, 0, 624000000}, 59 {PXA910_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000}, 60 }; 61 62 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { 63 {PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0}, 64 {PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0}, 65 {PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0}, 66 {PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0}, 67 {PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0}, 68 {PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0}, 69 {PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0}, 70 {PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0}, 71 {PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0}, 72 {PXA910_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0}, 73 {PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0}, 74 {PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0}, 75 {PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0}, 76 {PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0}, 77 }; 78 79 static struct mmp_clk_factor_masks uart_factor_masks = { 80 .factor = 2, 81 .num_mask = 0x1fff, 82 .den_mask = 0x1fff, 83 .num_shift = 16, 84 .den_shift = 0, 85 }; 86 87 static struct mmp_clk_factor_tbl uart_factor_tbl[] = { 88 {.num = 8125, .den = 1536}, /*14.745MHZ */ 89 }; 90 91 static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit) 92 { 93 struct clk *clk; 94 struct mmp_clk_unit *unit = &pxa_unit->unit; 95 96 mmp_register_fixed_rate_clks(unit, fixed_rate_clks, 97 ARRAY_SIZE(fixed_rate_clks)); 98 99 mmp_register_fixed_factor_clks(unit, fixed_factor_clks, 100 ARRAY_SIZE(fixed_factor_clks)); 101 102 clk = mmp_clk_register_factor("uart_pll", "pll1_4", 103 CLK_SET_RATE_PARENT, 104 pxa_unit->mpmu_base + MPMU_UART_PLL, 105 &uart_factor_masks, uart_factor_tbl, 106 ARRAY_SIZE(uart_factor_tbl), NULL); 107 mmp_clk_add(unit, PXA910_CLK_UART_PLL, clk); 108 } 109 110 static DEFINE_SPINLOCK(uart0_lock); 111 static DEFINE_SPINLOCK(uart1_lock); 112 static DEFINE_SPINLOCK(uart2_lock); 113 static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"}; 114 115 static DEFINE_SPINLOCK(ssp0_lock); 116 static DEFINE_SPINLOCK(ssp1_lock); 117 static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; 118 119 static DEFINE_SPINLOCK(timer0_lock); 120 static DEFINE_SPINLOCK(timer1_lock); 121 static const char *timer_parent_names[] = {"pll1_48", "clk32", "pll1_96"}; 122 123 static DEFINE_SPINLOCK(reset_lock); 124 125 static struct mmp_param_mux_clk apbc_mux_clks[] = { 126 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock}, 127 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock}, 128 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock}, 129 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock}, 130 {0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER0, 4, 3, 0, &timer0_lock}, 131 {0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER1, 4, 3, 0, &timer1_lock}, 132 }; 133 134 static struct mmp_param_mux_clk apbcp_mux_clks[] = { 135 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock}, 136 }; 137 138 static struct mmp_param_gate_clk apbc_gate_clks[] = { 139 {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock}, 140 {PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock}, 141 {PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL}, 142 {PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL}, 143 {PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock}, 144 {PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock}, 145 {PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock}, 146 {PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock}, 147 /* The gate clocks has mux parent. */ 148 {PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock}, 149 {PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock}, 150 {PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock}, 151 {PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock}, 152 {PXA910_CLK_TIMER0, "timer0_clk", "timer0_mux", CLK_SET_RATE_PARENT, APBC_TIMER0, 0x3, 0x3, 0x0, 0, &timer0_lock}, 153 {PXA910_CLK_TIMER1, "timer1_clk", "timer1_mux", CLK_SET_RATE_PARENT, APBC_TIMER1, 0x3, 0x3, 0x0, 0, &timer1_lock}, 154 }; 155 156 static struct mmp_param_gate_clk apbcp_gate_clks[] = { 157 {PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock}, 158 /* The gate clocks has mux parent. */ 159 {PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock}, 160 }; 161 162 static void pxa910_apb_periph_clk_init(struct pxa910_clk_unit *pxa_unit) 163 { 164 struct mmp_clk_unit *unit = &pxa_unit->unit; 165 166 mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base, 167 ARRAY_SIZE(apbc_mux_clks)); 168 169 mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base, 170 ARRAY_SIZE(apbcp_mux_clks)); 171 172 mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base, 173 ARRAY_SIZE(apbc_gate_clks)); 174 175 mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base, 176 ARRAY_SIZE(apbcp_gate_clks)); 177 } 178 179 static DEFINE_SPINLOCK(sdh0_lock); 180 static DEFINE_SPINLOCK(sdh1_lock); 181 static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"}; 182 183 static DEFINE_SPINLOCK(usb_lock); 184 185 static DEFINE_SPINLOCK(disp0_lock); 186 static const char *disp_parent_names[] = {"pll1_2", "pll1_12"}; 187 188 static DEFINE_SPINLOCK(ccic0_lock); 189 static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"}; 190 static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"}; 191 192 static struct mmp_param_mux_clk apmu_mux_clks[] = { 193 {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock}, 194 {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock}, 195 {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock}, 196 {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock}, 197 {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock}, 198 }; 199 200 static struct mmp_param_div_clk apmu_div_clks[] = { 201 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock}, 202 }; 203 204 static struct mmp_param_gate_clk apmu_gate_clks[] = { 205 {PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL}, 206 {PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock}, 207 {PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock}, 208 /* The gate clocks has mux parent. */ 209 {PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock}, 210 {PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock}, 211 {PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock}, 212 {PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock}, 213 {PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock}, 214 {PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock}, 215 }; 216 217 static void pxa910_axi_periph_clk_init(struct pxa910_clk_unit *pxa_unit) 218 { 219 struct mmp_clk_unit *unit = &pxa_unit->unit; 220 221 mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base, 222 ARRAY_SIZE(apmu_mux_clks)); 223 224 mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base, 225 ARRAY_SIZE(apmu_div_clks)); 226 227 mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base, 228 ARRAY_SIZE(apmu_gate_clks)); 229 } 230 231 static void pxa910_clk_reset_init(struct device_node *np, 232 struct pxa910_clk_unit *pxa_unit) 233 { 234 struct mmp_clk_reset_cell *cells; 235 int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets; 236 237 nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks); 238 nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks); 239 nr_resets = nr_resets_apbc + nr_resets_apbcp; 240 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); 241 if (!cells) 242 return; 243 244 base = 0; 245 for (i = 0; i < nr_resets_apbc; i++) { 246 cells[base + i].clk_id = apbc_gate_clks[i].id; 247 cells[base + i].reg = 248 pxa_unit->apbc_base + apbc_gate_clks[i].offset; 249 cells[base + i].flags = 0; 250 cells[base + i].lock = apbc_gate_clks[i].lock; 251 cells[base + i].bits = 0x4; 252 } 253 254 base = nr_resets_apbc; 255 for (i = 0; i < nr_resets_apbcp; i++) { 256 cells[base + i].clk_id = apbcp_gate_clks[i].id; 257 cells[base + i].reg = 258 pxa_unit->apbc_base + apbc_gate_clks[i].offset; 259 cells[base + i].flags = 0; 260 cells[base + i].lock = apbc_gate_clks[i].lock; 261 cells[base + i].bits = 0x4; 262 } 263 264 mmp_clk_reset_register(np, cells, nr_resets); 265 } 266 267 static void __init pxa910_clk_init(struct device_node *np) 268 { 269 struct pxa910_clk_unit *pxa_unit; 270 271 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); 272 if (!pxa_unit) 273 return; 274 275 pxa_unit->mpmu_base = of_iomap(np, 0); 276 if (!pxa_unit->mpmu_base) { 277 pr_err("failed to map mpmu registers\n"); 278 goto free_memory; 279 } 280 281 pxa_unit->apmu_base = of_iomap(np, 1); 282 if (!pxa_unit->apmu_base) { 283 pr_err("failed to map apmu registers\n"); 284 goto unmap_mpmu_region; 285 } 286 287 pxa_unit->apbc_base = of_iomap(np, 2); 288 if (!pxa_unit->apbc_base) { 289 pr_err("failed to map apbc registers\n"); 290 goto unmap_apmu_region; 291 } 292 293 pxa_unit->apbcp_base = of_iomap(np, 3); 294 if (!pxa_unit->apbcp_base) { 295 pr_err("failed to map apbcp registers\n"); 296 goto unmap_apbc_region; 297 } 298 299 mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS); 300 301 pxa910_pll_init(pxa_unit); 302 303 pxa910_apb_periph_clk_init(pxa_unit); 304 305 pxa910_axi_periph_clk_init(pxa_unit); 306 307 pxa910_clk_reset_init(np, pxa_unit); 308 309 return; 310 311 unmap_apbc_region: 312 iounmap(pxa_unit->apbc_base); 313 unmap_apmu_region: 314 iounmap(pxa_unit->apmu_base); 315 unmap_mpmu_region: 316 iounmap(pxa_unit->mpmu_base); 317 free_memory: 318 kfree(pxa_unit); 319 } 320 321 CLK_OF_DECLARE(pxa910_clk, "marvell,pxa910-clock", pxa910_clk_init); 322