1 /* 2 * pxa1928 clock framework source file 3 * 4 * Copyright (C) 2015 Linaro, Ltd. 5 * Rob Herring <robh@kernel.org> 6 * 7 * Based on drivers/clk/mmp/clk-of-mmp2.c: 8 * Copyright (C) 2012 Marvell 9 * Chao Xie <xiechao.mail@gmail.com> 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 #include <linux/of_address.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 21 #include <dt-bindings/clock/marvell,pxa1928.h> 22 23 #include "clk.h" 24 #include "reset.h" 25 26 #define MPMU_UART_PLL 0x14 27 28 struct pxa1928_clk_unit { 29 struct mmp_clk_unit unit; 30 void __iomem *mpmu_base; 31 void __iomem *apmu_base; 32 void __iomem *apbc_base; 33 void __iomem *apbcp_base; 34 }; 35 36 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { 37 {0, "clk32", NULL, 0, 32768}, 38 {0, "vctcxo", NULL, 0, 26000000}, 39 {0, "pll1_624", NULL, 0, 624000000}, 40 {0, "pll5p", NULL, 0, 832000000}, 41 {0, "pll5", NULL, 0, 1248000000}, 42 {0, "usb_pll", NULL, 0, 480000000}, 43 }; 44 45 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { 46 {0, "pll1_d2", "pll1_624", 1, 2, 0}, 47 {0, "pll1_d9", "pll1_624", 1, 9, 0}, 48 {0, "pll1_d12", "pll1_624", 1, 12, 0}, 49 {0, "pll1_d16", "pll1_624", 1, 16, 0}, 50 {0, "pll1_d20", "pll1_624", 1, 20, 0}, 51 {0, "pll1_416", "pll1_624", 2, 3, 0}, 52 {0, "vctcxo_d2", "vctcxo", 1, 2, 0}, 53 {0, "vctcxo_d4", "vctcxo", 1, 4, 0}, 54 }; 55 56 static struct mmp_clk_factor_masks uart_factor_masks = { 57 .factor = 2, 58 .num_mask = 0x1fff, 59 .den_mask = 0x1fff, 60 .num_shift = 16, 61 .den_shift = 0, 62 }; 63 64 static struct mmp_clk_factor_tbl uart_factor_tbl[] = { 65 {.num = 832, .den = 234}, /*58.5MHZ */ 66 {.num = 1, .den = 1}, /*26MHZ */ 67 }; 68 69 static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit) 70 { 71 struct clk *clk; 72 struct mmp_clk_unit *unit = &pxa_unit->unit; 73 74 mmp_register_fixed_rate_clks(unit, fixed_rate_clks, 75 ARRAY_SIZE(fixed_rate_clks)); 76 77 mmp_register_fixed_factor_clks(unit, fixed_factor_clks, 78 ARRAY_SIZE(fixed_factor_clks)); 79 80 clk = mmp_clk_register_factor("uart_pll", "pll1_416", 81 CLK_SET_RATE_PARENT, 82 pxa_unit->mpmu_base + MPMU_UART_PLL, 83 &uart_factor_masks, uart_factor_tbl, 84 ARRAY_SIZE(uart_factor_tbl), NULL); 85 } 86 87 static DEFINE_SPINLOCK(uart0_lock); 88 static DEFINE_SPINLOCK(uart1_lock); 89 static DEFINE_SPINLOCK(uart2_lock); 90 static DEFINE_SPINLOCK(uart3_lock); 91 static const char *uart_parent_names[] = {"uart_pll", "vctcxo"}; 92 93 static DEFINE_SPINLOCK(ssp0_lock); 94 static DEFINE_SPINLOCK(ssp1_lock); 95 static const char *ssp_parent_names[] = {"vctcxo_d4", "vctcxo_d2", "vctcxo", "pll1_d12"}; 96 97 static DEFINE_SPINLOCK(reset_lock); 98 99 static struct mmp_param_mux_clk apbc_mux_clks[] = { 100 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock}, 101 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock}, 102 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 4, 3, 0, &uart2_lock}, 103 {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 4, 3, 0, &uart3_lock}, 104 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 4, 3, 0, &ssp0_lock}, 105 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 4, 3, 0, &ssp1_lock}, 106 }; 107 108 static struct mmp_param_gate_clk apbc_gate_clks[] = { 109 {PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 110 {PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 111 {PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 112 {PXA1928_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 113 {PXA1928_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI4 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 114 {PXA1928_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI5 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 115 {PXA1928_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 116 {PXA1928_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, PXA1928_CLK_KPC * 4, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL}, 117 {PXA1928_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, PXA1928_CLK_RTC * 4, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL}, 118 {PXA1928_CLK_PWM0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 119 {PXA1928_CLK_PWM1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 120 {PXA1928_CLK_PWM2, "pwm2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 121 {PXA1928_CLK_PWM3, "pwm3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock}, 122 /* The gate clocks has mux parent. */ 123 {PXA1928_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 0x3, 0x3, 0x0, 0, &uart0_lock}, 124 {PXA1928_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 0x3, 0x3, 0x0, 0, &uart1_lock}, 125 {PXA1928_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 0x3, 0x3, 0x0, 0, &uart2_lock}, 126 {PXA1928_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 0x3, 0x3, 0x0, 0, &uart3_lock}, 127 {PXA1928_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 0x3, 0x3, 0x0, 0, &ssp0_lock}, 128 {PXA1928_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 0x3, 0x3, 0x0, 0, &ssp1_lock}, 129 }; 130 131 static void pxa1928_apb_periph_clk_init(struct pxa1928_clk_unit *pxa_unit) 132 { 133 struct mmp_clk_unit *unit = &pxa_unit->unit; 134 135 mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base, 136 ARRAY_SIZE(apbc_mux_clks)); 137 138 mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base, 139 ARRAY_SIZE(apbc_gate_clks)); 140 } 141 142 static DEFINE_SPINLOCK(sdh0_lock); 143 static DEFINE_SPINLOCK(sdh1_lock); 144 static DEFINE_SPINLOCK(sdh2_lock); 145 static DEFINE_SPINLOCK(sdh3_lock); 146 static DEFINE_SPINLOCK(sdh4_lock); 147 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"}; 148 149 static DEFINE_SPINLOCK(usb_lock); 150 151 static struct mmp_param_mux_clk apmu_mux_clks[] = { 152 {0, "sdh_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 8, 2, 0, &sdh0_lock}, 153 }; 154 155 static struct mmp_param_div_clk apmu_div_clks[] = { 156 {0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock}, 157 }; 158 159 static struct mmp_param_gate_clk apmu_gate_clks[] = { 160 {PXA1928_CLK_USB, "usb_clk", "usb_pll", 0, PXA1928_CLK_USB * 4, 0x9, 0x9, 0x0, 0, &usb_lock}, 161 {PXA1928_CLK_HSIC, "hsic_clk", "usb_pll", 0, PXA1928_CLK_HSIC * 4, 0x9, 0x9, 0x0, 0, &usb_lock}, 162 /* The gate clocks has mux parent. */ 163 {PXA1928_CLK_SDH0, "sdh0_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 0x1b, 0x1b, 0x0, 0, &sdh0_lock}, 164 {PXA1928_CLK_SDH1, "sdh1_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH1 * 4, 0x1b, 0x1b, 0x0, 0, &sdh1_lock}, 165 {PXA1928_CLK_SDH2, "sdh2_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH2 * 4, 0x1b, 0x1b, 0x0, 0, &sdh2_lock}, 166 {PXA1928_CLK_SDH3, "sdh3_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH3 * 4, 0x1b, 0x1b, 0x0, 0, &sdh3_lock}, 167 {PXA1928_CLK_SDH4, "sdh4_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH4 * 4, 0x1b, 0x1b, 0x0, 0, &sdh4_lock}, 168 }; 169 170 static void pxa1928_axi_periph_clk_init(struct pxa1928_clk_unit *pxa_unit) 171 { 172 struct mmp_clk_unit *unit = &pxa_unit->unit; 173 174 mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base, 175 ARRAY_SIZE(apmu_mux_clks)); 176 177 mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base, 178 ARRAY_SIZE(apmu_div_clks)); 179 180 mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base, 181 ARRAY_SIZE(apmu_gate_clks)); 182 } 183 184 static void pxa1928_clk_reset_init(struct device_node *np, 185 struct pxa1928_clk_unit *pxa_unit) 186 { 187 struct mmp_clk_reset_cell *cells; 188 int i, base, nr_resets; 189 190 nr_resets = ARRAY_SIZE(apbc_gate_clks); 191 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); 192 if (!cells) 193 return; 194 195 base = 0; 196 for (i = 0; i < nr_resets; i++) { 197 cells[base + i].clk_id = apbc_gate_clks[i].id; 198 cells[base + i].reg = 199 pxa_unit->apbc_base + apbc_gate_clks[i].offset; 200 cells[base + i].flags = 0; 201 cells[base + i].lock = apbc_gate_clks[i].lock; 202 cells[base + i].bits = 0x4; 203 } 204 205 mmp_clk_reset_register(np, cells, nr_resets); 206 } 207 208 static void __init pxa1928_mpmu_clk_init(struct device_node *np) 209 { 210 struct pxa1928_clk_unit *pxa_unit; 211 212 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); 213 if (!pxa_unit) 214 return; 215 216 pxa_unit->mpmu_base = of_iomap(np, 0); 217 if (!pxa_unit->mpmu_base) { 218 pr_err("failed to map mpmu registers\n"); 219 kfree(pxa_unit); 220 return; 221 } 222 223 pxa1928_pll_init(pxa_unit); 224 } 225 CLK_OF_DECLARE(pxa1928_mpmu_clk, "marvell,pxa1928-mpmu", pxa1928_mpmu_clk_init); 226 227 static void __init pxa1928_apmu_clk_init(struct device_node *np) 228 { 229 struct pxa1928_clk_unit *pxa_unit; 230 231 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); 232 if (!pxa_unit) 233 return; 234 235 pxa_unit->apmu_base = of_iomap(np, 0); 236 if (!pxa_unit->apmu_base) { 237 pr_err("failed to map apmu registers\n"); 238 kfree(pxa_unit); 239 return; 240 } 241 242 mmp_clk_init(np, &pxa_unit->unit, PXA1928_APMU_NR_CLKS); 243 244 pxa1928_axi_periph_clk_init(pxa_unit); 245 } 246 CLK_OF_DECLARE(pxa1928_apmu_clk, "marvell,pxa1928-apmu", pxa1928_apmu_clk_init); 247 248 static void __init pxa1928_apbc_clk_init(struct device_node *np) 249 { 250 struct pxa1928_clk_unit *pxa_unit; 251 252 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); 253 if (!pxa_unit) 254 return; 255 256 pxa_unit->apbc_base = of_iomap(np, 0); 257 if (!pxa_unit->apbc_base) { 258 pr_err("failed to map apbc registers\n"); 259 kfree(pxa_unit); 260 return; 261 } 262 263 mmp_clk_init(np, &pxa_unit->unit, PXA1928_APBC_NR_CLKS); 264 265 pxa1928_apb_periph_clk_init(pxa_unit); 266 pxa1928_clk_reset_init(np, pxa_unit); 267 } 268 CLK_OF_DECLARE(pxa1928_apbc_clk, "marvell,pxa1928-apbc", pxa1928_apbc_clk_init); 269