1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Daire McNamara,<daire.mcnamara@microchip.com> 4 * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5 */ 6 #include <linux/auxiliary_bus.h> 7 #include <linux/clk-provider.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <dt-bindings/clock/microchip,mpfs-clock.h> 13 #include <soc/microchip/mpfs.h> 14 15 /* address offset of control registers */ 16 #define REG_MSSPLL_REF_CR 0x08u 17 #define REG_MSSPLL_POSTDIV_CR 0x10u 18 #define REG_MSSPLL_SSCG_2_CR 0x2Cu 19 #define REG_CLOCK_CONFIG_CR 0x08u 20 #define REG_RTC_CLOCK_CR 0x0Cu 21 #define REG_SUBBLK_CLOCK_CR 0x84u 22 #define REG_SUBBLK_RESET_CR 0x88u 23 24 #define MSSPLL_FBDIV_SHIFT 0x00u 25 #define MSSPLL_FBDIV_WIDTH 0x0Cu 26 #define MSSPLL_REFDIV_SHIFT 0x08u 27 #define MSSPLL_REFDIV_WIDTH 0x06u 28 #define MSSPLL_POSTDIV_SHIFT 0x08u 29 #define MSSPLL_POSTDIV_WIDTH 0x07u 30 #define MSSPLL_FIXED_DIV 4u 31 32 struct mpfs_clock_data { 33 struct device *dev; 34 void __iomem *base; 35 void __iomem *msspll_base; 36 struct clk_hw_onecell_data hw_data; 37 }; 38 39 struct mpfs_msspll_hw_clock { 40 void __iomem *base; 41 unsigned int id; 42 u32 reg_offset; 43 u32 shift; 44 u32 width; 45 u32 flags; 46 struct clk_hw hw; 47 struct clk_init_data init; 48 }; 49 50 #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 51 52 struct mpfs_cfg_hw_clock { 53 struct clk_divider cfg; 54 struct clk_init_data init; 55 unsigned int id; 56 u32 reg_offset; 57 }; 58 59 struct mpfs_periph_hw_clock { 60 struct clk_gate periph; 61 unsigned int id; 62 }; 63 64 /* 65 * mpfs_clk_lock prevents anything else from writing to the 66 * mpfs clk block while a software locked register is being written. 67 */ 68 static DEFINE_SPINLOCK(mpfs_clk_lock); 69 70 static const struct clk_parent_data mpfs_ext_ref[] = { 71 { .index = 0 }, 72 }; 73 74 static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 75 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 76 { 0, 0 } 77 }; 78 79 static const struct clk_div_table mpfs_div_ahb_table[] = { 80 { 1, 2 }, { 2, 4}, { 3, 8 }, 81 { 0, 0 } 82 }; 83 84 /* 85 * The only two supported reference clock frequencies for the PolarFire SoC are 86 * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. 87 * It therefore only needs to have divider table entries corresponding to 88 * divide by 100 and 125. 89 */ 90 static const struct clk_div_table mpfs_div_rtcref_table[] = { 91 { 100, 100 }, { 125, 125 }, 92 { 0, 0 } 93 }; 94 95 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 96 { 97 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 98 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 99 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 100 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 101 u32 mult, ref_div, postdiv; 102 103 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 104 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 105 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 106 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 107 postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 108 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 109 110 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 111 } 112 113 static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 114 { 115 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 116 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 117 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 118 u32 mult, ref_div; 119 unsigned long rate_before_ctrl; 120 121 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 122 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 123 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 124 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 125 126 rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 127 128 return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 129 msspll_hw->flags); 130 } 131 132 static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 133 { 134 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 135 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 136 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 137 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 138 u32 mult, ref_div, postdiv; 139 int divider_setting; 140 unsigned long rate_before_ctrl, flags; 141 142 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 143 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 144 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 145 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 146 147 rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 148 divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 149 msspll_hw->flags); 150 151 if (divider_setting < 0) 152 return divider_setting; 153 154 spin_lock_irqsave(&mpfs_clk_lock, flags); 155 156 postdiv = readl_relaxed(postdiv_addr); 157 postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); 158 writel_relaxed(postdiv, postdiv_addr); 159 160 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 161 162 return 0; 163 } 164 165 static const struct clk_ops mpfs_clk_msspll_ops = { 166 .recalc_rate = mpfs_clk_msspll_recalc_rate, 167 .round_rate = mpfs_clk_msspll_round_rate, 168 .set_rate = mpfs_clk_msspll_set_rate, 169 }; 170 171 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 172 .id = _id, \ 173 .shift = _shift, \ 174 .width = _width, \ 175 .reg_offset = _offset, \ 176 .flags = _flags, \ 177 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 178 } 179 180 static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 181 CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 182 MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 183 }; 184 185 static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 186 unsigned int num_clks, struct mpfs_clock_data *data) 187 { 188 unsigned int i; 189 int ret; 190 191 for (i = 0; i < num_clks; i++) { 192 struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 193 194 msspll_hw->base = data->msspll_base; 195 ret = devm_clk_hw_register(dev, &msspll_hw->hw); 196 if (ret) 197 return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 198 CLK_MSSPLL); 199 200 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 201 } 202 203 return 0; 204 } 205 206 /* 207 * "CFG" clocks 208 */ 209 210 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 211 .id = _id, \ 212 .cfg.shift = _shift, \ 213 .cfg.width = _width, \ 214 .cfg.table = _table, \ 215 .reg_offset = _offset, \ 216 .cfg.flags = _flags, \ 217 .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ 218 .cfg.lock = &mpfs_clk_lock, \ 219 } 220 221 #define CLK_CPU_OFFSET 0u 222 #define CLK_AXI_OFFSET 1u 223 #define CLK_AHB_OFFSET 2u 224 #define CLK_RTCREF_OFFSET 3u 225 226 static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 227 CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 228 REG_CLOCK_CONFIG_CR), 229 CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 230 REG_CLOCK_CONFIG_CR), 231 CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 232 REG_CLOCK_CONFIG_CR), 233 { 234 .id = CLK_RTCREF, 235 .cfg.shift = 0, 236 .cfg.width = 12, 237 .cfg.table = mpfs_div_rtcref_table, 238 .reg_offset = REG_RTC_CLOCK_CR, 239 .cfg.flags = CLK_DIVIDER_ONE_BASED, 240 .cfg.hw.init = 241 CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0), 242 } 243 }; 244 245 static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 246 unsigned int num_clks, struct mpfs_clock_data *data) 247 { 248 unsigned int i, id; 249 int ret; 250 251 for (i = 0; i < num_clks; i++) { 252 struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 253 254 cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; 255 ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw); 256 if (ret) 257 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 258 cfg_hw->id); 259 260 id = cfg_hw->id; 261 data->hw_data.hws[id] = &cfg_hw->cfg.hw; 262 } 263 264 return 0; 265 } 266 267 /* 268 * peripheral clocks - devices connected to axi or ahb buses. 269 */ 270 271 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 272 .id = _id, \ 273 .periph.bit_idx = _shift, \ 274 .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ 275 _flags), \ 276 .periph.lock = &mpfs_clk_lock, \ 277 } 278 279 #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) 280 281 /* 282 * Critical clocks: 283 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 284 * trap handler 285 * - CLK_MMUART0: reserved by the hss 286 * - CLK_DDRC: provides clock to the ddr subsystem 287 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 288 * if the AHB interface clock is disabled 289 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 290 * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 291 * causes the FPGA fabric to go into reset. 292 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 293 */ 294 295 static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 296 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 297 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 298 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 299 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 300 CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), 301 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 302 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 303 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 304 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 305 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 306 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 307 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 308 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 309 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 310 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 311 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 312 CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 313 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 314 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 315 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 316 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 317 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 318 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 319 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 320 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 321 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 322 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 323 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 324 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 325 }; 326 327 static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 328 int num_clks, struct mpfs_clock_data *data) 329 { 330 unsigned int i, id; 331 int ret; 332 333 for (i = 0; i < num_clks; i++) { 334 struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 335 336 periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; 337 ret = devm_clk_hw_register(dev, &periph_hw->periph.hw); 338 if (ret) 339 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 340 periph_hw->id); 341 342 id = periph_hws[i].id; 343 data->hw_data.hws[id] = &periph_hw->periph.hw; 344 } 345 346 return 0; 347 } 348 349 /* 350 * Peripheral clock resets 351 */ 352 353 #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 354 355 u32 mpfs_reset_read(struct device *dev) 356 { 357 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 358 359 return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 360 } 361 EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 362 363 void mpfs_reset_write(struct device *dev, u32 val) 364 { 365 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 366 367 writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 368 } 369 EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 370 371 static void mpfs_reset_unregister_adev(void *_adev) 372 { 373 struct auxiliary_device *adev = _adev; 374 375 auxiliary_device_delete(adev); 376 } 377 378 static void mpfs_reset_adev_release(struct device *dev) 379 { 380 struct auxiliary_device *adev = to_auxiliary_dev(dev); 381 382 auxiliary_device_uninit(adev); 383 384 kfree(adev); 385 } 386 387 static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 388 { 389 struct auxiliary_device *adev; 390 int ret; 391 392 adev = kzalloc(sizeof(*adev), GFP_KERNEL); 393 if (!adev) 394 return ERR_PTR(-ENOMEM); 395 396 adev->name = "reset-mpfs"; 397 adev->dev.parent = clk_data->dev; 398 adev->dev.release = mpfs_reset_adev_release; 399 adev->id = 666u; 400 401 ret = auxiliary_device_init(adev); 402 if (ret) { 403 kfree(adev); 404 return ERR_PTR(ret); 405 } 406 407 return adev; 408 } 409 410 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 411 { 412 struct auxiliary_device *adev; 413 int ret; 414 415 adev = mpfs_reset_adev_alloc(clk_data); 416 if (IS_ERR(adev)) 417 return PTR_ERR(adev); 418 419 ret = auxiliary_device_add(adev); 420 if (ret) { 421 auxiliary_device_uninit(adev); 422 return ret; 423 } 424 425 return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 426 } 427 428 #else /* !CONFIG_RESET_CONTROLLER */ 429 430 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 431 { 432 return 0; 433 } 434 435 #endif /* !CONFIG_RESET_CONTROLLER */ 436 437 static int mpfs_clk_probe(struct platform_device *pdev) 438 { 439 struct device *dev = &pdev->dev; 440 struct mpfs_clock_data *clk_data; 441 unsigned int num_clks; 442 int ret; 443 444 /* CLK_RESERVED is not part of clock arrays, so add 1 */ 445 num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 446 + ARRAY_SIZE(mpfs_periph_clks) + 1; 447 448 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 449 if (!clk_data) 450 return -ENOMEM; 451 452 clk_data->base = devm_platform_ioremap_resource(pdev, 0); 453 if (IS_ERR(clk_data->base)) 454 return PTR_ERR(clk_data->base); 455 456 clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 457 if (IS_ERR(clk_data->msspll_base)) 458 return PTR_ERR(clk_data->msspll_base); 459 460 clk_data->hw_data.num = num_clks; 461 clk_data->dev = dev; 462 dev_set_drvdata(dev, clk_data); 463 464 ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 465 clk_data); 466 if (ret) 467 return ret; 468 469 ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 470 if (ret) 471 return ret; 472 473 ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 474 clk_data); 475 if (ret) 476 return ret; 477 478 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 479 if (ret) 480 return ret; 481 482 return mpfs_reset_controller_register(clk_data); 483 } 484 485 static const struct of_device_id mpfs_clk_of_match_table[] = { 486 { .compatible = "microchip,mpfs-clkcfg", }, 487 {} 488 }; 489 MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); 490 491 static struct platform_driver mpfs_clk_driver = { 492 .probe = mpfs_clk_probe, 493 .driver = { 494 .name = "microchip-mpfs-clkcfg", 495 .of_match_table = mpfs_clk_of_match_table, 496 }, 497 }; 498 499 static int __init clk_mpfs_init(void) 500 { 501 return platform_driver_register(&mpfs_clk_driver); 502 } 503 core_initcall(clk_mpfs_init); 504 505 static void __exit clk_mpfs_exit(void) 506 { 507 platform_driver_unregister(&mpfs_clk_driver); 508 } 509 module_exit(clk_mpfs_exit); 510 511 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 512 MODULE_LICENSE("GPL v2"); 513