1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Daire McNamara,<daire.mcnamara@microchip.com> 4 * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5 */ 6 #include <linux/auxiliary_bus.h> 7 #include <linux/clk-provider.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <dt-bindings/clock/microchip,mpfs-clock.h> 13 #include <soc/microchip/mpfs.h> 14 15 /* address offset of control registers */ 16 #define REG_MSSPLL_REF_CR 0x08u 17 #define REG_MSSPLL_POSTDIV_CR 0x10u 18 #define REG_MSSPLL_SSCG_2_CR 0x2Cu 19 #define REG_CLOCK_CONFIG_CR 0x08u 20 #define REG_RTC_CLOCK_CR 0x0Cu 21 #define REG_SUBBLK_CLOCK_CR 0x84u 22 #define REG_SUBBLK_RESET_CR 0x88u 23 24 #define MSSPLL_FBDIV_SHIFT 0x00u 25 #define MSSPLL_FBDIV_WIDTH 0x0Cu 26 #define MSSPLL_REFDIV_SHIFT 0x08u 27 #define MSSPLL_REFDIV_WIDTH 0x06u 28 #define MSSPLL_POSTDIV_SHIFT 0x08u 29 #define MSSPLL_POSTDIV_WIDTH 0x07u 30 #define MSSPLL_FIXED_DIV 4u 31 32 struct mpfs_clock_data { 33 struct device *dev; 34 void __iomem *base; 35 void __iomem *msspll_base; 36 struct clk_hw_onecell_data hw_data; 37 }; 38 39 struct mpfs_msspll_hw_clock { 40 void __iomem *base; 41 unsigned int id; 42 u32 reg_offset; 43 u32 shift; 44 u32 width; 45 u32 flags; 46 struct clk_hw hw; 47 struct clk_init_data init; 48 }; 49 50 #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 51 52 struct mpfs_cfg_clock { 53 const struct clk_div_table *table; 54 unsigned int id; 55 u32 reg_offset; 56 u8 shift; 57 u8 width; 58 u8 flags; 59 }; 60 61 struct mpfs_cfg_hw_clock { 62 struct mpfs_cfg_clock cfg; 63 void __iomem *sys_base; 64 struct clk_hw hw; 65 struct clk_init_data init; 66 }; 67 68 #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) 69 70 struct mpfs_periph_clock { 71 unsigned int id; 72 u8 shift; 73 }; 74 75 struct mpfs_periph_hw_clock { 76 struct mpfs_periph_clock periph; 77 void __iomem *sys_base; 78 struct clk_hw hw; 79 }; 80 81 #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 82 83 /* 84 * mpfs_clk_lock prevents anything else from writing to the 85 * mpfs clk block while a software locked register is being written. 86 */ 87 static DEFINE_SPINLOCK(mpfs_clk_lock); 88 89 static const struct clk_parent_data mpfs_ext_ref[] = { 90 { .index = 0 }, 91 }; 92 93 static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 94 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 95 { 0, 0 } 96 }; 97 98 static const struct clk_div_table mpfs_div_ahb_table[] = { 99 { 1, 2 }, { 2, 4}, { 3, 8 }, 100 { 0, 0 } 101 }; 102 103 /* 104 * The only two supported reference clock frequencies for the PolarFire SoC are 105 * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. 106 * It therefore only needs to have divider table entries corresponding to 107 * divide by 100 and 125. 108 */ 109 static const struct clk_div_table mpfs_div_rtcref_table[] = { 110 { 100, 100 }, { 125, 125 }, 111 { 0, 0 } 112 }; 113 114 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 115 { 116 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 118 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 119 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 120 u32 mult, ref_div, postdiv; 121 122 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 123 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 124 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 125 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 126 postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 127 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 128 129 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 130 } 131 132 static const struct clk_ops mpfs_clk_msspll_ops = { 133 .recalc_rate = mpfs_clk_msspll_recalc_rate, 134 }; 135 136 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 137 .id = _id, \ 138 .shift = _shift, \ 139 .width = _width, \ 140 .reg_offset = _offset, \ 141 .flags = _flags, \ 142 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 143 } 144 145 static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 146 CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 147 MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 148 }; 149 150 static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, 151 void __iomem *base) 152 { 153 msspll_hw->base = base; 154 155 return devm_clk_hw_register(dev, &msspll_hw->hw); 156 } 157 158 static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 159 unsigned int num_clks, struct mpfs_clock_data *data) 160 { 161 void __iomem *base = data->msspll_base; 162 unsigned int i; 163 int ret; 164 165 for (i = 0; i < num_clks; i++) { 166 struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 167 168 ret = mpfs_clk_register_msspll(dev, msspll_hw, base); 169 if (ret) 170 return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 171 CLK_MSSPLL); 172 173 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 174 } 175 176 return 0; 177 } 178 179 /* 180 * "CFG" clocks 181 */ 182 183 static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) 184 { 185 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 186 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 187 void __iomem *base_addr = cfg_hw->sys_base; 188 u32 val; 189 190 val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; 191 val &= clk_div_mask(cfg->width); 192 193 return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); 194 } 195 196 static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 197 { 198 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 199 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 200 201 return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); 202 } 203 204 static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 205 { 206 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 207 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 208 void __iomem *base_addr = cfg_hw->sys_base; 209 unsigned long flags; 210 u32 val; 211 int divider_setting; 212 213 divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); 214 215 if (divider_setting < 0) 216 return divider_setting; 217 218 spin_lock_irqsave(&mpfs_clk_lock, flags); 219 val = readl_relaxed(base_addr + cfg->reg_offset); 220 val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); 221 val |= divider_setting << cfg->shift; 222 writel_relaxed(val, base_addr + cfg->reg_offset); 223 224 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 225 226 return 0; 227 } 228 229 static const struct clk_ops mpfs_clk_cfg_ops = { 230 .recalc_rate = mpfs_cfg_clk_recalc_rate, 231 .round_rate = mpfs_cfg_clk_round_rate, 232 .set_rate = mpfs_cfg_clk_set_rate, 233 }; 234 235 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 236 .cfg.id = _id, \ 237 .cfg.shift = _shift, \ 238 .cfg.width = _width, \ 239 .cfg.table = _table, \ 240 .cfg.reg_offset = _offset, \ 241 .cfg.flags = _flags, \ 242 .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ 243 } 244 245 #define CLK_CPU_OFFSET 0u 246 #define CLK_AXI_OFFSET 1u 247 #define CLK_AHB_OFFSET 2u 248 #define CLK_RTCREF_OFFSET 3u 249 250 static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 251 CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 252 REG_CLOCK_CONFIG_CR), 253 CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 254 REG_CLOCK_CONFIG_CR), 255 CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 256 REG_CLOCK_CONFIG_CR), 257 { 258 .cfg.id = CLK_RTCREF, 259 .cfg.shift = 0, 260 .cfg.width = 12, 261 .cfg.table = mpfs_div_rtcref_table, 262 .cfg.reg_offset = REG_RTC_CLOCK_CR, 263 .cfg.flags = CLK_DIVIDER_ONE_BASED, 264 .hw.init = 265 CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), 266 } 267 }; 268 269 static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, 270 void __iomem *sys_base) 271 { 272 cfg_hw->sys_base = sys_base; 273 274 return devm_clk_hw_register(dev, &cfg_hw->hw); 275 } 276 277 static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 278 unsigned int num_clks, struct mpfs_clock_data *data) 279 { 280 void __iomem *sys_base = data->base; 281 unsigned int i, id; 282 int ret; 283 284 for (i = 0; i < num_clks; i++) { 285 struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 286 287 ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); 288 if (ret) 289 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 290 cfg_hw->cfg.id); 291 292 id = cfg_hw->cfg.id; 293 data->hw_data.hws[id] = &cfg_hw->hw; 294 } 295 296 return 0; 297 } 298 299 /* 300 * peripheral clocks - devices connected to axi or ahb buses. 301 */ 302 303 static int mpfs_periph_clk_enable(struct clk_hw *hw) 304 { 305 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 306 struct mpfs_periph_clock *periph = &periph_hw->periph; 307 void __iomem *base_addr = periph_hw->sys_base; 308 u32 reg, val; 309 unsigned long flags; 310 311 spin_lock_irqsave(&mpfs_clk_lock, flags); 312 313 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 314 val = reg | (1u << periph->shift); 315 writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 316 317 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 318 319 return 0; 320 } 321 322 static void mpfs_periph_clk_disable(struct clk_hw *hw) 323 { 324 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 325 struct mpfs_periph_clock *periph = &periph_hw->periph; 326 void __iomem *base_addr = periph_hw->sys_base; 327 u32 reg, val; 328 unsigned long flags; 329 330 spin_lock_irqsave(&mpfs_clk_lock, flags); 331 332 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 333 val = reg & ~(1u << periph->shift); 334 writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 335 336 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 337 } 338 339 static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 340 { 341 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 342 struct mpfs_periph_clock *periph = &periph_hw->periph; 343 void __iomem *base_addr = periph_hw->sys_base; 344 u32 reg; 345 346 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 347 if (reg & (1u << periph->shift)) 348 return 1; 349 350 return 0; 351 } 352 353 static const struct clk_ops mpfs_periph_clk_ops = { 354 .enable = mpfs_periph_clk_enable, 355 .disable = mpfs_periph_clk_disable, 356 .is_enabled = mpfs_periph_clk_is_enabled, 357 }; 358 359 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 360 .periph.id = _id, \ 361 .periph.shift = _shift, \ 362 .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 363 _flags), \ 364 } 365 366 #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw) 367 368 /* 369 * Critical clocks: 370 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 371 * trap handler 372 * - CLK_MMUART0: reserved by the hss 373 * - CLK_DDRC: provides clock to the ddr subsystem 374 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 375 * if the AHB interface clock is disabled 376 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 377 * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 378 * causes the FPGA fabric to go into reset. 379 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 380 */ 381 382 static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 383 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 384 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 385 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 386 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 387 CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), 388 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 389 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 390 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 391 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 392 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 393 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 394 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 395 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 396 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 397 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 398 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 399 CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 400 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 401 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 402 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 403 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 404 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 405 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 406 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 407 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 408 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 409 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 410 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 411 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 412 }; 413 414 static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, 415 void __iomem *sys_base) 416 { 417 periph_hw->sys_base = sys_base; 418 419 return devm_clk_hw_register(dev, &periph_hw->hw); 420 } 421 422 static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 423 int num_clks, struct mpfs_clock_data *data) 424 { 425 void __iomem *sys_base = data->base; 426 unsigned int i, id; 427 int ret; 428 429 for (i = 0; i < num_clks; i++) { 430 struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 431 432 ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); 433 if (ret) 434 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 435 periph_hw->periph.id); 436 437 id = periph_hws[i].periph.id; 438 data->hw_data.hws[id] = &periph_hw->hw; 439 } 440 441 return 0; 442 } 443 444 /* 445 * Peripheral clock resets 446 */ 447 448 #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 449 450 u32 mpfs_reset_read(struct device *dev) 451 { 452 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 453 454 return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 455 } 456 EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 457 458 void mpfs_reset_write(struct device *dev, u32 val) 459 { 460 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 461 462 writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 463 } 464 EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 465 466 static void mpfs_reset_unregister_adev(void *_adev) 467 { 468 struct auxiliary_device *adev = _adev; 469 470 auxiliary_device_delete(adev); 471 } 472 473 static void mpfs_reset_adev_release(struct device *dev) 474 { 475 struct auxiliary_device *adev = to_auxiliary_dev(dev); 476 477 auxiliary_device_uninit(adev); 478 479 kfree(adev); 480 } 481 482 static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 483 { 484 struct auxiliary_device *adev; 485 int ret; 486 487 adev = kzalloc(sizeof(*adev), GFP_KERNEL); 488 if (!adev) 489 return ERR_PTR(-ENOMEM); 490 491 adev->name = "reset-mpfs"; 492 adev->dev.parent = clk_data->dev; 493 adev->dev.release = mpfs_reset_adev_release; 494 adev->id = 666u; 495 496 ret = auxiliary_device_init(adev); 497 if (ret) { 498 kfree(adev); 499 return ERR_PTR(ret); 500 } 501 502 return adev; 503 } 504 505 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 506 { 507 struct auxiliary_device *adev; 508 int ret; 509 510 adev = mpfs_reset_adev_alloc(clk_data); 511 if (IS_ERR(adev)) 512 return PTR_ERR(adev); 513 514 ret = auxiliary_device_add(adev); 515 if (ret) { 516 auxiliary_device_uninit(adev); 517 return ret; 518 } 519 520 return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 521 } 522 523 #else /* !CONFIG_RESET_CONTROLLER */ 524 525 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 526 { 527 return 0; 528 } 529 530 #endif /* !CONFIG_RESET_CONTROLLER */ 531 532 static int mpfs_clk_probe(struct platform_device *pdev) 533 { 534 struct device *dev = &pdev->dev; 535 struct mpfs_clock_data *clk_data; 536 unsigned int num_clks; 537 int ret; 538 539 /* CLK_RESERVED is not part of clock arrays, so add 1 */ 540 num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 541 + ARRAY_SIZE(mpfs_periph_clks) + 1; 542 543 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 544 if (!clk_data) 545 return -ENOMEM; 546 547 clk_data->base = devm_platform_ioremap_resource(pdev, 0); 548 if (IS_ERR(clk_data->base)) 549 return PTR_ERR(clk_data->base); 550 551 clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 552 if (IS_ERR(clk_data->msspll_base)) 553 return PTR_ERR(clk_data->msspll_base); 554 555 clk_data->hw_data.num = num_clks; 556 clk_data->dev = dev; 557 dev_set_drvdata(dev, clk_data); 558 559 ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 560 clk_data); 561 if (ret) 562 return ret; 563 564 ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 565 if (ret) 566 return ret; 567 568 ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 569 clk_data); 570 if (ret) 571 return ret; 572 573 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 574 if (ret) 575 return ret; 576 577 return mpfs_reset_controller_register(clk_data); 578 } 579 580 static const struct of_device_id mpfs_clk_of_match_table[] = { 581 { .compatible = "microchip,mpfs-clkcfg", }, 582 {} 583 }; 584 MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); 585 586 static struct platform_driver mpfs_clk_driver = { 587 .probe = mpfs_clk_probe, 588 .driver = { 589 .name = "microchip-mpfs-clkcfg", 590 .of_match_table = mpfs_clk_of_match_table, 591 }, 592 }; 593 594 static int __init clk_mpfs_init(void) 595 { 596 return platform_driver_register(&mpfs_clk_driver); 597 } 598 core_initcall(clk_mpfs_init); 599 600 static void __exit clk_mpfs_exit(void) 601 { 602 platform_driver_unregister(&mpfs_clk_driver); 603 } 604 module_exit(clk_mpfs_exit); 605 606 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 607 MODULE_LICENSE("GPL v2"); 608