1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Daire McNamara,<daire.mcnamara@microchip.com> 4 * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5 */ 6 #include <linux/clk-provider.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/slab.h> 11 #include <dt-bindings/clock/microchip,mpfs-clock.h> 12 13 /* address offset of control registers */ 14 #define REG_CLOCK_CONFIG_CR 0x08u 15 #define REG_SUBBLK_CLOCK_CR 0x84u 16 #define REG_SUBBLK_RESET_CR 0x88u 17 18 struct mpfs_clock_data { 19 void __iomem *base; 20 struct clk_hw_onecell_data hw_data; 21 }; 22 23 struct mpfs_cfg_clock { 24 const struct clk_div_table *table; 25 unsigned int id; 26 u8 shift; 27 u8 width; 28 }; 29 30 struct mpfs_cfg_hw_clock { 31 struct mpfs_cfg_clock cfg; 32 void __iomem *sys_base; 33 struct clk_hw hw; 34 struct clk_init_data init; 35 }; 36 37 #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) 38 39 struct mpfs_periph_clock { 40 unsigned int id; 41 u8 shift; 42 }; 43 44 struct mpfs_periph_hw_clock { 45 struct mpfs_periph_clock periph; 46 void __iomem *sys_base; 47 struct clk_hw hw; 48 }; 49 50 #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 51 52 /* 53 * mpfs_clk_lock prevents anything else from writing to the 54 * mpfs clk block while a software locked register is being written. 55 */ 56 static DEFINE_SPINLOCK(mpfs_clk_lock); 57 58 static const struct clk_parent_data mpfs_cfg_parent[] = { 59 { .index = 0 }, 60 }; 61 62 static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 63 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 64 { 0, 0 } 65 }; 66 67 static const struct clk_div_table mpfs_div_ahb_table[] = { 68 { 1, 2 }, { 2, 4}, { 3, 8 }, 69 { 0, 0 } 70 }; 71 72 static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) 73 { 74 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 75 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 76 void __iomem *base_addr = cfg_hw->sys_base; 77 u32 val; 78 79 val = readl_relaxed(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift; 80 val &= clk_div_mask(cfg->width); 81 82 return prate / (1u << val); 83 } 84 85 static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 86 { 87 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 88 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 89 90 return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); 91 } 92 93 static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 94 { 95 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 96 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 97 void __iomem *base_addr = cfg_hw->sys_base; 98 unsigned long flags; 99 u32 val; 100 int divider_setting; 101 102 divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); 103 104 if (divider_setting < 0) 105 return divider_setting; 106 107 spin_lock_irqsave(&mpfs_clk_lock, flags); 108 109 val = readl_relaxed(base_addr + REG_CLOCK_CONFIG_CR); 110 val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); 111 val |= divider_setting << cfg->shift; 112 writel_relaxed(val, base_addr + REG_CLOCK_CONFIG_CR); 113 114 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 115 116 return 0; 117 } 118 119 static const struct clk_ops mpfs_clk_cfg_ops = { 120 .recalc_rate = mpfs_cfg_clk_recalc_rate, 121 .round_rate = mpfs_cfg_clk_round_rate, 122 .set_rate = mpfs_cfg_clk_set_rate, 123 }; 124 125 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags) { \ 126 .cfg.id = _id, \ 127 .cfg.shift = _shift, \ 128 .cfg.width = _width, \ 129 .cfg.table = _table, \ 130 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_cfg_ops, \ 131 _flags), \ 132 } 133 134 static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 135 CLK_CFG(CLK_CPU, "clk_cpu", mpfs_cfg_parent, 0, 2, mpfs_div_cpu_axi_table, 0), 136 CLK_CFG(CLK_AXI, "clk_axi", mpfs_cfg_parent, 2, 2, mpfs_div_cpu_axi_table, 0), 137 CLK_CFG(CLK_AHB, "clk_ahb", mpfs_cfg_parent, 4, 2, mpfs_div_ahb_table, 0), 138 }; 139 140 static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, 141 void __iomem *sys_base) 142 { 143 cfg_hw->sys_base = sys_base; 144 145 return devm_clk_hw_register(dev, &cfg_hw->hw); 146 } 147 148 static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 149 unsigned int num_clks, struct mpfs_clock_data *data) 150 { 151 void __iomem *sys_base = data->base; 152 unsigned int i, id; 153 int ret; 154 155 for (i = 0; i < num_clks; i++) { 156 struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 157 158 ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); 159 if (ret) 160 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 161 cfg_hw->cfg.id); 162 163 id = cfg_hws[i].cfg.id; 164 data->hw_data.hws[id] = &cfg_hw->hw; 165 } 166 167 return 0; 168 } 169 170 static int mpfs_periph_clk_enable(struct clk_hw *hw) 171 { 172 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 173 struct mpfs_periph_clock *periph = &periph_hw->periph; 174 void __iomem *base_addr = periph_hw->sys_base; 175 u32 reg, val; 176 unsigned long flags; 177 178 spin_lock_irqsave(&mpfs_clk_lock, flags); 179 180 reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); 181 val = reg & ~(1u << periph->shift); 182 writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); 183 184 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 185 val = reg | (1u << periph->shift); 186 writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 187 188 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 189 190 return 0; 191 } 192 193 static void mpfs_periph_clk_disable(struct clk_hw *hw) 194 { 195 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 196 struct mpfs_periph_clock *periph = &periph_hw->periph; 197 void __iomem *base_addr = periph_hw->sys_base; 198 u32 reg, val; 199 unsigned long flags; 200 201 spin_lock_irqsave(&mpfs_clk_lock, flags); 202 203 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 204 val = reg & ~(1u << periph->shift); 205 writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 206 207 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 208 } 209 210 static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 211 { 212 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 213 struct mpfs_periph_clock *periph = &periph_hw->periph; 214 void __iomem *base_addr = periph_hw->sys_base; 215 u32 reg; 216 217 reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); 218 if ((reg & (1u << periph->shift)) == 0u) { 219 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 220 if (reg & (1u << periph->shift)) 221 return 1; 222 } 223 224 return 0; 225 } 226 227 static const struct clk_ops mpfs_periph_clk_ops = { 228 .enable = mpfs_periph_clk_enable, 229 .disable = mpfs_periph_clk_disable, 230 .is_enabled = mpfs_periph_clk_is_enabled, 231 }; 232 233 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 234 .periph.id = _id, \ 235 .periph.shift = _shift, \ 236 .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 237 _flags), \ 238 } 239 240 #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].hw) 241 242 /* 243 * Critical clocks: 244 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 245 * trap handler 246 * - CLK_MMUART0: reserved by the hss 247 * - CLK_DDRC: provides clock to the ddr subsystem 248 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 249 * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 250 * causes the FPGA fabric to go into reset. 251 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 252 */ 253 254 static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 255 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 256 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 257 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 258 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 259 CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(AHB), 4, 0), 260 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 261 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 262 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 263 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 264 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 265 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 266 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 267 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 268 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 269 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 270 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 271 CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 272 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, 0), 273 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 274 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 275 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 276 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 277 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 278 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 279 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 280 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 281 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 282 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 283 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 284 }; 285 286 static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, 287 void __iomem *sys_base) 288 { 289 periph_hw->sys_base = sys_base; 290 291 return devm_clk_hw_register(dev, &periph_hw->hw); 292 } 293 294 static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 295 int num_clks, struct mpfs_clock_data *data) 296 { 297 void __iomem *sys_base = data->base; 298 unsigned int i, id; 299 int ret; 300 301 for (i = 0; i < num_clks; i++) { 302 struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 303 304 ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); 305 if (ret) 306 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 307 periph_hw->periph.id); 308 309 id = periph_hws[i].periph.id; 310 data->hw_data.hws[id] = &periph_hw->hw; 311 } 312 313 return 0; 314 } 315 316 static int mpfs_clk_probe(struct platform_device *pdev) 317 { 318 struct device *dev = &pdev->dev; 319 struct mpfs_clock_data *clk_data; 320 unsigned int num_clks; 321 int ret; 322 323 /* CLK_RESERVED is not part of cfg_clks nor periph_clks, so add 1 */ 324 num_clks = ARRAY_SIZE(mpfs_cfg_clks) + ARRAY_SIZE(mpfs_periph_clks) + 1; 325 326 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 327 if (!clk_data) 328 return -ENOMEM; 329 330 clk_data->base = devm_platform_ioremap_resource(pdev, 0); 331 if (IS_ERR(clk_data->base)) 332 return PTR_ERR(clk_data->base); 333 334 clk_data->hw_data.num = num_clks; 335 336 ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 337 if (ret) 338 return ret; 339 340 ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 341 clk_data); 342 if (ret) 343 return ret; 344 345 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 346 if (ret) 347 return ret; 348 349 return ret; 350 } 351 352 static const struct of_device_id mpfs_clk_of_match_table[] = { 353 { .compatible = "microchip,mpfs-clkcfg", }, 354 {} 355 }; 356 MODULE_DEVICE_TABLE(of, mpfs_clk_match_table); 357 358 static struct platform_driver mpfs_clk_driver = { 359 .probe = mpfs_clk_probe, 360 .driver = { 361 .name = "microchip-mpfs-clkcfg", 362 .of_match_table = mpfs_clk_of_match_table, 363 }, 364 }; 365 366 static int __init clk_mpfs_init(void) 367 { 368 return platform_driver_register(&mpfs_clk_driver); 369 } 370 core_initcall(clk_mpfs_init); 371 372 static void __exit clk_mpfs_exit(void) 373 { 374 platform_driver_unregister(&mpfs_clk_driver); 375 } 376 module_exit(clk_mpfs_exit); 377 378 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 379 MODULE_LICENSE("GPL v2"); 380