1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Daire McNamara,<daire.mcnamara@microchip.com> 4 * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5 */ 6 #include <linux/auxiliary_bus.h> 7 #include <linux/clk-provider.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <dt-bindings/clock/microchip,mpfs-clock.h> 13 #include <soc/microchip/mpfs.h> 14 15 /* address offset of control registers */ 16 #define REG_MSSPLL_REF_CR 0x08u 17 #define REG_MSSPLL_POSTDIV_CR 0x10u 18 #define REG_MSSPLL_SSCG_2_CR 0x2Cu 19 #define REG_CLOCK_CONFIG_CR 0x08u 20 #define REG_RTC_CLOCK_CR 0x0Cu 21 #define REG_SUBBLK_CLOCK_CR 0x84u 22 #define REG_SUBBLK_RESET_CR 0x88u 23 24 #define MSSPLL_FBDIV_SHIFT 0x00u 25 #define MSSPLL_FBDIV_WIDTH 0x0Cu 26 #define MSSPLL_REFDIV_SHIFT 0x08u 27 #define MSSPLL_REFDIV_WIDTH 0x06u 28 #define MSSPLL_POSTDIV_SHIFT 0x08u 29 #define MSSPLL_POSTDIV_WIDTH 0x07u 30 #define MSSPLL_FIXED_DIV 4u 31 32 struct mpfs_clock_data { 33 struct device *dev; 34 void __iomem *base; 35 void __iomem *msspll_base; 36 struct clk_hw_onecell_data hw_data; 37 }; 38 39 struct mpfs_msspll_hw_clock { 40 void __iomem *base; 41 unsigned int id; 42 u32 reg_offset; 43 u32 shift; 44 u32 width; 45 u32 flags; 46 struct clk_hw hw; 47 struct clk_init_data init; 48 }; 49 50 #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 51 52 struct mpfs_cfg_clock { 53 void __iomem *reg; 54 const struct clk_div_table *table; 55 u8 shift; 56 u8 width; 57 u8 flags; 58 }; 59 60 struct mpfs_cfg_hw_clock { 61 struct mpfs_cfg_clock cfg; 62 struct clk_hw hw; 63 struct clk_init_data init; 64 unsigned int id; 65 u32 reg_offset; 66 }; 67 68 #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) 69 70 struct mpfs_periph_clock { 71 void __iomem *reg; 72 u8 shift; 73 }; 74 75 struct mpfs_periph_hw_clock { 76 struct mpfs_periph_clock periph; 77 struct clk_hw hw; 78 unsigned int id; 79 }; 80 81 #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 82 83 /* 84 * mpfs_clk_lock prevents anything else from writing to the 85 * mpfs clk block while a software locked register is being written. 86 */ 87 static DEFINE_SPINLOCK(mpfs_clk_lock); 88 89 static const struct clk_parent_data mpfs_ext_ref[] = { 90 { .index = 0 }, 91 }; 92 93 static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 94 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 95 { 0, 0 } 96 }; 97 98 static const struct clk_div_table mpfs_div_ahb_table[] = { 99 { 1, 2 }, { 2, 4}, { 3, 8 }, 100 { 0, 0 } 101 }; 102 103 /* 104 * The only two supported reference clock frequencies for the PolarFire SoC are 105 * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. 106 * It therefore only needs to have divider table entries corresponding to 107 * divide by 100 and 125. 108 */ 109 static const struct clk_div_table mpfs_div_rtcref_table[] = { 110 { 100, 100 }, { 125, 125 }, 111 { 0, 0 } 112 }; 113 114 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 115 { 116 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 118 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 119 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 120 u32 mult, ref_div, postdiv; 121 122 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 123 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 124 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 125 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 126 postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 127 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 128 129 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 130 } 131 132 static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 133 { 134 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 135 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 136 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 137 u32 mult, ref_div; 138 unsigned long rate_before_ctrl; 139 140 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 141 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 142 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 143 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 144 145 rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 146 147 return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 148 msspll_hw->flags); 149 } 150 151 static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 152 { 153 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 154 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 155 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 156 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 157 u32 mult, ref_div, postdiv; 158 int divider_setting; 159 unsigned long rate_before_ctrl, flags; 160 161 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 162 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 163 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 164 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 165 166 rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 167 divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 168 msspll_hw->flags); 169 170 if (divider_setting < 0) 171 return divider_setting; 172 173 spin_lock_irqsave(&mpfs_clk_lock, flags); 174 175 postdiv = readl_relaxed(postdiv_addr); 176 postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); 177 writel_relaxed(postdiv, postdiv_addr); 178 179 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 180 181 return 0; 182 } 183 184 static const struct clk_ops mpfs_clk_msspll_ops = { 185 .recalc_rate = mpfs_clk_msspll_recalc_rate, 186 .round_rate = mpfs_clk_msspll_round_rate, 187 .set_rate = mpfs_clk_msspll_set_rate, 188 }; 189 190 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 191 .id = _id, \ 192 .shift = _shift, \ 193 .width = _width, \ 194 .reg_offset = _offset, \ 195 .flags = _flags, \ 196 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 197 } 198 199 static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 200 CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 201 MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 202 }; 203 204 static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, 205 void __iomem *base) 206 { 207 msspll_hw->base = base; 208 209 return devm_clk_hw_register(dev, &msspll_hw->hw); 210 } 211 212 static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 213 unsigned int num_clks, struct mpfs_clock_data *data) 214 { 215 unsigned int i; 216 int ret; 217 218 for (i = 0; i < num_clks; i++) { 219 struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 220 221 ret = mpfs_clk_register_msspll(dev, msspll_hw, data->msspll_base); 222 if (ret) 223 return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 224 CLK_MSSPLL); 225 226 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 227 } 228 229 return 0; 230 } 231 232 /* 233 * "CFG" clocks 234 */ 235 236 static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) 237 { 238 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 239 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 240 u32 val; 241 242 val = readl_relaxed(cfg->reg) >> cfg->shift; 243 val &= clk_div_mask(cfg->width); 244 245 return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); 246 } 247 248 static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 249 { 250 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 251 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 252 253 return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); 254 } 255 256 static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 257 { 258 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 259 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 260 unsigned long flags; 261 u32 val; 262 int divider_setting; 263 264 divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); 265 266 if (divider_setting < 0) 267 return divider_setting; 268 269 spin_lock_irqsave(&mpfs_clk_lock, flags); 270 val = readl_relaxed(cfg->reg); 271 val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); 272 val |= divider_setting << cfg->shift; 273 writel_relaxed(val, cfg->reg); 274 275 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 276 277 return 0; 278 } 279 280 static const struct clk_ops mpfs_clk_cfg_ops = { 281 .recalc_rate = mpfs_cfg_clk_recalc_rate, 282 .round_rate = mpfs_cfg_clk_round_rate, 283 .set_rate = mpfs_cfg_clk_set_rate, 284 }; 285 286 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 287 .id = _id, \ 288 .cfg.shift = _shift, \ 289 .cfg.width = _width, \ 290 .cfg.table = _table, \ 291 .reg_offset = _offset, \ 292 .cfg.flags = _flags, \ 293 .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ 294 } 295 296 #define CLK_CPU_OFFSET 0u 297 #define CLK_AXI_OFFSET 1u 298 #define CLK_AHB_OFFSET 2u 299 #define CLK_RTCREF_OFFSET 3u 300 301 static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 302 CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 303 REG_CLOCK_CONFIG_CR), 304 CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 305 REG_CLOCK_CONFIG_CR), 306 CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 307 REG_CLOCK_CONFIG_CR), 308 { 309 .id = CLK_RTCREF, 310 .cfg.shift = 0, 311 .cfg.width = 12, 312 .cfg.table = mpfs_div_rtcref_table, 313 .reg_offset = REG_RTC_CLOCK_CR, 314 .cfg.flags = CLK_DIVIDER_ONE_BASED, 315 .hw.init = 316 CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), 317 } 318 }; 319 320 static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, 321 void __iomem *base) 322 { 323 cfg_hw->cfg.reg = base + cfg_hw->reg_offset; 324 325 return devm_clk_hw_register(dev, &cfg_hw->hw); 326 } 327 328 static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 329 unsigned int num_clks, struct mpfs_clock_data *data) 330 { 331 unsigned int i, id; 332 int ret; 333 334 for (i = 0; i < num_clks; i++) { 335 struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 336 337 ret = mpfs_clk_register_cfg(dev, cfg_hw, data->base); 338 if (ret) 339 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 340 cfg_hw->id); 341 342 id = cfg_hw->id; 343 data->hw_data.hws[id] = &cfg_hw->hw; 344 } 345 346 return 0; 347 } 348 349 /* 350 * peripheral clocks - devices connected to axi or ahb buses. 351 */ 352 353 static int mpfs_periph_clk_enable(struct clk_hw *hw) 354 { 355 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 356 struct mpfs_periph_clock *periph = &periph_hw->periph; 357 u32 reg, val; 358 unsigned long flags; 359 360 spin_lock_irqsave(&mpfs_clk_lock, flags); 361 362 reg = readl_relaxed(periph->reg); 363 val = reg | (1u << periph->shift); 364 writel_relaxed(val, periph->reg); 365 366 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 367 368 return 0; 369 } 370 371 static void mpfs_periph_clk_disable(struct clk_hw *hw) 372 { 373 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 374 struct mpfs_periph_clock *periph = &periph_hw->periph; 375 u32 reg, val; 376 unsigned long flags; 377 378 spin_lock_irqsave(&mpfs_clk_lock, flags); 379 380 reg = readl_relaxed(periph->reg); 381 val = reg & ~(1u << periph->shift); 382 writel_relaxed(val, periph->reg); 383 384 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 385 } 386 387 static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 388 { 389 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 390 struct mpfs_periph_clock *periph = &periph_hw->periph; 391 u32 reg; 392 393 reg = readl_relaxed(periph->reg); 394 if (reg & (1u << periph->shift)) 395 return 1; 396 397 return 0; 398 } 399 400 static const struct clk_ops mpfs_periph_clk_ops = { 401 .enable = mpfs_periph_clk_enable, 402 .disable = mpfs_periph_clk_disable, 403 .is_enabled = mpfs_periph_clk_is_enabled, 404 }; 405 406 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 407 .id = _id, \ 408 .periph.shift = _shift, \ 409 .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 410 _flags), \ 411 } 412 413 #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw) 414 415 /* 416 * Critical clocks: 417 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 418 * trap handler 419 * - CLK_MMUART0: reserved by the hss 420 * - CLK_DDRC: provides clock to the ddr subsystem 421 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 422 * if the AHB interface clock is disabled 423 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 424 * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 425 * causes the FPGA fabric to go into reset. 426 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 427 */ 428 429 static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 430 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 431 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 432 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 433 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 434 CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), 435 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 436 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 437 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 438 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 439 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 440 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 441 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 442 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 443 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 444 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 445 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 446 CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 447 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 448 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 449 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 450 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 451 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 452 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 453 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 454 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 455 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 456 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 457 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 458 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 459 }; 460 461 static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, 462 void __iomem *base) 463 { 464 periph_hw->periph.reg = base + REG_SUBBLK_CLOCK_CR; 465 466 return devm_clk_hw_register(dev, &periph_hw->hw); 467 } 468 469 static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 470 int num_clks, struct mpfs_clock_data *data) 471 { 472 unsigned int i, id; 473 int ret; 474 475 for (i = 0; i < num_clks; i++) { 476 struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 477 478 ret = mpfs_clk_register_periph(dev, periph_hw, data->base); 479 if (ret) 480 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 481 periph_hw->id); 482 483 id = periph_hws[i].id; 484 data->hw_data.hws[id] = &periph_hw->hw; 485 } 486 487 return 0; 488 } 489 490 /* 491 * Peripheral clock resets 492 */ 493 494 #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 495 496 u32 mpfs_reset_read(struct device *dev) 497 { 498 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 499 500 return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 501 } 502 EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 503 504 void mpfs_reset_write(struct device *dev, u32 val) 505 { 506 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 507 508 writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 509 } 510 EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 511 512 static void mpfs_reset_unregister_adev(void *_adev) 513 { 514 struct auxiliary_device *adev = _adev; 515 516 auxiliary_device_delete(adev); 517 } 518 519 static void mpfs_reset_adev_release(struct device *dev) 520 { 521 struct auxiliary_device *adev = to_auxiliary_dev(dev); 522 523 auxiliary_device_uninit(adev); 524 525 kfree(adev); 526 } 527 528 static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 529 { 530 struct auxiliary_device *adev; 531 int ret; 532 533 adev = kzalloc(sizeof(*adev), GFP_KERNEL); 534 if (!adev) 535 return ERR_PTR(-ENOMEM); 536 537 adev->name = "reset-mpfs"; 538 adev->dev.parent = clk_data->dev; 539 adev->dev.release = mpfs_reset_adev_release; 540 adev->id = 666u; 541 542 ret = auxiliary_device_init(adev); 543 if (ret) { 544 kfree(adev); 545 return ERR_PTR(ret); 546 } 547 548 return adev; 549 } 550 551 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 552 { 553 struct auxiliary_device *adev; 554 int ret; 555 556 adev = mpfs_reset_adev_alloc(clk_data); 557 if (IS_ERR(adev)) 558 return PTR_ERR(adev); 559 560 ret = auxiliary_device_add(adev); 561 if (ret) { 562 auxiliary_device_uninit(adev); 563 return ret; 564 } 565 566 return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 567 } 568 569 #else /* !CONFIG_RESET_CONTROLLER */ 570 571 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 572 { 573 return 0; 574 } 575 576 #endif /* !CONFIG_RESET_CONTROLLER */ 577 578 static int mpfs_clk_probe(struct platform_device *pdev) 579 { 580 struct device *dev = &pdev->dev; 581 struct mpfs_clock_data *clk_data; 582 unsigned int num_clks; 583 int ret; 584 585 /* CLK_RESERVED is not part of clock arrays, so add 1 */ 586 num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 587 + ARRAY_SIZE(mpfs_periph_clks) + 1; 588 589 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 590 if (!clk_data) 591 return -ENOMEM; 592 593 clk_data->base = devm_platform_ioremap_resource(pdev, 0); 594 if (IS_ERR(clk_data->base)) 595 return PTR_ERR(clk_data->base); 596 597 clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 598 if (IS_ERR(clk_data->msspll_base)) 599 return PTR_ERR(clk_data->msspll_base); 600 601 clk_data->hw_data.num = num_clks; 602 clk_data->dev = dev; 603 dev_set_drvdata(dev, clk_data); 604 605 ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 606 clk_data); 607 if (ret) 608 return ret; 609 610 ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 611 if (ret) 612 return ret; 613 614 ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 615 clk_data); 616 if (ret) 617 return ret; 618 619 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 620 if (ret) 621 return ret; 622 623 return mpfs_reset_controller_register(clk_data); 624 } 625 626 static const struct of_device_id mpfs_clk_of_match_table[] = { 627 { .compatible = "microchip,mpfs-clkcfg", }, 628 {} 629 }; 630 MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); 631 632 static struct platform_driver mpfs_clk_driver = { 633 .probe = mpfs_clk_probe, 634 .driver = { 635 .name = "microchip-mpfs-clkcfg", 636 .of_match_table = mpfs_clk_of_match_table, 637 }, 638 }; 639 640 static int __init clk_mpfs_init(void) 641 { 642 return platform_driver_register(&mpfs_clk_driver); 643 } 644 core_initcall(clk_mpfs_init); 645 646 static void __exit clk_mpfs_exit(void) 647 { 648 platform_driver_unregister(&mpfs_clk_driver); 649 } 650 module_exit(clk_mpfs_exit); 651 652 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 653 MODULE_LICENSE("GPL v2"); 654