1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Daire McNamara,<daire.mcnamara@microchip.com> 4 * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5 */ 6 #include <linux/auxiliary_bus.h> 7 #include <linux/clk-provider.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <dt-bindings/clock/microchip,mpfs-clock.h> 13 #include <soc/microchip/mpfs.h> 14 15 /* address offset of control registers */ 16 #define REG_MSSPLL_REF_CR 0x08u 17 #define REG_MSSPLL_POSTDIV_CR 0x10u 18 #define REG_MSSPLL_SSCG_2_CR 0x2Cu 19 #define REG_CLOCK_CONFIG_CR 0x08u 20 #define REG_RTC_CLOCK_CR 0x0Cu 21 #define REG_SUBBLK_CLOCK_CR 0x84u 22 #define REG_SUBBLK_RESET_CR 0x88u 23 24 #define MSSPLL_FBDIV_SHIFT 0x00u 25 #define MSSPLL_FBDIV_WIDTH 0x0Cu 26 #define MSSPLL_REFDIV_SHIFT 0x08u 27 #define MSSPLL_REFDIV_WIDTH 0x06u 28 #define MSSPLL_POSTDIV_SHIFT 0x08u 29 #define MSSPLL_POSTDIV_WIDTH 0x07u 30 #define MSSPLL_FIXED_DIV 4u 31 32 struct mpfs_clock_data { 33 struct device *dev; 34 void __iomem *base; 35 void __iomem *msspll_base; 36 struct clk_hw_onecell_data hw_data; 37 }; 38 39 struct mpfs_msspll_hw_clock { 40 void __iomem *base; 41 unsigned int id; 42 u32 reg_offset; 43 u32 shift; 44 u32 width; 45 u32 flags; 46 struct clk_hw hw; 47 struct clk_init_data init; 48 }; 49 50 #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 51 52 struct mpfs_cfg_hw_clock { 53 struct clk_divider cfg; 54 struct clk_init_data init; 55 unsigned int id; 56 u32 reg_offset; 57 }; 58 59 struct mpfs_periph_clock { 60 void __iomem *reg; 61 u8 shift; 62 }; 63 64 struct mpfs_periph_hw_clock { 65 struct mpfs_periph_clock periph; 66 struct clk_hw hw; 67 unsigned int id; 68 }; 69 70 #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 71 72 /* 73 * mpfs_clk_lock prevents anything else from writing to the 74 * mpfs clk block while a software locked register is being written. 75 */ 76 static DEFINE_SPINLOCK(mpfs_clk_lock); 77 78 static const struct clk_parent_data mpfs_ext_ref[] = { 79 { .index = 0 }, 80 }; 81 82 static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 83 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 84 { 0, 0 } 85 }; 86 87 static const struct clk_div_table mpfs_div_ahb_table[] = { 88 { 1, 2 }, { 2, 4}, { 3, 8 }, 89 { 0, 0 } 90 }; 91 92 /* 93 * The only two supported reference clock frequencies for the PolarFire SoC are 94 * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. 95 * It therefore only needs to have divider table entries corresponding to 96 * divide by 100 and 125. 97 */ 98 static const struct clk_div_table mpfs_div_rtcref_table[] = { 99 { 100, 100 }, { 125, 125 }, 100 { 0, 0 } 101 }; 102 103 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 104 { 105 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 106 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 107 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 108 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 109 u32 mult, ref_div, postdiv; 110 111 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 112 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 113 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 114 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 115 postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 116 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 117 118 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 119 } 120 121 static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 122 { 123 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 124 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 125 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 126 u32 mult, ref_div; 127 unsigned long rate_before_ctrl; 128 129 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 130 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 131 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 132 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 133 134 rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 135 136 return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 137 msspll_hw->flags); 138 } 139 140 static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 141 { 142 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 143 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 144 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 145 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 146 u32 mult, ref_div, postdiv; 147 int divider_setting; 148 unsigned long rate_before_ctrl, flags; 149 150 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 151 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 152 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 153 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 154 155 rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 156 divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 157 msspll_hw->flags); 158 159 if (divider_setting < 0) 160 return divider_setting; 161 162 spin_lock_irqsave(&mpfs_clk_lock, flags); 163 164 postdiv = readl_relaxed(postdiv_addr); 165 postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); 166 writel_relaxed(postdiv, postdiv_addr); 167 168 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 169 170 return 0; 171 } 172 173 static const struct clk_ops mpfs_clk_msspll_ops = { 174 .recalc_rate = mpfs_clk_msspll_recalc_rate, 175 .round_rate = mpfs_clk_msspll_round_rate, 176 .set_rate = mpfs_clk_msspll_set_rate, 177 }; 178 179 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 180 .id = _id, \ 181 .shift = _shift, \ 182 .width = _width, \ 183 .reg_offset = _offset, \ 184 .flags = _flags, \ 185 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 186 } 187 188 static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 189 CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 190 MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 191 }; 192 193 static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 194 unsigned int num_clks, struct mpfs_clock_data *data) 195 { 196 unsigned int i; 197 int ret; 198 199 for (i = 0; i < num_clks; i++) { 200 struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 201 202 msspll_hw->base = data->msspll_base; 203 ret = devm_clk_hw_register(dev, &msspll_hw->hw); 204 if (ret) 205 return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 206 CLK_MSSPLL); 207 208 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 209 } 210 211 return 0; 212 } 213 214 /* 215 * "CFG" clocks 216 */ 217 218 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 219 .id = _id, \ 220 .cfg.shift = _shift, \ 221 .cfg.width = _width, \ 222 .cfg.table = _table, \ 223 .reg_offset = _offset, \ 224 .cfg.flags = _flags, \ 225 .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ 226 .cfg.lock = &mpfs_clk_lock, \ 227 } 228 229 #define CLK_CPU_OFFSET 0u 230 #define CLK_AXI_OFFSET 1u 231 #define CLK_AHB_OFFSET 2u 232 #define CLK_RTCREF_OFFSET 3u 233 234 static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 235 CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 236 REG_CLOCK_CONFIG_CR), 237 CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 238 REG_CLOCK_CONFIG_CR), 239 CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 240 REG_CLOCK_CONFIG_CR), 241 { 242 .id = CLK_RTCREF, 243 .cfg.shift = 0, 244 .cfg.width = 12, 245 .cfg.table = mpfs_div_rtcref_table, 246 .reg_offset = REG_RTC_CLOCK_CR, 247 .cfg.flags = CLK_DIVIDER_ONE_BASED, 248 .cfg.hw.init = 249 CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0), 250 } 251 }; 252 253 static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 254 unsigned int num_clks, struct mpfs_clock_data *data) 255 { 256 unsigned int i, id; 257 int ret; 258 259 for (i = 0; i < num_clks; i++) { 260 struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 261 262 cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; 263 ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw); 264 if (ret) 265 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 266 cfg_hw->id); 267 268 id = cfg_hw->id; 269 data->hw_data.hws[id] = &cfg_hw->cfg.hw; 270 } 271 272 return 0; 273 } 274 275 /* 276 * peripheral clocks - devices connected to axi or ahb buses. 277 */ 278 279 static int mpfs_periph_clk_enable(struct clk_hw *hw) 280 { 281 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 282 struct mpfs_periph_clock *periph = &periph_hw->periph; 283 u32 reg, val; 284 unsigned long flags; 285 286 spin_lock_irqsave(&mpfs_clk_lock, flags); 287 288 reg = readl_relaxed(periph->reg); 289 val = reg | (1u << periph->shift); 290 writel_relaxed(val, periph->reg); 291 292 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 293 294 return 0; 295 } 296 297 static void mpfs_periph_clk_disable(struct clk_hw *hw) 298 { 299 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 300 struct mpfs_periph_clock *periph = &periph_hw->periph; 301 u32 reg, val; 302 unsigned long flags; 303 304 spin_lock_irqsave(&mpfs_clk_lock, flags); 305 306 reg = readl_relaxed(periph->reg); 307 val = reg & ~(1u << periph->shift); 308 writel_relaxed(val, periph->reg); 309 310 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 311 } 312 313 static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 314 { 315 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 316 struct mpfs_periph_clock *periph = &periph_hw->periph; 317 u32 reg; 318 319 reg = readl_relaxed(periph->reg); 320 if (reg & (1u << periph->shift)) 321 return 1; 322 323 return 0; 324 } 325 326 static const struct clk_ops mpfs_periph_clk_ops = { 327 .enable = mpfs_periph_clk_enable, 328 .disable = mpfs_periph_clk_disable, 329 .is_enabled = mpfs_periph_clk_is_enabled, 330 }; 331 332 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 333 .id = _id, \ 334 .periph.shift = _shift, \ 335 .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 336 _flags), \ 337 } 338 339 #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) 340 341 /* 342 * Critical clocks: 343 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 344 * trap handler 345 * - CLK_MMUART0: reserved by the hss 346 * - CLK_DDRC: provides clock to the ddr subsystem 347 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 348 * if the AHB interface clock is disabled 349 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 350 * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 351 * causes the FPGA fabric to go into reset. 352 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 353 */ 354 355 static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 356 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 357 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 358 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 359 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 360 CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), 361 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 362 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 363 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 364 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 365 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 366 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 367 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 368 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 369 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 370 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 371 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 372 CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 373 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 374 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 375 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 376 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 377 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 378 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 379 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 380 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 381 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 382 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 383 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 384 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 385 }; 386 387 static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 388 int num_clks, struct mpfs_clock_data *data) 389 { 390 unsigned int i, id; 391 int ret; 392 393 for (i = 0; i < num_clks; i++) { 394 struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 395 396 periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; 397 ret = devm_clk_hw_register(dev, &periph_hw->hw); 398 if (ret) 399 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 400 periph_hw->id); 401 402 id = periph_hws[i].id; 403 data->hw_data.hws[id] = &periph_hw->hw; 404 } 405 406 return 0; 407 } 408 409 /* 410 * Peripheral clock resets 411 */ 412 413 #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 414 415 u32 mpfs_reset_read(struct device *dev) 416 { 417 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 418 419 return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 420 } 421 EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 422 423 void mpfs_reset_write(struct device *dev, u32 val) 424 { 425 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 426 427 writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 428 } 429 EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 430 431 static void mpfs_reset_unregister_adev(void *_adev) 432 { 433 struct auxiliary_device *adev = _adev; 434 435 auxiliary_device_delete(adev); 436 } 437 438 static void mpfs_reset_adev_release(struct device *dev) 439 { 440 struct auxiliary_device *adev = to_auxiliary_dev(dev); 441 442 auxiliary_device_uninit(adev); 443 444 kfree(adev); 445 } 446 447 static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 448 { 449 struct auxiliary_device *adev; 450 int ret; 451 452 adev = kzalloc(sizeof(*adev), GFP_KERNEL); 453 if (!adev) 454 return ERR_PTR(-ENOMEM); 455 456 adev->name = "reset-mpfs"; 457 adev->dev.parent = clk_data->dev; 458 adev->dev.release = mpfs_reset_adev_release; 459 adev->id = 666u; 460 461 ret = auxiliary_device_init(adev); 462 if (ret) { 463 kfree(adev); 464 return ERR_PTR(ret); 465 } 466 467 return adev; 468 } 469 470 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 471 { 472 struct auxiliary_device *adev; 473 int ret; 474 475 adev = mpfs_reset_adev_alloc(clk_data); 476 if (IS_ERR(adev)) 477 return PTR_ERR(adev); 478 479 ret = auxiliary_device_add(adev); 480 if (ret) { 481 auxiliary_device_uninit(adev); 482 return ret; 483 } 484 485 return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 486 } 487 488 #else /* !CONFIG_RESET_CONTROLLER */ 489 490 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 491 { 492 return 0; 493 } 494 495 #endif /* !CONFIG_RESET_CONTROLLER */ 496 497 static int mpfs_clk_probe(struct platform_device *pdev) 498 { 499 struct device *dev = &pdev->dev; 500 struct mpfs_clock_data *clk_data; 501 unsigned int num_clks; 502 int ret; 503 504 /* CLK_RESERVED is not part of clock arrays, so add 1 */ 505 num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 506 + ARRAY_SIZE(mpfs_periph_clks) + 1; 507 508 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 509 if (!clk_data) 510 return -ENOMEM; 511 512 clk_data->base = devm_platform_ioremap_resource(pdev, 0); 513 if (IS_ERR(clk_data->base)) 514 return PTR_ERR(clk_data->base); 515 516 clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 517 if (IS_ERR(clk_data->msspll_base)) 518 return PTR_ERR(clk_data->msspll_base); 519 520 clk_data->hw_data.num = num_clks; 521 clk_data->dev = dev; 522 dev_set_drvdata(dev, clk_data); 523 524 ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 525 clk_data); 526 if (ret) 527 return ret; 528 529 ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 530 if (ret) 531 return ret; 532 533 ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 534 clk_data); 535 if (ret) 536 return ret; 537 538 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 539 if (ret) 540 return ret; 541 542 return mpfs_reset_controller_register(clk_data); 543 } 544 545 static const struct of_device_id mpfs_clk_of_match_table[] = { 546 { .compatible = "microchip,mpfs-clkcfg", }, 547 {} 548 }; 549 MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); 550 551 static struct platform_driver mpfs_clk_driver = { 552 .probe = mpfs_clk_probe, 553 .driver = { 554 .name = "microchip-mpfs-clkcfg", 555 .of_match_table = mpfs_clk_of_match_table, 556 }, 557 }; 558 559 static int __init clk_mpfs_init(void) 560 { 561 return platform_driver_register(&mpfs_clk_driver); 562 } 563 core_initcall(clk_mpfs_init); 564 565 static void __exit clk_mpfs_exit(void) 566 { 567 platform_driver_unregister(&mpfs_clk_driver); 568 } 569 module_exit(clk_mpfs_exit); 570 571 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 572 MODULE_LICENSE("GPL v2"); 573