1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Daire McNamara,<daire.mcnamara@microchip.com> 4 * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5 */ 6 #include <linux/clk-provider.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/slab.h> 11 #include <dt-bindings/clock/microchip,mpfs-clock.h> 12 13 /* address offset of control registers */ 14 #define REG_MSSPLL_REF_CR 0x08u 15 #define REG_MSSPLL_POSTDIV_CR 0x10u 16 #define REG_MSSPLL_SSCG_2_CR 0x2Cu 17 #define REG_CLOCK_CONFIG_CR 0x08u 18 #define REG_SUBBLK_CLOCK_CR 0x84u 19 #define REG_SUBBLK_RESET_CR 0x88u 20 21 #define MSSPLL_FBDIV_SHIFT 0x00u 22 #define MSSPLL_FBDIV_WIDTH 0x0Cu 23 #define MSSPLL_REFDIV_SHIFT 0x08u 24 #define MSSPLL_REFDIV_WIDTH 0x06u 25 #define MSSPLL_POSTDIV_SHIFT 0x08u 26 #define MSSPLL_POSTDIV_WIDTH 0x07u 27 #define MSSPLL_FIXED_DIV 4u 28 29 struct mpfs_clock_data { 30 void __iomem *base; 31 void __iomem *msspll_base; 32 struct clk_hw_onecell_data hw_data; 33 }; 34 35 struct mpfs_msspll_hw_clock { 36 void __iomem *base; 37 unsigned int id; 38 u32 reg_offset; 39 u32 shift; 40 u32 width; 41 u32 flags; 42 struct clk_hw hw; 43 struct clk_init_data init; 44 }; 45 46 #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 47 48 struct mpfs_cfg_clock { 49 const struct clk_div_table *table; 50 unsigned int id; 51 u32 reg_offset; 52 u8 shift; 53 u8 width; 54 u8 flags; 55 }; 56 57 struct mpfs_cfg_hw_clock { 58 struct mpfs_cfg_clock cfg; 59 void __iomem *sys_base; 60 struct clk_hw hw; 61 struct clk_init_data init; 62 }; 63 64 #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) 65 66 struct mpfs_periph_clock { 67 unsigned int id; 68 u8 shift; 69 }; 70 71 struct mpfs_periph_hw_clock { 72 struct mpfs_periph_clock periph; 73 void __iomem *sys_base; 74 struct clk_hw hw; 75 }; 76 77 #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 78 79 /* 80 * mpfs_clk_lock prevents anything else from writing to the 81 * mpfs clk block while a software locked register is being written. 82 */ 83 static DEFINE_SPINLOCK(mpfs_clk_lock); 84 85 static const struct clk_parent_data mpfs_ext_ref[] = { 86 { .index = 0 }, 87 }; 88 89 static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 90 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 91 { 0, 0 } 92 }; 93 94 static const struct clk_div_table mpfs_div_ahb_table[] = { 95 { 1, 2 }, { 2, 4}, { 3, 8 }, 96 { 0, 0 } 97 }; 98 99 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 100 { 101 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 102 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 103 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 104 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 105 u32 mult, ref_div, postdiv; 106 107 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 108 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 109 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 110 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 111 postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 112 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 113 114 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 115 } 116 117 static const struct clk_ops mpfs_clk_msspll_ops = { 118 .recalc_rate = mpfs_clk_msspll_recalc_rate, 119 }; 120 121 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 122 .id = _id, \ 123 .shift = _shift, \ 124 .width = _width, \ 125 .reg_offset = _offset, \ 126 .flags = _flags, \ 127 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 128 } 129 130 static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 131 CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 132 MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 133 }; 134 135 static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, 136 void __iomem *base) 137 { 138 msspll_hw->base = base; 139 140 return devm_clk_hw_register(dev, &msspll_hw->hw); 141 } 142 143 static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 144 unsigned int num_clks, struct mpfs_clock_data *data) 145 { 146 void __iomem *base = data->msspll_base; 147 unsigned int i; 148 int ret; 149 150 for (i = 0; i < num_clks; i++) { 151 struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 152 153 ret = mpfs_clk_register_msspll(dev, msspll_hw, base); 154 if (ret) 155 return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 156 CLK_MSSPLL); 157 158 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 159 } 160 161 return 0; 162 } 163 164 /* 165 * "CFG" clocks 166 */ 167 168 static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) 169 { 170 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 171 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 172 void __iomem *base_addr = cfg_hw->sys_base; 173 u32 val; 174 175 val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; 176 val &= clk_div_mask(cfg->width); 177 178 return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); 179 } 180 181 static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 182 { 183 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 184 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 185 186 return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); 187 } 188 189 static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 190 { 191 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 192 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 193 void __iomem *base_addr = cfg_hw->sys_base; 194 unsigned long flags; 195 u32 val; 196 int divider_setting; 197 198 divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); 199 200 if (divider_setting < 0) 201 return divider_setting; 202 203 spin_lock_irqsave(&mpfs_clk_lock, flags); 204 val = readl_relaxed(base_addr + cfg->reg_offset); 205 val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); 206 val |= divider_setting << cfg->shift; 207 writel_relaxed(val, base_addr + cfg->reg_offset); 208 209 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 210 211 return 0; 212 } 213 214 static const struct clk_ops mpfs_clk_cfg_ops = { 215 .recalc_rate = mpfs_cfg_clk_recalc_rate, 216 .round_rate = mpfs_cfg_clk_round_rate, 217 .set_rate = mpfs_cfg_clk_set_rate, 218 }; 219 220 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 221 .cfg.id = _id, \ 222 .cfg.shift = _shift, \ 223 .cfg.width = _width, \ 224 .cfg.table = _table, \ 225 .cfg.reg_offset = _offset, \ 226 .cfg.flags = _flags, \ 227 .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ 228 } 229 230 static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 231 CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 232 REG_CLOCK_CONFIG_CR), 233 CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 234 REG_CLOCK_CONFIG_CR), 235 CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 236 REG_CLOCK_CONFIG_CR), 237 }; 238 239 static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, 240 void __iomem *sys_base) 241 { 242 cfg_hw->sys_base = sys_base; 243 244 return devm_clk_hw_register(dev, &cfg_hw->hw); 245 } 246 247 static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 248 unsigned int num_clks, struct mpfs_clock_data *data) 249 { 250 void __iomem *sys_base = data->base; 251 unsigned int i, id; 252 int ret; 253 254 for (i = 0; i < num_clks; i++) { 255 struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 256 257 ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); 258 if (ret) 259 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 260 cfg_hw->cfg.id); 261 262 id = cfg_hw->cfg.id; 263 data->hw_data.hws[id] = &cfg_hw->hw; 264 } 265 266 return 0; 267 } 268 269 /* 270 * peripheral clocks - devices connected to axi or ahb buses. 271 */ 272 273 static int mpfs_periph_clk_enable(struct clk_hw *hw) 274 { 275 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 276 struct mpfs_periph_clock *periph = &periph_hw->periph; 277 void __iomem *base_addr = periph_hw->sys_base; 278 u32 reg, val; 279 unsigned long flags; 280 281 spin_lock_irqsave(&mpfs_clk_lock, flags); 282 283 reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); 284 val = reg & ~(1u << periph->shift); 285 writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); 286 287 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 288 val = reg | (1u << periph->shift); 289 writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 290 291 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 292 293 return 0; 294 } 295 296 static void mpfs_periph_clk_disable(struct clk_hw *hw) 297 { 298 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 299 struct mpfs_periph_clock *periph = &periph_hw->periph; 300 void __iomem *base_addr = periph_hw->sys_base; 301 u32 reg, val; 302 unsigned long flags; 303 304 spin_lock_irqsave(&mpfs_clk_lock, flags); 305 306 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 307 val = reg & ~(1u << periph->shift); 308 writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 309 310 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 311 } 312 313 static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 314 { 315 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 316 struct mpfs_periph_clock *periph = &periph_hw->periph; 317 void __iomem *base_addr = periph_hw->sys_base; 318 u32 reg; 319 320 reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); 321 if ((reg & (1u << periph->shift)) == 0u) { 322 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 323 if (reg & (1u << periph->shift)) 324 return 1; 325 } 326 327 return 0; 328 } 329 330 static const struct clk_ops mpfs_periph_clk_ops = { 331 .enable = mpfs_periph_clk_enable, 332 .disable = mpfs_periph_clk_disable, 333 .is_enabled = mpfs_periph_clk_is_enabled, 334 }; 335 336 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 337 .periph.id = _id, \ 338 .periph.shift = _shift, \ 339 .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 340 _flags), \ 341 } 342 343 #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].hw) 344 345 /* 346 * Critical clocks: 347 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 348 * trap handler 349 * - CLK_MMUART0: reserved by the hss 350 * - CLK_DDRC: provides clock to the ddr subsystem 351 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 352 * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 353 * causes the FPGA fabric to go into reset. 354 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 355 */ 356 357 static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 358 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 359 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 360 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 361 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 362 CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(AHB), 4, 0), 363 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 364 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 365 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 366 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 367 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 368 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 369 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 370 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 371 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 372 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 373 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 374 CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 375 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, 0), 376 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 377 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 378 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 379 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 380 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 381 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 382 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 383 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 384 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 385 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 386 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 387 }; 388 389 static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, 390 void __iomem *sys_base) 391 { 392 periph_hw->sys_base = sys_base; 393 394 return devm_clk_hw_register(dev, &periph_hw->hw); 395 } 396 397 static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 398 int num_clks, struct mpfs_clock_data *data) 399 { 400 void __iomem *sys_base = data->base; 401 unsigned int i, id; 402 int ret; 403 404 for (i = 0; i < num_clks; i++) { 405 struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 406 407 ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); 408 if (ret) 409 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 410 periph_hw->periph.id); 411 412 id = periph_hws[i].periph.id; 413 data->hw_data.hws[id] = &periph_hw->hw; 414 } 415 416 return 0; 417 } 418 419 static int mpfs_clk_probe(struct platform_device *pdev) 420 { 421 struct device *dev = &pdev->dev; 422 struct mpfs_clock_data *clk_data; 423 unsigned int num_clks; 424 int ret; 425 426 /* CLK_RESERVED is not part of clock arrays, so add 1 */ 427 num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 428 + ARRAY_SIZE(mpfs_periph_clks) + 1; 429 430 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 431 if (!clk_data) 432 return -ENOMEM; 433 434 clk_data->base = devm_platform_ioremap_resource(pdev, 0); 435 if (IS_ERR(clk_data->base)) 436 return PTR_ERR(clk_data->base); 437 438 clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 439 if (IS_ERR(clk_data->msspll_base)) 440 return PTR_ERR(clk_data->msspll_base); 441 442 clk_data->hw_data.num = num_clks; 443 444 ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 445 clk_data); 446 if (ret) 447 return ret; 448 449 ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 450 if (ret) 451 return ret; 452 453 ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 454 clk_data); 455 if (ret) 456 return ret; 457 458 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 459 if (ret) 460 return ret; 461 462 return ret; 463 } 464 465 static const struct of_device_id mpfs_clk_of_match_table[] = { 466 { .compatible = "microchip,mpfs-clkcfg", }, 467 {} 468 }; 469 MODULE_DEVICE_TABLE(of, mpfs_clk_match_table); 470 471 static struct platform_driver mpfs_clk_driver = { 472 .probe = mpfs_clk_probe, 473 .driver = { 474 .name = "microchip-mpfs-clkcfg", 475 .of_match_table = mpfs_clk_of_match_table, 476 }, 477 }; 478 479 static int __init clk_mpfs_init(void) 480 { 481 return platform_driver_register(&mpfs_clk_driver); 482 } 483 core_initcall(clk_mpfs_init); 484 485 static void __exit clk_mpfs_exit(void) 486 { 487 platform_driver_unregister(&mpfs_clk_driver); 488 } 489 module_exit(clk_mpfs_exit); 490 491 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 492 MODULE_LICENSE("GPL v2"); 493