1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Daire McNamara,<daire.mcnamara@microchip.com> 4 * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5 */ 6 #include <linux/auxiliary_bus.h> 7 #include <linux/clk-provider.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <dt-bindings/clock/microchip,mpfs-clock.h> 13 #include <soc/microchip/mpfs.h> 14 15 /* address offset of control registers */ 16 #define REG_MSSPLL_REF_CR 0x08u 17 #define REG_MSSPLL_POSTDIV_CR 0x10u 18 #define REG_MSSPLL_SSCG_2_CR 0x2Cu 19 #define REG_CLOCK_CONFIG_CR 0x08u 20 #define REG_RTC_CLOCK_CR 0x0Cu 21 #define REG_SUBBLK_CLOCK_CR 0x84u 22 #define REG_SUBBLK_RESET_CR 0x88u 23 24 #define MSSPLL_FBDIV_SHIFT 0x00u 25 #define MSSPLL_FBDIV_WIDTH 0x0Cu 26 #define MSSPLL_REFDIV_SHIFT 0x08u 27 #define MSSPLL_REFDIV_WIDTH 0x06u 28 #define MSSPLL_POSTDIV_SHIFT 0x08u 29 #define MSSPLL_POSTDIV_WIDTH 0x07u 30 #define MSSPLL_FIXED_DIV 4u 31 32 struct mpfs_clock_data { 33 struct device *dev; 34 void __iomem *base; 35 void __iomem *msspll_base; 36 struct clk_hw_onecell_data hw_data; 37 }; 38 39 struct mpfs_msspll_hw_clock { 40 void __iomem *base; 41 unsigned int id; 42 u32 reg_offset; 43 u32 shift; 44 u32 width; 45 u32 flags; 46 struct clk_hw hw; 47 struct clk_init_data init; 48 }; 49 50 #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 51 52 struct mpfs_cfg_clock { 53 const struct clk_div_table *table; 54 unsigned int id; 55 u32 reg_offset; 56 u8 shift; 57 u8 width; 58 u8 flags; 59 }; 60 61 struct mpfs_cfg_hw_clock { 62 struct mpfs_cfg_clock cfg; 63 void __iomem *sys_base; 64 struct clk_hw hw; 65 struct clk_init_data init; 66 }; 67 68 #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) 69 70 struct mpfs_periph_clock { 71 unsigned int id; 72 u8 shift; 73 }; 74 75 struct mpfs_periph_hw_clock { 76 struct mpfs_periph_clock periph; 77 void __iomem *sys_base; 78 struct clk_hw hw; 79 }; 80 81 #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 82 83 /* 84 * mpfs_clk_lock prevents anything else from writing to the 85 * mpfs clk block while a software locked register is being written. 86 */ 87 static DEFINE_SPINLOCK(mpfs_clk_lock); 88 89 static const struct clk_parent_data mpfs_ext_ref[] = { 90 { .index = 0 }, 91 }; 92 93 static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 94 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 95 { 0, 0 } 96 }; 97 98 static const struct clk_div_table mpfs_div_ahb_table[] = { 99 { 1, 2 }, { 2, 4}, { 3, 8 }, 100 { 0, 0 } 101 }; 102 103 /* 104 * The only two supported reference clock frequencies for the PolarFire SoC are 105 * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. 106 * It therefore only needs to have divider table entries corresponding to 107 * divide by 100 and 125. 108 */ 109 static const struct clk_div_table mpfs_div_rtcref_table[] = { 110 { 100, 100 }, { 125, 125 }, 111 { 0, 0 } 112 }; 113 114 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 115 { 116 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 118 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 119 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 120 u32 mult, ref_div, postdiv; 121 122 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 123 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 124 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 125 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 126 postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 127 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 128 129 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 130 } 131 132 static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 133 { 134 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 135 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 136 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 137 u32 mult, ref_div; 138 unsigned long rate_before_ctrl; 139 140 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 141 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 142 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 143 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 144 145 rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 146 147 return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 148 msspll_hw->flags); 149 } 150 151 static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 152 { 153 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 154 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 155 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 156 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 157 u32 mult, ref_div, postdiv; 158 int divider_setting; 159 unsigned long rate_before_ctrl, flags; 160 161 mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 162 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 163 ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 164 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 165 166 rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 167 divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 168 msspll_hw->flags); 169 170 if (divider_setting < 0) 171 return divider_setting; 172 173 spin_lock_irqsave(&mpfs_clk_lock, flags); 174 175 postdiv = readl_relaxed(postdiv_addr); 176 postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); 177 writel_relaxed(postdiv, postdiv_addr); 178 179 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 180 181 return 0; 182 } 183 184 static const struct clk_ops mpfs_clk_msspll_ops = { 185 .recalc_rate = mpfs_clk_msspll_recalc_rate, 186 .round_rate = mpfs_clk_msspll_round_rate, 187 .set_rate = mpfs_clk_msspll_set_rate, 188 }; 189 190 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 191 .id = _id, \ 192 .shift = _shift, \ 193 .width = _width, \ 194 .reg_offset = _offset, \ 195 .flags = _flags, \ 196 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 197 } 198 199 static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 200 CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 201 MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 202 }; 203 204 static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, 205 void __iomem *base) 206 { 207 msspll_hw->base = base; 208 209 return devm_clk_hw_register(dev, &msspll_hw->hw); 210 } 211 212 static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 213 unsigned int num_clks, struct mpfs_clock_data *data) 214 { 215 void __iomem *base = data->msspll_base; 216 unsigned int i; 217 int ret; 218 219 for (i = 0; i < num_clks; i++) { 220 struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 221 222 ret = mpfs_clk_register_msspll(dev, msspll_hw, base); 223 if (ret) 224 return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 225 CLK_MSSPLL); 226 227 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 228 } 229 230 return 0; 231 } 232 233 /* 234 * "CFG" clocks 235 */ 236 237 static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) 238 { 239 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 240 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 241 void __iomem *base_addr = cfg_hw->sys_base; 242 u32 val; 243 244 val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; 245 val &= clk_div_mask(cfg->width); 246 247 return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); 248 } 249 250 static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 251 { 252 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 253 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 254 255 return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); 256 } 257 258 static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 259 { 260 struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 261 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 262 void __iomem *base_addr = cfg_hw->sys_base; 263 unsigned long flags; 264 u32 val; 265 int divider_setting; 266 267 divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); 268 269 if (divider_setting < 0) 270 return divider_setting; 271 272 spin_lock_irqsave(&mpfs_clk_lock, flags); 273 val = readl_relaxed(base_addr + cfg->reg_offset); 274 val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); 275 val |= divider_setting << cfg->shift; 276 writel_relaxed(val, base_addr + cfg->reg_offset); 277 278 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 279 280 return 0; 281 } 282 283 static const struct clk_ops mpfs_clk_cfg_ops = { 284 .recalc_rate = mpfs_cfg_clk_recalc_rate, 285 .round_rate = mpfs_cfg_clk_round_rate, 286 .set_rate = mpfs_cfg_clk_set_rate, 287 }; 288 289 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 290 .cfg.id = _id, \ 291 .cfg.shift = _shift, \ 292 .cfg.width = _width, \ 293 .cfg.table = _table, \ 294 .cfg.reg_offset = _offset, \ 295 .cfg.flags = _flags, \ 296 .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ 297 } 298 299 #define CLK_CPU_OFFSET 0u 300 #define CLK_AXI_OFFSET 1u 301 #define CLK_AHB_OFFSET 2u 302 #define CLK_RTCREF_OFFSET 3u 303 304 static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 305 CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 306 REG_CLOCK_CONFIG_CR), 307 CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 308 REG_CLOCK_CONFIG_CR), 309 CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 310 REG_CLOCK_CONFIG_CR), 311 { 312 .cfg.id = CLK_RTCREF, 313 .cfg.shift = 0, 314 .cfg.width = 12, 315 .cfg.table = mpfs_div_rtcref_table, 316 .cfg.reg_offset = REG_RTC_CLOCK_CR, 317 .cfg.flags = CLK_DIVIDER_ONE_BASED, 318 .hw.init = 319 CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), 320 } 321 }; 322 323 static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, 324 void __iomem *sys_base) 325 { 326 cfg_hw->sys_base = sys_base; 327 328 return devm_clk_hw_register(dev, &cfg_hw->hw); 329 } 330 331 static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 332 unsigned int num_clks, struct mpfs_clock_data *data) 333 { 334 void __iomem *sys_base = data->base; 335 unsigned int i, id; 336 int ret; 337 338 for (i = 0; i < num_clks; i++) { 339 struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 340 341 ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); 342 if (ret) 343 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 344 cfg_hw->cfg.id); 345 346 id = cfg_hw->cfg.id; 347 data->hw_data.hws[id] = &cfg_hw->hw; 348 } 349 350 return 0; 351 } 352 353 /* 354 * peripheral clocks - devices connected to axi or ahb buses. 355 */ 356 357 static int mpfs_periph_clk_enable(struct clk_hw *hw) 358 { 359 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 360 struct mpfs_periph_clock *periph = &periph_hw->periph; 361 void __iomem *base_addr = periph_hw->sys_base; 362 u32 reg, val; 363 unsigned long flags; 364 365 spin_lock_irqsave(&mpfs_clk_lock, flags); 366 367 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 368 val = reg | (1u << periph->shift); 369 writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 370 371 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 372 373 return 0; 374 } 375 376 static void mpfs_periph_clk_disable(struct clk_hw *hw) 377 { 378 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 379 struct mpfs_periph_clock *periph = &periph_hw->periph; 380 void __iomem *base_addr = periph_hw->sys_base; 381 u32 reg, val; 382 unsigned long flags; 383 384 spin_lock_irqsave(&mpfs_clk_lock, flags); 385 386 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 387 val = reg & ~(1u << periph->shift); 388 writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 389 390 spin_unlock_irqrestore(&mpfs_clk_lock, flags); 391 } 392 393 static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 394 { 395 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 396 struct mpfs_periph_clock *periph = &periph_hw->periph; 397 void __iomem *base_addr = periph_hw->sys_base; 398 u32 reg; 399 400 reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 401 if (reg & (1u << periph->shift)) 402 return 1; 403 404 return 0; 405 } 406 407 static const struct clk_ops mpfs_periph_clk_ops = { 408 .enable = mpfs_periph_clk_enable, 409 .disable = mpfs_periph_clk_disable, 410 .is_enabled = mpfs_periph_clk_is_enabled, 411 }; 412 413 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 414 .periph.id = _id, \ 415 .periph.shift = _shift, \ 416 .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 417 _flags), \ 418 } 419 420 #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw) 421 422 /* 423 * Critical clocks: 424 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 425 * trap handler 426 * - CLK_MMUART0: reserved by the hss 427 * - CLK_DDRC: provides clock to the ddr subsystem 428 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 429 * if the AHB interface clock is disabled 430 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 431 * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 432 * causes the FPGA fabric to go into reset. 433 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 434 */ 435 436 static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 437 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 438 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 439 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 440 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 441 CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), 442 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 443 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 444 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 445 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 446 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 447 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 448 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 449 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 450 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 451 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 452 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 453 CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 454 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 455 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 456 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 457 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 458 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 459 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 460 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 461 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 462 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 463 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 464 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 465 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 466 }; 467 468 static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, 469 void __iomem *sys_base) 470 { 471 periph_hw->sys_base = sys_base; 472 473 return devm_clk_hw_register(dev, &periph_hw->hw); 474 } 475 476 static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 477 int num_clks, struct mpfs_clock_data *data) 478 { 479 void __iomem *sys_base = data->base; 480 unsigned int i, id; 481 int ret; 482 483 for (i = 0; i < num_clks; i++) { 484 struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 485 486 ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); 487 if (ret) 488 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 489 periph_hw->periph.id); 490 491 id = periph_hws[i].periph.id; 492 data->hw_data.hws[id] = &periph_hw->hw; 493 } 494 495 return 0; 496 } 497 498 /* 499 * Peripheral clock resets 500 */ 501 502 #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 503 504 u32 mpfs_reset_read(struct device *dev) 505 { 506 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 507 508 return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 509 } 510 EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 511 512 void mpfs_reset_write(struct device *dev, u32 val) 513 { 514 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 515 516 writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 517 } 518 EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 519 520 static void mpfs_reset_unregister_adev(void *_adev) 521 { 522 struct auxiliary_device *adev = _adev; 523 524 auxiliary_device_delete(adev); 525 } 526 527 static void mpfs_reset_adev_release(struct device *dev) 528 { 529 struct auxiliary_device *adev = to_auxiliary_dev(dev); 530 531 auxiliary_device_uninit(adev); 532 533 kfree(adev); 534 } 535 536 static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 537 { 538 struct auxiliary_device *adev; 539 int ret; 540 541 adev = kzalloc(sizeof(*adev), GFP_KERNEL); 542 if (!adev) 543 return ERR_PTR(-ENOMEM); 544 545 adev->name = "reset-mpfs"; 546 adev->dev.parent = clk_data->dev; 547 adev->dev.release = mpfs_reset_adev_release; 548 adev->id = 666u; 549 550 ret = auxiliary_device_init(adev); 551 if (ret) { 552 kfree(adev); 553 return ERR_PTR(ret); 554 } 555 556 return adev; 557 } 558 559 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 560 { 561 struct auxiliary_device *adev; 562 int ret; 563 564 adev = mpfs_reset_adev_alloc(clk_data); 565 if (IS_ERR(adev)) 566 return PTR_ERR(adev); 567 568 ret = auxiliary_device_add(adev); 569 if (ret) { 570 auxiliary_device_uninit(adev); 571 return ret; 572 } 573 574 return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 575 } 576 577 #else /* !CONFIG_RESET_CONTROLLER */ 578 579 static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 580 { 581 return 0; 582 } 583 584 #endif /* !CONFIG_RESET_CONTROLLER */ 585 586 static int mpfs_clk_probe(struct platform_device *pdev) 587 { 588 struct device *dev = &pdev->dev; 589 struct mpfs_clock_data *clk_data; 590 unsigned int num_clks; 591 int ret; 592 593 /* CLK_RESERVED is not part of clock arrays, so add 1 */ 594 num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 595 + ARRAY_SIZE(mpfs_periph_clks) + 1; 596 597 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 598 if (!clk_data) 599 return -ENOMEM; 600 601 clk_data->base = devm_platform_ioremap_resource(pdev, 0); 602 if (IS_ERR(clk_data->base)) 603 return PTR_ERR(clk_data->base); 604 605 clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 606 if (IS_ERR(clk_data->msspll_base)) 607 return PTR_ERR(clk_data->msspll_base); 608 609 clk_data->hw_data.num = num_clks; 610 clk_data->dev = dev; 611 dev_set_drvdata(dev, clk_data); 612 613 ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 614 clk_data); 615 if (ret) 616 return ret; 617 618 ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 619 if (ret) 620 return ret; 621 622 ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 623 clk_data); 624 if (ret) 625 return ret; 626 627 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 628 if (ret) 629 return ret; 630 631 return mpfs_reset_controller_register(clk_data); 632 } 633 634 static const struct of_device_id mpfs_clk_of_match_table[] = { 635 { .compatible = "microchip,mpfs-clkcfg", }, 636 {} 637 }; 638 MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); 639 640 static struct platform_driver mpfs_clk_driver = { 641 .probe = mpfs_clk_probe, 642 .driver = { 643 .name = "microchip-mpfs-clkcfg", 644 .of_match_table = mpfs_clk_of_match_table, 645 }, 646 }; 647 648 static int __init clk_mpfs_init(void) 649 { 650 return platform_driver_register(&mpfs_clk_driver); 651 } 652 core_initcall(clk_mpfs_init); 653 654 static void __exit clk_mpfs_exit(void) 655 { 656 platform_driver_unregister(&mpfs_clk_driver); 657 } 658 module_exit(clk_mpfs_exit); 659 660 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 661 MODULE_LICENSE("GPL v2"); 662