1635e5e73SDaire McNamara // SPDX-License-Identifier: GPL-2.0-only 2635e5e73SDaire McNamara /* 3635e5e73SDaire McNamara * Daire McNamara,<daire.mcnamara@microchip.com> 4635e5e73SDaire McNamara * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5635e5e73SDaire McNamara */ 6b56bae2dSConor Dooley #include <linux/auxiliary_bus.h> 7635e5e73SDaire McNamara #include <linux/clk-provider.h> 8635e5e73SDaire McNamara #include <linux/io.h> 9635e5e73SDaire McNamara #include <linux/module.h> 10635e5e73SDaire McNamara #include <linux/platform_device.h> 11635e5e73SDaire McNamara #include <linux/slab.h> 12635e5e73SDaire McNamara #include <dt-bindings/clock/microchip,mpfs-clock.h> 13b56bae2dSConor Dooley #include <soc/microchip/mpfs.h> 14635e5e73SDaire McNamara 15635e5e73SDaire McNamara /* address offset of control registers */ 16445c2da8SConor Dooley #define REG_MSSPLL_REF_CR 0x08u 17445c2da8SConor Dooley #define REG_MSSPLL_POSTDIV_CR 0x10u 18445c2da8SConor Dooley #define REG_MSSPLL_SSCG_2_CR 0x2Cu 19635e5e73SDaire McNamara #define REG_CLOCK_CONFIG_CR 0x08u 201c6a7ea3SConor Dooley #define REG_RTC_CLOCK_CR 0x0Cu 21635e5e73SDaire McNamara #define REG_SUBBLK_CLOCK_CR 0x84u 22635e5e73SDaire McNamara #define REG_SUBBLK_RESET_CR 0x88u 23635e5e73SDaire McNamara 24445c2da8SConor Dooley #define MSSPLL_FBDIV_SHIFT 0x00u 25445c2da8SConor Dooley #define MSSPLL_FBDIV_WIDTH 0x0Cu 26445c2da8SConor Dooley #define MSSPLL_REFDIV_SHIFT 0x08u 27445c2da8SConor Dooley #define MSSPLL_REFDIV_WIDTH 0x06u 28445c2da8SConor Dooley #define MSSPLL_POSTDIV_SHIFT 0x08u 29445c2da8SConor Dooley #define MSSPLL_POSTDIV_WIDTH 0x07u 30445c2da8SConor Dooley #define MSSPLL_FIXED_DIV 4u 31445c2da8SConor Dooley 32635e5e73SDaire McNamara struct mpfs_clock_data { 33b56bae2dSConor Dooley struct device *dev; 34635e5e73SDaire McNamara void __iomem *base; 35445c2da8SConor Dooley void __iomem *msspll_base; 36635e5e73SDaire McNamara struct clk_hw_onecell_data hw_data; 37635e5e73SDaire McNamara }; 38635e5e73SDaire McNamara 39445c2da8SConor Dooley struct mpfs_msspll_hw_clock { 40445c2da8SConor Dooley void __iomem *base; 41445c2da8SConor Dooley unsigned int id; 42445c2da8SConor Dooley u32 reg_offset; 43445c2da8SConor Dooley u32 shift; 44445c2da8SConor Dooley u32 width; 45445c2da8SConor Dooley u32 flags; 46445c2da8SConor Dooley struct clk_hw hw; 47445c2da8SConor Dooley struct clk_init_data init; 48445c2da8SConor Dooley }; 49445c2da8SConor Dooley 50445c2da8SConor Dooley #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 51445c2da8SConor Dooley 52635e5e73SDaire McNamara struct mpfs_cfg_hw_clock { 534da2404bSConor Dooley struct clk_divider cfg; 54635e5e73SDaire McNamara struct clk_init_data init; 5552fe6b52SConor Dooley unsigned int id; 5652fe6b52SConor Dooley u32 reg_offset; 57635e5e73SDaire McNamara }; 58635e5e73SDaire McNamara 59635e5e73SDaire McNamara struct mpfs_periph_hw_clock { 60*d8155697SConor Dooley struct clk_gate periph; 6152fe6b52SConor Dooley unsigned int id; 62635e5e73SDaire McNamara }; 63635e5e73SDaire McNamara 64635e5e73SDaire McNamara /* 65635e5e73SDaire McNamara * mpfs_clk_lock prevents anything else from writing to the 66635e5e73SDaire McNamara * mpfs clk block while a software locked register is being written. 67635e5e73SDaire McNamara */ 68635e5e73SDaire McNamara static DEFINE_SPINLOCK(mpfs_clk_lock); 69635e5e73SDaire McNamara 70445c2da8SConor Dooley static const struct clk_parent_data mpfs_ext_ref[] = { 71635e5e73SDaire McNamara { .index = 0 }, 72635e5e73SDaire McNamara }; 73635e5e73SDaire McNamara 74635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 75635e5e73SDaire McNamara { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 76635e5e73SDaire McNamara { 0, 0 } 77635e5e73SDaire McNamara }; 78635e5e73SDaire McNamara 79635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_ahb_table[] = { 80635e5e73SDaire McNamara { 1, 2 }, { 2, 4}, { 3, 8 }, 81635e5e73SDaire McNamara { 0, 0 } 82635e5e73SDaire McNamara }; 83635e5e73SDaire McNamara 841c6a7ea3SConor Dooley /* 851c6a7ea3SConor Dooley * The only two supported reference clock frequencies for the PolarFire SoC are 861c6a7ea3SConor Dooley * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. 871c6a7ea3SConor Dooley * It therefore only needs to have divider table entries corresponding to 881c6a7ea3SConor Dooley * divide by 100 and 125. 891c6a7ea3SConor Dooley */ 901c6a7ea3SConor Dooley static const struct clk_div_table mpfs_div_rtcref_table[] = { 911c6a7ea3SConor Dooley { 100, 100 }, { 125, 125 }, 921c6a7ea3SConor Dooley { 0, 0 } 931c6a7ea3SConor Dooley }; 941c6a7ea3SConor Dooley 95445c2da8SConor Dooley static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 96445c2da8SConor Dooley { 97445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 98445c2da8SConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 99445c2da8SConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 100445c2da8SConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 101445c2da8SConor Dooley u32 mult, ref_div, postdiv; 102445c2da8SConor Dooley 103445c2da8SConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 104445c2da8SConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 105445c2da8SConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 106445c2da8SConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 107445c2da8SConor Dooley postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 108445c2da8SConor Dooley postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 109445c2da8SConor Dooley 110445c2da8SConor Dooley return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 111445c2da8SConor Dooley } 112445c2da8SConor Dooley 11314016e4aSConor Dooley static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 11414016e4aSConor Dooley { 11514016e4aSConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 11614016e4aSConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 11714016e4aSConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 11814016e4aSConor Dooley u32 mult, ref_div; 11914016e4aSConor Dooley unsigned long rate_before_ctrl; 12014016e4aSConor Dooley 12114016e4aSConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 12214016e4aSConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 12314016e4aSConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 12414016e4aSConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 12514016e4aSConor Dooley 12614016e4aSConor Dooley rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 12714016e4aSConor Dooley 12814016e4aSConor Dooley return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 12914016e4aSConor Dooley msspll_hw->flags); 13014016e4aSConor Dooley } 13114016e4aSConor Dooley 13214016e4aSConor Dooley static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 13314016e4aSConor Dooley { 13414016e4aSConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 13514016e4aSConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 13614016e4aSConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 13714016e4aSConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 13814016e4aSConor Dooley u32 mult, ref_div, postdiv; 13914016e4aSConor Dooley int divider_setting; 14014016e4aSConor Dooley unsigned long rate_before_ctrl, flags; 14114016e4aSConor Dooley 14214016e4aSConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 14314016e4aSConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 14414016e4aSConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 14514016e4aSConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 14614016e4aSConor Dooley 14714016e4aSConor Dooley rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 14814016e4aSConor Dooley divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 14914016e4aSConor Dooley msspll_hw->flags); 15014016e4aSConor Dooley 15114016e4aSConor Dooley if (divider_setting < 0) 15214016e4aSConor Dooley return divider_setting; 15314016e4aSConor Dooley 15414016e4aSConor Dooley spin_lock_irqsave(&mpfs_clk_lock, flags); 15514016e4aSConor Dooley 15614016e4aSConor Dooley postdiv = readl_relaxed(postdiv_addr); 15714016e4aSConor Dooley postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); 15814016e4aSConor Dooley writel_relaxed(postdiv, postdiv_addr); 15914016e4aSConor Dooley 16014016e4aSConor Dooley spin_unlock_irqrestore(&mpfs_clk_lock, flags); 16114016e4aSConor Dooley 16214016e4aSConor Dooley return 0; 16314016e4aSConor Dooley } 16414016e4aSConor Dooley 165445c2da8SConor Dooley static const struct clk_ops mpfs_clk_msspll_ops = { 166445c2da8SConor Dooley .recalc_rate = mpfs_clk_msspll_recalc_rate, 16714016e4aSConor Dooley .round_rate = mpfs_clk_msspll_round_rate, 16814016e4aSConor Dooley .set_rate = mpfs_clk_msspll_set_rate, 169445c2da8SConor Dooley }; 170445c2da8SConor Dooley 171445c2da8SConor Dooley #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 172445c2da8SConor Dooley .id = _id, \ 173445c2da8SConor Dooley .shift = _shift, \ 174445c2da8SConor Dooley .width = _width, \ 175445c2da8SConor Dooley .reg_offset = _offset, \ 176445c2da8SConor Dooley .flags = _flags, \ 177445c2da8SConor Dooley .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 178445c2da8SConor Dooley } 179445c2da8SConor Dooley 180445c2da8SConor Dooley static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 181445c2da8SConor Dooley CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 182445c2da8SConor Dooley MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 183445c2da8SConor Dooley }; 184445c2da8SConor Dooley 185445c2da8SConor Dooley static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 186445c2da8SConor Dooley unsigned int num_clks, struct mpfs_clock_data *data) 187445c2da8SConor Dooley { 188445c2da8SConor Dooley unsigned int i; 189445c2da8SConor Dooley int ret; 190445c2da8SConor Dooley 191445c2da8SConor Dooley for (i = 0; i < num_clks; i++) { 192445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 193445c2da8SConor Dooley 194e7df7ba0SConor Dooley msspll_hw->base = data->msspll_base; 195e7df7ba0SConor Dooley ret = devm_clk_hw_register(dev, &msspll_hw->hw); 196445c2da8SConor Dooley if (ret) 197445c2da8SConor Dooley return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 198445c2da8SConor Dooley CLK_MSSPLL); 199445c2da8SConor Dooley 200445c2da8SConor Dooley data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 201445c2da8SConor Dooley } 202445c2da8SConor Dooley 203445c2da8SConor Dooley return 0; 204445c2da8SConor Dooley } 205445c2da8SConor Dooley 206445c2da8SConor Dooley /* 207445c2da8SConor Dooley * "CFG" clocks 208445c2da8SConor Dooley */ 209445c2da8SConor Dooley 210445c2da8SConor Dooley #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 21152fe6b52SConor Dooley .id = _id, \ 212635e5e73SDaire McNamara .cfg.shift = _shift, \ 213635e5e73SDaire McNamara .cfg.width = _width, \ 214635e5e73SDaire McNamara .cfg.table = _table, \ 21552fe6b52SConor Dooley .reg_offset = _offset, \ 216445c2da8SConor Dooley .cfg.flags = _flags, \ 2174da2404bSConor Dooley .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ 2184da2404bSConor Dooley .cfg.lock = &mpfs_clk_lock, \ 219635e5e73SDaire McNamara } 220635e5e73SDaire McNamara 2215da39ac5SConor Dooley #define CLK_CPU_OFFSET 0u 2225da39ac5SConor Dooley #define CLK_AXI_OFFSET 1u 2235da39ac5SConor Dooley #define CLK_AHB_OFFSET 2u 2245da39ac5SConor Dooley #define CLK_RTCREF_OFFSET 3u 2255da39ac5SConor Dooley 226635e5e73SDaire McNamara static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 227445c2da8SConor Dooley CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 228445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 229445c2da8SConor Dooley CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 230445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 231445c2da8SConor Dooley CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 232445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 2331c6a7ea3SConor Dooley { 23452fe6b52SConor Dooley .id = CLK_RTCREF, 2351c6a7ea3SConor Dooley .cfg.shift = 0, 2361c6a7ea3SConor Dooley .cfg.width = 12, 2371c6a7ea3SConor Dooley .cfg.table = mpfs_div_rtcref_table, 23852fe6b52SConor Dooley .reg_offset = REG_RTC_CLOCK_CR, 2391c6a7ea3SConor Dooley .cfg.flags = CLK_DIVIDER_ONE_BASED, 2404da2404bSConor Dooley .cfg.hw.init = 2414da2404bSConor Dooley CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0), 2421c6a7ea3SConor Dooley } 243635e5e73SDaire McNamara }; 244635e5e73SDaire McNamara 245635e5e73SDaire McNamara static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 246635e5e73SDaire McNamara unsigned int num_clks, struct mpfs_clock_data *data) 247635e5e73SDaire McNamara { 248635e5e73SDaire McNamara unsigned int i, id; 249635e5e73SDaire McNamara int ret; 250635e5e73SDaire McNamara 251635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 252635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 253635e5e73SDaire McNamara 254e7df7ba0SConor Dooley cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; 2554da2404bSConor Dooley ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw); 256635e5e73SDaire McNamara if (ret) 257635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 25852fe6b52SConor Dooley cfg_hw->id); 259635e5e73SDaire McNamara 26052fe6b52SConor Dooley id = cfg_hw->id; 2614da2404bSConor Dooley data->hw_data.hws[id] = &cfg_hw->cfg.hw; 262635e5e73SDaire McNamara } 263635e5e73SDaire McNamara 264635e5e73SDaire McNamara return 0; 265635e5e73SDaire McNamara } 266635e5e73SDaire McNamara 267445c2da8SConor Dooley /* 268445c2da8SConor Dooley * peripheral clocks - devices connected to axi or ahb buses. 269445c2da8SConor Dooley */ 270445c2da8SConor Dooley 271635e5e73SDaire McNamara #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 27252fe6b52SConor Dooley .id = _id, \ 273*d8155697SConor Dooley .periph.bit_idx = _shift, \ 274*d8155697SConor Dooley .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ 275635e5e73SDaire McNamara _flags), \ 276*d8155697SConor Dooley .periph.lock = &mpfs_clk_lock, \ 277635e5e73SDaire McNamara } 278635e5e73SDaire McNamara 2794da2404bSConor Dooley #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) 280635e5e73SDaire McNamara 281635e5e73SDaire McNamara /* 282635e5e73SDaire McNamara * Critical clocks: 283635e5e73SDaire McNamara * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 284635e5e73SDaire McNamara * trap handler 285635e5e73SDaire McNamara * - CLK_MMUART0: reserved by the hss 286635e5e73SDaire McNamara * - CLK_DDRC: provides clock to the ddr subsystem 28705d27090SConor Dooley * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 28805d27090SConor Dooley * if the AHB interface clock is disabled 289a2438f82SConor Dooley * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 290a2438f82SConor Dooley * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 291a2438f82SConor Dooley * causes the FPGA fabric to go into reset. 292a2438f82SConor Dooley * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 293635e5e73SDaire McNamara */ 294635e5e73SDaire McNamara 295635e5e73SDaire McNamara static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 296635e5e73SDaire McNamara CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 297635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 298635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 299635e5e73SDaire McNamara CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 3001c6a7ea3SConor Dooley CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), 301635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 302635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 303635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 304635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 305635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 306635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 307635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 308635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 309635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 310635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 311635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 312635e5e73SDaire McNamara CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 31305d27090SConor Dooley CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 314635e5e73SDaire McNamara CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 315635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 316635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 317635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 318635e5e73SDaire McNamara CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 3198f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 3208f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 3218f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 3228f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 323a2438f82SConor Dooley CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 324635e5e73SDaire McNamara CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 325635e5e73SDaire McNamara }; 326635e5e73SDaire McNamara 327635e5e73SDaire McNamara static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 328635e5e73SDaire McNamara int num_clks, struct mpfs_clock_data *data) 329635e5e73SDaire McNamara { 330635e5e73SDaire McNamara unsigned int i, id; 331635e5e73SDaire McNamara int ret; 332635e5e73SDaire McNamara 333635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 334635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 335635e5e73SDaire McNamara 336e7df7ba0SConor Dooley periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; 337*d8155697SConor Dooley ret = devm_clk_hw_register(dev, &periph_hw->periph.hw); 338635e5e73SDaire McNamara if (ret) 339635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 34052fe6b52SConor Dooley periph_hw->id); 341635e5e73SDaire McNamara 34252fe6b52SConor Dooley id = periph_hws[i].id; 343*d8155697SConor Dooley data->hw_data.hws[id] = &periph_hw->periph.hw; 344635e5e73SDaire McNamara } 345635e5e73SDaire McNamara 346635e5e73SDaire McNamara return 0; 347635e5e73SDaire McNamara } 348635e5e73SDaire McNamara 349b56bae2dSConor Dooley /* 350b56bae2dSConor Dooley * Peripheral clock resets 351b56bae2dSConor Dooley */ 352b56bae2dSConor Dooley 353b56bae2dSConor Dooley #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 354b56bae2dSConor Dooley 355b56bae2dSConor Dooley u32 mpfs_reset_read(struct device *dev) 356b56bae2dSConor Dooley { 357b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 358b56bae2dSConor Dooley 359b56bae2dSConor Dooley return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 360b56bae2dSConor Dooley } 361b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 362b56bae2dSConor Dooley 363b56bae2dSConor Dooley void mpfs_reset_write(struct device *dev, u32 val) 364b56bae2dSConor Dooley { 365b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 366b56bae2dSConor Dooley 367b56bae2dSConor Dooley writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 368b56bae2dSConor Dooley } 369b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 370b56bae2dSConor Dooley 371b56bae2dSConor Dooley static void mpfs_reset_unregister_adev(void *_adev) 372b56bae2dSConor Dooley { 373b56bae2dSConor Dooley struct auxiliary_device *adev = _adev; 374b56bae2dSConor Dooley 375b56bae2dSConor Dooley auxiliary_device_delete(adev); 376b56bae2dSConor Dooley } 377b56bae2dSConor Dooley 378b56bae2dSConor Dooley static void mpfs_reset_adev_release(struct device *dev) 379b56bae2dSConor Dooley { 380b56bae2dSConor Dooley struct auxiliary_device *adev = to_auxiliary_dev(dev); 381b56bae2dSConor Dooley 382b56bae2dSConor Dooley auxiliary_device_uninit(adev); 383b56bae2dSConor Dooley 384b56bae2dSConor Dooley kfree(adev); 385b56bae2dSConor Dooley } 386b56bae2dSConor Dooley 387b56bae2dSConor Dooley static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 388b56bae2dSConor Dooley { 389b56bae2dSConor Dooley struct auxiliary_device *adev; 390b56bae2dSConor Dooley int ret; 391b56bae2dSConor Dooley 392b56bae2dSConor Dooley adev = kzalloc(sizeof(*adev), GFP_KERNEL); 393b56bae2dSConor Dooley if (!adev) 394b56bae2dSConor Dooley return ERR_PTR(-ENOMEM); 395b56bae2dSConor Dooley 396b56bae2dSConor Dooley adev->name = "reset-mpfs"; 397b56bae2dSConor Dooley adev->dev.parent = clk_data->dev; 398b56bae2dSConor Dooley adev->dev.release = mpfs_reset_adev_release; 399b56bae2dSConor Dooley adev->id = 666u; 400b56bae2dSConor Dooley 401b56bae2dSConor Dooley ret = auxiliary_device_init(adev); 402b56bae2dSConor Dooley if (ret) { 403b56bae2dSConor Dooley kfree(adev); 404b56bae2dSConor Dooley return ERR_PTR(ret); 405b56bae2dSConor Dooley } 406b56bae2dSConor Dooley 407b56bae2dSConor Dooley return adev; 408b56bae2dSConor Dooley } 409b56bae2dSConor Dooley 410b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 411b56bae2dSConor Dooley { 412b56bae2dSConor Dooley struct auxiliary_device *adev; 413b56bae2dSConor Dooley int ret; 414b56bae2dSConor Dooley 415b56bae2dSConor Dooley adev = mpfs_reset_adev_alloc(clk_data); 416b56bae2dSConor Dooley if (IS_ERR(adev)) 417b56bae2dSConor Dooley return PTR_ERR(adev); 418b56bae2dSConor Dooley 419b56bae2dSConor Dooley ret = auxiliary_device_add(adev); 420b56bae2dSConor Dooley if (ret) { 421b56bae2dSConor Dooley auxiliary_device_uninit(adev); 422b56bae2dSConor Dooley return ret; 423b56bae2dSConor Dooley } 424b56bae2dSConor Dooley 425b56bae2dSConor Dooley return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 426b56bae2dSConor Dooley } 427b56bae2dSConor Dooley 428b56bae2dSConor Dooley #else /* !CONFIG_RESET_CONTROLLER */ 429b56bae2dSConor Dooley 430b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 431b56bae2dSConor Dooley { 432b56bae2dSConor Dooley return 0; 433b56bae2dSConor Dooley } 434b56bae2dSConor Dooley 435b56bae2dSConor Dooley #endif /* !CONFIG_RESET_CONTROLLER */ 436b56bae2dSConor Dooley 437635e5e73SDaire McNamara static int mpfs_clk_probe(struct platform_device *pdev) 438635e5e73SDaire McNamara { 439635e5e73SDaire McNamara struct device *dev = &pdev->dev; 440635e5e73SDaire McNamara struct mpfs_clock_data *clk_data; 441635e5e73SDaire McNamara unsigned int num_clks; 442635e5e73SDaire McNamara int ret; 443635e5e73SDaire McNamara 444445c2da8SConor Dooley /* CLK_RESERVED is not part of clock arrays, so add 1 */ 445445c2da8SConor Dooley num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 446445c2da8SConor Dooley + ARRAY_SIZE(mpfs_periph_clks) + 1; 447635e5e73SDaire McNamara 448635e5e73SDaire McNamara clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 449635e5e73SDaire McNamara if (!clk_data) 450635e5e73SDaire McNamara return -ENOMEM; 451635e5e73SDaire McNamara 452635e5e73SDaire McNamara clk_data->base = devm_platform_ioremap_resource(pdev, 0); 453635e5e73SDaire McNamara if (IS_ERR(clk_data->base)) 454635e5e73SDaire McNamara return PTR_ERR(clk_data->base); 455635e5e73SDaire McNamara 456445c2da8SConor Dooley clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 457445c2da8SConor Dooley if (IS_ERR(clk_data->msspll_base)) 458445c2da8SConor Dooley return PTR_ERR(clk_data->msspll_base); 459445c2da8SConor Dooley 460635e5e73SDaire McNamara clk_data->hw_data.num = num_clks; 461b56bae2dSConor Dooley clk_data->dev = dev; 462b56bae2dSConor Dooley dev_set_drvdata(dev, clk_data); 463635e5e73SDaire McNamara 464445c2da8SConor Dooley ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 465445c2da8SConor Dooley clk_data); 466445c2da8SConor Dooley if (ret) 467445c2da8SConor Dooley return ret; 468445c2da8SConor Dooley 469635e5e73SDaire McNamara ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 470635e5e73SDaire McNamara if (ret) 471635e5e73SDaire McNamara return ret; 472635e5e73SDaire McNamara 473635e5e73SDaire McNamara ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 474635e5e73SDaire McNamara clk_data); 475635e5e73SDaire McNamara if (ret) 476635e5e73SDaire McNamara return ret; 477635e5e73SDaire McNamara 478635e5e73SDaire McNamara ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 479635e5e73SDaire McNamara if (ret) 480635e5e73SDaire McNamara return ret; 481635e5e73SDaire McNamara 482b56bae2dSConor Dooley return mpfs_reset_controller_register(clk_data); 483635e5e73SDaire McNamara } 484635e5e73SDaire McNamara 485635e5e73SDaire McNamara static const struct of_device_id mpfs_clk_of_match_table[] = { 486635e5e73SDaire McNamara { .compatible = "microchip,mpfs-clkcfg", }, 487635e5e73SDaire McNamara {} 488635e5e73SDaire McNamara }; 489b56bae2dSConor Dooley MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); 490635e5e73SDaire McNamara 491635e5e73SDaire McNamara static struct platform_driver mpfs_clk_driver = { 492635e5e73SDaire McNamara .probe = mpfs_clk_probe, 493635e5e73SDaire McNamara .driver = { 494635e5e73SDaire McNamara .name = "microchip-mpfs-clkcfg", 495635e5e73SDaire McNamara .of_match_table = mpfs_clk_of_match_table, 496635e5e73SDaire McNamara }, 497635e5e73SDaire McNamara }; 498635e5e73SDaire McNamara 499635e5e73SDaire McNamara static int __init clk_mpfs_init(void) 500635e5e73SDaire McNamara { 501635e5e73SDaire McNamara return platform_driver_register(&mpfs_clk_driver); 502635e5e73SDaire McNamara } 503635e5e73SDaire McNamara core_initcall(clk_mpfs_init); 504635e5e73SDaire McNamara 505635e5e73SDaire McNamara static void __exit clk_mpfs_exit(void) 506635e5e73SDaire McNamara { 507635e5e73SDaire McNamara platform_driver_unregister(&mpfs_clk_driver); 508635e5e73SDaire McNamara } 509635e5e73SDaire McNamara module_exit(clk_mpfs_exit); 510635e5e73SDaire McNamara 511635e5e73SDaire McNamara MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 512635e5e73SDaire McNamara MODULE_LICENSE("GPL v2"); 513