1635e5e73SDaire McNamara // SPDX-License-Identifier: GPL-2.0-only 2635e5e73SDaire McNamara /* 3635e5e73SDaire McNamara * Daire McNamara,<daire.mcnamara@microchip.com> 4635e5e73SDaire McNamara * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5635e5e73SDaire McNamara */ 6*b56bae2dSConor Dooley #include <linux/auxiliary_bus.h> 7635e5e73SDaire McNamara #include <linux/clk-provider.h> 8635e5e73SDaire McNamara #include <linux/io.h> 9635e5e73SDaire McNamara #include <linux/module.h> 10635e5e73SDaire McNamara #include <linux/platform_device.h> 11635e5e73SDaire McNamara #include <linux/slab.h> 12635e5e73SDaire McNamara #include <dt-bindings/clock/microchip,mpfs-clock.h> 13*b56bae2dSConor Dooley #include <soc/microchip/mpfs.h> 14635e5e73SDaire McNamara 15635e5e73SDaire McNamara /* address offset of control registers */ 16445c2da8SConor Dooley #define REG_MSSPLL_REF_CR 0x08u 17445c2da8SConor Dooley #define REG_MSSPLL_POSTDIV_CR 0x10u 18445c2da8SConor Dooley #define REG_MSSPLL_SSCG_2_CR 0x2Cu 19635e5e73SDaire McNamara #define REG_CLOCK_CONFIG_CR 0x08u 201c6a7ea3SConor Dooley #define REG_RTC_CLOCK_CR 0x0Cu 21635e5e73SDaire McNamara #define REG_SUBBLK_CLOCK_CR 0x84u 22635e5e73SDaire McNamara #define REG_SUBBLK_RESET_CR 0x88u 23635e5e73SDaire McNamara 24445c2da8SConor Dooley #define MSSPLL_FBDIV_SHIFT 0x00u 25445c2da8SConor Dooley #define MSSPLL_FBDIV_WIDTH 0x0Cu 26445c2da8SConor Dooley #define MSSPLL_REFDIV_SHIFT 0x08u 27445c2da8SConor Dooley #define MSSPLL_REFDIV_WIDTH 0x06u 28445c2da8SConor Dooley #define MSSPLL_POSTDIV_SHIFT 0x08u 29445c2da8SConor Dooley #define MSSPLL_POSTDIV_WIDTH 0x07u 30445c2da8SConor Dooley #define MSSPLL_FIXED_DIV 4u 31445c2da8SConor Dooley 32635e5e73SDaire McNamara struct mpfs_clock_data { 33*b56bae2dSConor Dooley struct device *dev; 34635e5e73SDaire McNamara void __iomem *base; 35445c2da8SConor Dooley void __iomem *msspll_base; 36635e5e73SDaire McNamara struct clk_hw_onecell_data hw_data; 37635e5e73SDaire McNamara }; 38635e5e73SDaire McNamara 39445c2da8SConor Dooley struct mpfs_msspll_hw_clock { 40445c2da8SConor Dooley void __iomem *base; 41445c2da8SConor Dooley unsigned int id; 42445c2da8SConor Dooley u32 reg_offset; 43445c2da8SConor Dooley u32 shift; 44445c2da8SConor Dooley u32 width; 45445c2da8SConor Dooley u32 flags; 46445c2da8SConor Dooley struct clk_hw hw; 47445c2da8SConor Dooley struct clk_init_data init; 48445c2da8SConor Dooley }; 49445c2da8SConor Dooley 50445c2da8SConor Dooley #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 51445c2da8SConor Dooley 52635e5e73SDaire McNamara struct mpfs_cfg_clock { 53635e5e73SDaire McNamara const struct clk_div_table *table; 54635e5e73SDaire McNamara unsigned int id; 55445c2da8SConor Dooley u32 reg_offset; 56635e5e73SDaire McNamara u8 shift; 57635e5e73SDaire McNamara u8 width; 58445c2da8SConor Dooley u8 flags; 59635e5e73SDaire McNamara }; 60635e5e73SDaire McNamara 61635e5e73SDaire McNamara struct mpfs_cfg_hw_clock { 62635e5e73SDaire McNamara struct mpfs_cfg_clock cfg; 63635e5e73SDaire McNamara void __iomem *sys_base; 64635e5e73SDaire McNamara struct clk_hw hw; 65635e5e73SDaire McNamara struct clk_init_data init; 66635e5e73SDaire McNamara }; 67635e5e73SDaire McNamara 68635e5e73SDaire McNamara #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) 69635e5e73SDaire McNamara 70635e5e73SDaire McNamara struct mpfs_periph_clock { 71635e5e73SDaire McNamara unsigned int id; 72635e5e73SDaire McNamara u8 shift; 73635e5e73SDaire McNamara }; 74635e5e73SDaire McNamara 75635e5e73SDaire McNamara struct mpfs_periph_hw_clock { 76635e5e73SDaire McNamara struct mpfs_periph_clock periph; 77635e5e73SDaire McNamara void __iomem *sys_base; 78635e5e73SDaire McNamara struct clk_hw hw; 79635e5e73SDaire McNamara }; 80635e5e73SDaire McNamara 81635e5e73SDaire McNamara #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 82635e5e73SDaire McNamara 83635e5e73SDaire McNamara /* 84635e5e73SDaire McNamara * mpfs_clk_lock prevents anything else from writing to the 85635e5e73SDaire McNamara * mpfs clk block while a software locked register is being written. 86635e5e73SDaire McNamara */ 87635e5e73SDaire McNamara static DEFINE_SPINLOCK(mpfs_clk_lock); 88635e5e73SDaire McNamara 89445c2da8SConor Dooley static const struct clk_parent_data mpfs_ext_ref[] = { 90635e5e73SDaire McNamara { .index = 0 }, 91635e5e73SDaire McNamara }; 92635e5e73SDaire McNamara 93635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 94635e5e73SDaire McNamara { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 95635e5e73SDaire McNamara { 0, 0 } 96635e5e73SDaire McNamara }; 97635e5e73SDaire McNamara 98635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_ahb_table[] = { 99635e5e73SDaire McNamara { 1, 2 }, { 2, 4}, { 3, 8 }, 100635e5e73SDaire McNamara { 0, 0 } 101635e5e73SDaire McNamara }; 102635e5e73SDaire McNamara 1031c6a7ea3SConor Dooley /* 1041c6a7ea3SConor Dooley * The only two supported reference clock frequencies for the PolarFire SoC are 1051c6a7ea3SConor Dooley * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. 1061c6a7ea3SConor Dooley * It therefore only needs to have divider table entries corresponding to 1071c6a7ea3SConor Dooley * divide by 100 and 125. 1081c6a7ea3SConor Dooley */ 1091c6a7ea3SConor Dooley static const struct clk_div_table mpfs_div_rtcref_table[] = { 1101c6a7ea3SConor Dooley { 100, 100 }, { 125, 125 }, 1111c6a7ea3SConor Dooley { 0, 0 } 1121c6a7ea3SConor Dooley }; 1131c6a7ea3SConor Dooley 114445c2da8SConor Dooley static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 115445c2da8SConor Dooley { 116445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 117445c2da8SConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 118445c2da8SConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 119445c2da8SConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 120445c2da8SConor Dooley u32 mult, ref_div, postdiv; 121445c2da8SConor Dooley 122445c2da8SConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 123445c2da8SConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 124445c2da8SConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 125445c2da8SConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 126445c2da8SConor Dooley postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 127445c2da8SConor Dooley postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 128445c2da8SConor Dooley 129445c2da8SConor Dooley return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 130445c2da8SConor Dooley } 131445c2da8SConor Dooley 132445c2da8SConor Dooley static const struct clk_ops mpfs_clk_msspll_ops = { 133445c2da8SConor Dooley .recalc_rate = mpfs_clk_msspll_recalc_rate, 134445c2da8SConor Dooley }; 135445c2da8SConor Dooley 136445c2da8SConor Dooley #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 137445c2da8SConor Dooley .id = _id, \ 138445c2da8SConor Dooley .shift = _shift, \ 139445c2da8SConor Dooley .width = _width, \ 140445c2da8SConor Dooley .reg_offset = _offset, \ 141445c2da8SConor Dooley .flags = _flags, \ 142445c2da8SConor Dooley .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 143445c2da8SConor Dooley } 144445c2da8SConor Dooley 145445c2da8SConor Dooley static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 146445c2da8SConor Dooley CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 147445c2da8SConor Dooley MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 148445c2da8SConor Dooley }; 149445c2da8SConor Dooley 150445c2da8SConor Dooley static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, 151445c2da8SConor Dooley void __iomem *base) 152445c2da8SConor Dooley { 153445c2da8SConor Dooley msspll_hw->base = base; 154445c2da8SConor Dooley 155445c2da8SConor Dooley return devm_clk_hw_register(dev, &msspll_hw->hw); 156445c2da8SConor Dooley } 157445c2da8SConor Dooley 158445c2da8SConor Dooley static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 159445c2da8SConor Dooley unsigned int num_clks, struct mpfs_clock_data *data) 160445c2da8SConor Dooley { 161445c2da8SConor Dooley void __iomem *base = data->msspll_base; 162445c2da8SConor Dooley unsigned int i; 163445c2da8SConor Dooley int ret; 164445c2da8SConor Dooley 165445c2da8SConor Dooley for (i = 0; i < num_clks; i++) { 166445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 167445c2da8SConor Dooley 168445c2da8SConor Dooley ret = mpfs_clk_register_msspll(dev, msspll_hw, base); 169445c2da8SConor Dooley if (ret) 170445c2da8SConor Dooley return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 171445c2da8SConor Dooley CLK_MSSPLL); 172445c2da8SConor Dooley 173445c2da8SConor Dooley data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 174445c2da8SConor Dooley } 175445c2da8SConor Dooley 176445c2da8SConor Dooley return 0; 177445c2da8SConor Dooley } 178445c2da8SConor Dooley 179445c2da8SConor Dooley /* 180445c2da8SConor Dooley * "CFG" clocks 181445c2da8SConor Dooley */ 182445c2da8SConor Dooley 183635e5e73SDaire McNamara static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) 184635e5e73SDaire McNamara { 185635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 186635e5e73SDaire McNamara struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 187635e5e73SDaire McNamara void __iomem *base_addr = cfg_hw->sys_base; 188635e5e73SDaire McNamara u32 val; 189635e5e73SDaire McNamara 190445c2da8SConor Dooley val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; 191635e5e73SDaire McNamara val &= clk_div_mask(cfg->width); 192635e5e73SDaire McNamara 193445c2da8SConor Dooley return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); 194635e5e73SDaire McNamara } 195635e5e73SDaire McNamara 196635e5e73SDaire McNamara static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 197635e5e73SDaire McNamara { 198635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 199635e5e73SDaire McNamara struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 200635e5e73SDaire McNamara 201635e5e73SDaire McNamara return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); 202635e5e73SDaire McNamara } 203635e5e73SDaire McNamara 204635e5e73SDaire McNamara static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 205635e5e73SDaire McNamara { 206635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 207635e5e73SDaire McNamara struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 208635e5e73SDaire McNamara void __iomem *base_addr = cfg_hw->sys_base; 209635e5e73SDaire McNamara unsigned long flags; 210635e5e73SDaire McNamara u32 val; 211635e5e73SDaire McNamara int divider_setting; 212635e5e73SDaire McNamara 213635e5e73SDaire McNamara divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); 214635e5e73SDaire McNamara 215635e5e73SDaire McNamara if (divider_setting < 0) 216635e5e73SDaire McNamara return divider_setting; 217635e5e73SDaire McNamara 218635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 219445c2da8SConor Dooley val = readl_relaxed(base_addr + cfg->reg_offset); 220635e5e73SDaire McNamara val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); 221635e5e73SDaire McNamara val |= divider_setting << cfg->shift; 222445c2da8SConor Dooley writel_relaxed(val, base_addr + cfg->reg_offset); 223635e5e73SDaire McNamara 224635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 225635e5e73SDaire McNamara 226635e5e73SDaire McNamara return 0; 227635e5e73SDaire McNamara } 228635e5e73SDaire McNamara 229635e5e73SDaire McNamara static const struct clk_ops mpfs_clk_cfg_ops = { 230635e5e73SDaire McNamara .recalc_rate = mpfs_cfg_clk_recalc_rate, 231635e5e73SDaire McNamara .round_rate = mpfs_cfg_clk_round_rate, 232635e5e73SDaire McNamara .set_rate = mpfs_cfg_clk_set_rate, 233635e5e73SDaire McNamara }; 234635e5e73SDaire McNamara 235445c2da8SConor Dooley #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 236635e5e73SDaire McNamara .cfg.id = _id, \ 237635e5e73SDaire McNamara .cfg.shift = _shift, \ 238635e5e73SDaire McNamara .cfg.width = _width, \ 239635e5e73SDaire McNamara .cfg.table = _table, \ 240445c2da8SConor Dooley .cfg.reg_offset = _offset, \ 241445c2da8SConor Dooley .cfg.flags = _flags, \ 242445c2da8SConor Dooley .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ 243635e5e73SDaire McNamara } 244635e5e73SDaire McNamara 2455da39ac5SConor Dooley #define CLK_CPU_OFFSET 0u 2465da39ac5SConor Dooley #define CLK_AXI_OFFSET 1u 2475da39ac5SConor Dooley #define CLK_AHB_OFFSET 2u 2485da39ac5SConor Dooley #define CLK_RTCREF_OFFSET 3u 2495da39ac5SConor Dooley 250635e5e73SDaire McNamara static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 251445c2da8SConor Dooley CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 252445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 253445c2da8SConor Dooley CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 254445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 255445c2da8SConor Dooley CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 256445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 2571c6a7ea3SConor Dooley { 2581c6a7ea3SConor Dooley .cfg.id = CLK_RTCREF, 2591c6a7ea3SConor Dooley .cfg.shift = 0, 2601c6a7ea3SConor Dooley .cfg.width = 12, 2611c6a7ea3SConor Dooley .cfg.table = mpfs_div_rtcref_table, 2621c6a7ea3SConor Dooley .cfg.reg_offset = REG_RTC_CLOCK_CR, 2631c6a7ea3SConor Dooley .cfg.flags = CLK_DIVIDER_ONE_BASED, 2641c6a7ea3SConor Dooley .hw.init = 2651c6a7ea3SConor Dooley CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), 2661c6a7ea3SConor Dooley } 267635e5e73SDaire McNamara }; 268635e5e73SDaire McNamara 269635e5e73SDaire McNamara static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, 270635e5e73SDaire McNamara void __iomem *sys_base) 271635e5e73SDaire McNamara { 272635e5e73SDaire McNamara cfg_hw->sys_base = sys_base; 273635e5e73SDaire McNamara 274635e5e73SDaire McNamara return devm_clk_hw_register(dev, &cfg_hw->hw); 275635e5e73SDaire McNamara } 276635e5e73SDaire McNamara 277635e5e73SDaire McNamara static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 278635e5e73SDaire McNamara unsigned int num_clks, struct mpfs_clock_data *data) 279635e5e73SDaire McNamara { 280635e5e73SDaire McNamara void __iomem *sys_base = data->base; 281635e5e73SDaire McNamara unsigned int i, id; 282635e5e73SDaire McNamara int ret; 283635e5e73SDaire McNamara 284635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 285635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 286635e5e73SDaire McNamara 287635e5e73SDaire McNamara ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); 288635e5e73SDaire McNamara if (ret) 289635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 290635e5e73SDaire McNamara cfg_hw->cfg.id); 291635e5e73SDaire McNamara 292445c2da8SConor Dooley id = cfg_hw->cfg.id; 293635e5e73SDaire McNamara data->hw_data.hws[id] = &cfg_hw->hw; 294635e5e73SDaire McNamara } 295635e5e73SDaire McNamara 296635e5e73SDaire McNamara return 0; 297635e5e73SDaire McNamara } 298635e5e73SDaire McNamara 299445c2da8SConor Dooley /* 300445c2da8SConor Dooley * peripheral clocks - devices connected to axi or ahb buses. 301445c2da8SConor Dooley */ 302445c2da8SConor Dooley 303635e5e73SDaire McNamara static int mpfs_periph_clk_enable(struct clk_hw *hw) 304635e5e73SDaire McNamara { 305635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 306635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 307635e5e73SDaire McNamara void __iomem *base_addr = periph_hw->sys_base; 308635e5e73SDaire McNamara u32 reg, val; 309635e5e73SDaire McNamara unsigned long flags; 310635e5e73SDaire McNamara 311635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 312635e5e73SDaire McNamara 313635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 314635e5e73SDaire McNamara val = reg | (1u << periph->shift); 315635e5e73SDaire McNamara writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 316635e5e73SDaire McNamara 317635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 318635e5e73SDaire McNamara 319635e5e73SDaire McNamara return 0; 320635e5e73SDaire McNamara } 321635e5e73SDaire McNamara 322635e5e73SDaire McNamara static void mpfs_periph_clk_disable(struct clk_hw *hw) 323635e5e73SDaire McNamara { 324635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 325635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 326635e5e73SDaire McNamara void __iomem *base_addr = periph_hw->sys_base; 327635e5e73SDaire McNamara u32 reg, val; 328635e5e73SDaire McNamara unsigned long flags; 329635e5e73SDaire McNamara 330635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 331635e5e73SDaire McNamara 332635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 333635e5e73SDaire McNamara val = reg & ~(1u << periph->shift); 334635e5e73SDaire McNamara writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 335635e5e73SDaire McNamara 336635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 337635e5e73SDaire McNamara } 338635e5e73SDaire McNamara 339635e5e73SDaire McNamara static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 340635e5e73SDaire McNamara { 341635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 342635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 343635e5e73SDaire McNamara void __iomem *base_addr = periph_hw->sys_base; 344635e5e73SDaire McNamara u32 reg; 345635e5e73SDaire McNamara 346635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 347635e5e73SDaire McNamara if (reg & (1u << periph->shift)) 348635e5e73SDaire McNamara return 1; 349635e5e73SDaire McNamara 350635e5e73SDaire McNamara return 0; 351635e5e73SDaire McNamara } 352635e5e73SDaire McNamara 353635e5e73SDaire McNamara static const struct clk_ops mpfs_periph_clk_ops = { 354635e5e73SDaire McNamara .enable = mpfs_periph_clk_enable, 355635e5e73SDaire McNamara .disable = mpfs_periph_clk_disable, 356635e5e73SDaire McNamara .is_enabled = mpfs_periph_clk_is_enabled, 357635e5e73SDaire McNamara }; 358635e5e73SDaire McNamara 359635e5e73SDaire McNamara #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 360635e5e73SDaire McNamara .periph.id = _id, \ 361635e5e73SDaire McNamara .periph.shift = _shift, \ 362635e5e73SDaire McNamara .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 363635e5e73SDaire McNamara _flags), \ 364635e5e73SDaire McNamara } 365635e5e73SDaire McNamara 3665da39ac5SConor Dooley #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw) 367635e5e73SDaire McNamara 368635e5e73SDaire McNamara /* 369635e5e73SDaire McNamara * Critical clocks: 370635e5e73SDaire McNamara * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 371635e5e73SDaire McNamara * trap handler 372635e5e73SDaire McNamara * - CLK_MMUART0: reserved by the hss 373635e5e73SDaire McNamara * - CLK_DDRC: provides clock to the ddr subsystem 37405d27090SConor Dooley * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 37505d27090SConor Dooley * if the AHB interface clock is disabled 376a2438f82SConor Dooley * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 377a2438f82SConor Dooley * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 378a2438f82SConor Dooley * causes the FPGA fabric to go into reset. 379a2438f82SConor Dooley * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 380635e5e73SDaire McNamara */ 381635e5e73SDaire McNamara 382635e5e73SDaire McNamara static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 383635e5e73SDaire McNamara CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 384635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 385635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 386635e5e73SDaire McNamara CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 3871c6a7ea3SConor Dooley CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), 388635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 389635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 390635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 391635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 392635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 393635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 394635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 395635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 396635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 397635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 398635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 399635e5e73SDaire McNamara CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 40005d27090SConor Dooley CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 401635e5e73SDaire McNamara CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 402635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 403635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 404635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 405635e5e73SDaire McNamara CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 4068f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 4078f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 4088f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 4098f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 410a2438f82SConor Dooley CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 411635e5e73SDaire McNamara CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 412635e5e73SDaire McNamara }; 413635e5e73SDaire McNamara 414635e5e73SDaire McNamara static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, 415635e5e73SDaire McNamara void __iomem *sys_base) 416635e5e73SDaire McNamara { 417635e5e73SDaire McNamara periph_hw->sys_base = sys_base; 418635e5e73SDaire McNamara 419635e5e73SDaire McNamara return devm_clk_hw_register(dev, &periph_hw->hw); 420635e5e73SDaire McNamara } 421635e5e73SDaire McNamara 422635e5e73SDaire McNamara static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 423635e5e73SDaire McNamara int num_clks, struct mpfs_clock_data *data) 424635e5e73SDaire McNamara { 425635e5e73SDaire McNamara void __iomem *sys_base = data->base; 426635e5e73SDaire McNamara unsigned int i, id; 427635e5e73SDaire McNamara int ret; 428635e5e73SDaire McNamara 429635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 430635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 431635e5e73SDaire McNamara 432635e5e73SDaire McNamara ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); 433635e5e73SDaire McNamara if (ret) 434635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 435635e5e73SDaire McNamara periph_hw->periph.id); 436635e5e73SDaire McNamara 437635e5e73SDaire McNamara id = periph_hws[i].periph.id; 438635e5e73SDaire McNamara data->hw_data.hws[id] = &periph_hw->hw; 439635e5e73SDaire McNamara } 440635e5e73SDaire McNamara 441635e5e73SDaire McNamara return 0; 442635e5e73SDaire McNamara } 443635e5e73SDaire McNamara 444*b56bae2dSConor Dooley /* 445*b56bae2dSConor Dooley * Peripheral clock resets 446*b56bae2dSConor Dooley */ 447*b56bae2dSConor Dooley 448*b56bae2dSConor Dooley #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 449*b56bae2dSConor Dooley 450*b56bae2dSConor Dooley u32 mpfs_reset_read(struct device *dev) 451*b56bae2dSConor Dooley { 452*b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 453*b56bae2dSConor Dooley 454*b56bae2dSConor Dooley return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 455*b56bae2dSConor Dooley } 456*b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 457*b56bae2dSConor Dooley 458*b56bae2dSConor Dooley void mpfs_reset_write(struct device *dev, u32 val) 459*b56bae2dSConor Dooley { 460*b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 461*b56bae2dSConor Dooley 462*b56bae2dSConor Dooley writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 463*b56bae2dSConor Dooley } 464*b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 465*b56bae2dSConor Dooley 466*b56bae2dSConor Dooley static void mpfs_reset_unregister_adev(void *_adev) 467*b56bae2dSConor Dooley { 468*b56bae2dSConor Dooley struct auxiliary_device *adev = _adev; 469*b56bae2dSConor Dooley 470*b56bae2dSConor Dooley auxiliary_device_delete(adev); 471*b56bae2dSConor Dooley } 472*b56bae2dSConor Dooley 473*b56bae2dSConor Dooley static void mpfs_reset_adev_release(struct device *dev) 474*b56bae2dSConor Dooley { 475*b56bae2dSConor Dooley struct auxiliary_device *adev = to_auxiliary_dev(dev); 476*b56bae2dSConor Dooley 477*b56bae2dSConor Dooley auxiliary_device_uninit(adev); 478*b56bae2dSConor Dooley 479*b56bae2dSConor Dooley kfree(adev); 480*b56bae2dSConor Dooley } 481*b56bae2dSConor Dooley 482*b56bae2dSConor Dooley static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 483*b56bae2dSConor Dooley { 484*b56bae2dSConor Dooley struct auxiliary_device *adev; 485*b56bae2dSConor Dooley int ret; 486*b56bae2dSConor Dooley 487*b56bae2dSConor Dooley adev = kzalloc(sizeof(*adev), GFP_KERNEL); 488*b56bae2dSConor Dooley if (!adev) 489*b56bae2dSConor Dooley return ERR_PTR(-ENOMEM); 490*b56bae2dSConor Dooley 491*b56bae2dSConor Dooley adev->name = "reset-mpfs"; 492*b56bae2dSConor Dooley adev->dev.parent = clk_data->dev; 493*b56bae2dSConor Dooley adev->dev.release = mpfs_reset_adev_release; 494*b56bae2dSConor Dooley adev->id = 666u; 495*b56bae2dSConor Dooley 496*b56bae2dSConor Dooley ret = auxiliary_device_init(adev); 497*b56bae2dSConor Dooley if (ret) { 498*b56bae2dSConor Dooley kfree(adev); 499*b56bae2dSConor Dooley return ERR_PTR(ret); 500*b56bae2dSConor Dooley } 501*b56bae2dSConor Dooley 502*b56bae2dSConor Dooley return adev; 503*b56bae2dSConor Dooley } 504*b56bae2dSConor Dooley 505*b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 506*b56bae2dSConor Dooley { 507*b56bae2dSConor Dooley struct auxiliary_device *adev; 508*b56bae2dSConor Dooley int ret; 509*b56bae2dSConor Dooley 510*b56bae2dSConor Dooley adev = mpfs_reset_adev_alloc(clk_data); 511*b56bae2dSConor Dooley if (IS_ERR(adev)) 512*b56bae2dSConor Dooley return PTR_ERR(adev); 513*b56bae2dSConor Dooley 514*b56bae2dSConor Dooley ret = auxiliary_device_add(adev); 515*b56bae2dSConor Dooley if (ret) { 516*b56bae2dSConor Dooley auxiliary_device_uninit(adev); 517*b56bae2dSConor Dooley return ret; 518*b56bae2dSConor Dooley } 519*b56bae2dSConor Dooley 520*b56bae2dSConor Dooley return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 521*b56bae2dSConor Dooley } 522*b56bae2dSConor Dooley 523*b56bae2dSConor Dooley #else /* !CONFIG_RESET_CONTROLLER */ 524*b56bae2dSConor Dooley 525*b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 526*b56bae2dSConor Dooley { 527*b56bae2dSConor Dooley return 0; 528*b56bae2dSConor Dooley } 529*b56bae2dSConor Dooley 530*b56bae2dSConor Dooley #endif /* !CONFIG_RESET_CONTROLLER */ 531*b56bae2dSConor Dooley 532635e5e73SDaire McNamara static int mpfs_clk_probe(struct platform_device *pdev) 533635e5e73SDaire McNamara { 534635e5e73SDaire McNamara struct device *dev = &pdev->dev; 535635e5e73SDaire McNamara struct mpfs_clock_data *clk_data; 536635e5e73SDaire McNamara unsigned int num_clks; 537635e5e73SDaire McNamara int ret; 538635e5e73SDaire McNamara 539445c2da8SConor Dooley /* CLK_RESERVED is not part of clock arrays, so add 1 */ 540445c2da8SConor Dooley num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 541445c2da8SConor Dooley + ARRAY_SIZE(mpfs_periph_clks) + 1; 542635e5e73SDaire McNamara 543635e5e73SDaire McNamara clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 544635e5e73SDaire McNamara if (!clk_data) 545635e5e73SDaire McNamara return -ENOMEM; 546635e5e73SDaire McNamara 547635e5e73SDaire McNamara clk_data->base = devm_platform_ioremap_resource(pdev, 0); 548635e5e73SDaire McNamara if (IS_ERR(clk_data->base)) 549635e5e73SDaire McNamara return PTR_ERR(clk_data->base); 550635e5e73SDaire McNamara 551445c2da8SConor Dooley clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 552445c2da8SConor Dooley if (IS_ERR(clk_data->msspll_base)) 553445c2da8SConor Dooley return PTR_ERR(clk_data->msspll_base); 554445c2da8SConor Dooley 555635e5e73SDaire McNamara clk_data->hw_data.num = num_clks; 556*b56bae2dSConor Dooley clk_data->dev = dev; 557*b56bae2dSConor Dooley dev_set_drvdata(dev, clk_data); 558635e5e73SDaire McNamara 559445c2da8SConor Dooley ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 560445c2da8SConor Dooley clk_data); 561445c2da8SConor Dooley if (ret) 562445c2da8SConor Dooley return ret; 563445c2da8SConor Dooley 564635e5e73SDaire McNamara ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 565635e5e73SDaire McNamara if (ret) 566635e5e73SDaire McNamara return ret; 567635e5e73SDaire McNamara 568635e5e73SDaire McNamara ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 569635e5e73SDaire McNamara clk_data); 570635e5e73SDaire McNamara if (ret) 571635e5e73SDaire McNamara return ret; 572635e5e73SDaire McNamara 573635e5e73SDaire McNamara ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 574635e5e73SDaire McNamara if (ret) 575635e5e73SDaire McNamara return ret; 576635e5e73SDaire McNamara 577*b56bae2dSConor Dooley return mpfs_reset_controller_register(clk_data); 578635e5e73SDaire McNamara } 579635e5e73SDaire McNamara 580635e5e73SDaire McNamara static const struct of_device_id mpfs_clk_of_match_table[] = { 581635e5e73SDaire McNamara { .compatible = "microchip,mpfs-clkcfg", }, 582635e5e73SDaire McNamara {} 583635e5e73SDaire McNamara }; 584*b56bae2dSConor Dooley MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); 585635e5e73SDaire McNamara 586635e5e73SDaire McNamara static struct platform_driver mpfs_clk_driver = { 587635e5e73SDaire McNamara .probe = mpfs_clk_probe, 588635e5e73SDaire McNamara .driver = { 589635e5e73SDaire McNamara .name = "microchip-mpfs-clkcfg", 590635e5e73SDaire McNamara .of_match_table = mpfs_clk_of_match_table, 591635e5e73SDaire McNamara }, 592635e5e73SDaire McNamara }; 593635e5e73SDaire McNamara 594635e5e73SDaire McNamara static int __init clk_mpfs_init(void) 595635e5e73SDaire McNamara { 596635e5e73SDaire McNamara return platform_driver_register(&mpfs_clk_driver); 597635e5e73SDaire McNamara } 598635e5e73SDaire McNamara core_initcall(clk_mpfs_init); 599635e5e73SDaire McNamara 600635e5e73SDaire McNamara static void __exit clk_mpfs_exit(void) 601635e5e73SDaire McNamara { 602635e5e73SDaire McNamara platform_driver_unregister(&mpfs_clk_driver); 603635e5e73SDaire McNamara } 604635e5e73SDaire McNamara module_exit(clk_mpfs_exit); 605635e5e73SDaire McNamara 606635e5e73SDaire McNamara MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 607635e5e73SDaire McNamara MODULE_LICENSE("GPL v2"); 608