1635e5e73SDaire McNamara // SPDX-License-Identifier: GPL-2.0-only 2635e5e73SDaire McNamara /* 3635e5e73SDaire McNamara * Daire McNamara,<daire.mcnamara@microchip.com> 4635e5e73SDaire McNamara * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5635e5e73SDaire McNamara */ 6b56bae2dSConor Dooley #include <linux/auxiliary_bus.h> 7635e5e73SDaire McNamara #include <linux/clk-provider.h> 8635e5e73SDaire McNamara #include <linux/io.h> 9635e5e73SDaire McNamara #include <linux/module.h> 10635e5e73SDaire McNamara #include <linux/platform_device.h> 11635e5e73SDaire McNamara #include <linux/slab.h> 12635e5e73SDaire McNamara #include <dt-bindings/clock/microchip,mpfs-clock.h> 13b56bae2dSConor Dooley #include <soc/microchip/mpfs.h> 14635e5e73SDaire McNamara 15635e5e73SDaire McNamara /* address offset of control registers */ 16445c2da8SConor Dooley #define REG_MSSPLL_REF_CR 0x08u 17445c2da8SConor Dooley #define REG_MSSPLL_POSTDIV_CR 0x10u 18445c2da8SConor Dooley #define REG_MSSPLL_SSCG_2_CR 0x2Cu 19635e5e73SDaire McNamara #define REG_CLOCK_CONFIG_CR 0x08u 201c6a7ea3SConor Dooley #define REG_RTC_CLOCK_CR 0x0Cu 21635e5e73SDaire McNamara #define REG_SUBBLK_CLOCK_CR 0x84u 22635e5e73SDaire McNamara #define REG_SUBBLK_RESET_CR 0x88u 23635e5e73SDaire McNamara 24445c2da8SConor Dooley #define MSSPLL_FBDIV_SHIFT 0x00u 25445c2da8SConor Dooley #define MSSPLL_FBDIV_WIDTH 0x0Cu 26445c2da8SConor Dooley #define MSSPLL_REFDIV_SHIFT 0x08u 27445c2da8SConor Dooley #define MSSPLL_REFDIV_WIDTH 0x06u 28445c2da8SConor Dooley #define MSSPLL_POSTDIV_SHIFT 0x08u 29445c2da8SConor Dooley #define MSSPLL_POSTDIV_WIDTH 0x07u 30445c2da8SConor Dooley #define MSSPLL_FIXED_DIV 4u 31445c2da8SConor Dooley 32635e5e73SDaire McNamara struct mpfs_clock_data { 33b56bae2dSConor Dooley struct device *dev; 34635e5e73SDaire McNamara void __iomem *base; 35445c2da8SConor Dooley void __iomem *msspll_base; 36635e5e73SDaire McNamara struct clk_hw_onecell_data hw_data; 37635e5e73SDaire McNamara }; 38635e5e73SDaire McNamara 39445c2da8SConor Dooley struct mpfs_msspll_hw_clock { 40445c2da8SConor Dooley void __iomem *base; 41445c2da8SConor Dooley unsigned int id; 42445c2da8SConor Dooley u32 reg_offset; 43445c2da8SConor Dooley u32 shift; 44445c2da8SConor Dooley u32 width; 45445c2da8SConor Dooley u32 flags; 46445c2da8SConor Dooley struct clk_hw hw; 47445c2da8SConor Dooley struct clk_init_data init; 48445c2da8SConor Dooley }; 49445c2da8SConor Dooley 50445c2da8SConor Dooley #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 51445c2da8SConor Dooley 52635e5e73SDaire McNamara struct mpfs_cfg_hw_clock { 53*4da2404bSConor Dooley struct clk_divider cfg; 54635e5e73SDaire McNamara struct clk_init_data init; 5552fe6b52SConor Dooley unsigned int id; 5652fe6b52SConor Dooley u32 reg_offset; 57635e5e73SDaire McNamara }; 58635e5e73SDaire McNamara 59635e5e73SDaire McNamara struct mpfs_periph_clock { 605fa27b77SConor Dooley void __iomem *reg; 61635e5e73SDaire McNamara u8 shift; 62635e5e73SDaire McNamara }; 63635e5e73SDaire McNamara 64635e5e73SDaire McNamara struct mpfs_periph_hw_clock { 65635e5e73SDaire McNamara struct mpfs_periph_clock periph; 66635e5e73SDaire McNamara struct clk_hw hw; 6752fe6b52SConor Dooley unsigned int id; 68635e5e73SDaire McNamara }; 69635e5e73SDaire McNamara 70635e5e73SDaire McNamara #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 71635e5e73SDaire McNamara 72635e5e73SDaire McNamara /* 73635e5e73SDaire McNamara * mpfs_clk_lock prevents anything else from writing to the 74635e5e73SDaire McNamara * mpfs clk block while a software locked register is being written. 75635e5e73SDaire McNamara */ 76635e5e73SDaire McNamara static DEFINE_SPINLOCK(mpfs_clk_lock); 77635e5e73SDaire McNamara 78445c2da8SConor Dooley static const struct clk_parent_data mpfs_ext_ref[] = { 79635e5e73SDaire McNamara { .index = 0 }, 80635e5e73SDaire McNamara }; 81635e5e73SDaire McNamara 82635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 83635e5e73SDaire McNamara { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 84635e5e73SDaire McNamara { 0, 0 } 85635e5e73SDaire McNamara }; 86635e5e73SDaire McNamara 87635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_ahb_table[] = { 88635e5e73SDaire McNamara { 1, 2 }, { 2, 4}, { 3, 8 }, 89635e5e73SDaire McNamara { 0, 0 } 90635e5e73SDaire McNamara }; 91635e5e73SDaire McNamara 921c6a7ea3SConor Dooley /* 931c6a7ea3SConor Dooley * The only two supported reference clock frequencies for the PolarFire SoC are 941c6a7ea3SConor Dooley * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. 951c6a7ea3SConor Dooley * It therefore only needs to have divider table entries corresponding to 961c6a7ea3SConor Dooley * divide by 100 and 125. 971c6a7ea3SConor Dooley */ 981c6a7ea3SConor Dooley static const struct clk_div_table mpfs_div_rtcref_table[] = { 991c6a7ea3SConor Dooley { 100, 100 }, { 125, 125 }, 1001c6a7ea3SConor Dooley { 0, 0 } 1011c6a7ea3SConor Dooley }; 1021c6a7ea3SConor Dooley 103445c2da8SConor Dooley static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 104445c2da8SConor Dooley { 105445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 106445c2da8SConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 107445c2da8SConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 108445c2da8SConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 109445c2da8SConor Dooley u32 mult, ref_div, postdiv; 110445c2da8SConor Dooley 111445c2da8SConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 112445c2da8SConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 113445c2da8SConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 114445c2da8SConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 115445c2da8SConor Dooley postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 116445c2da8SConor Dooley postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 117445c2da8SConor Dooley 118445c2da8SConor Dooley return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 119445c2da8SConor Dooley } 120445c2da8SConor Dooley 12114016e4aSConor Dooley static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 12214016e4aSConor Dooley { 12314016e4aSConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 12414016e4aSConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 12514016e4aSConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 12614016e4aSConor Dooley u32 mult, ref_div; 12714016e4aSConor Dooley unsigned long rate_before_ctrl; 12814016e4aSConor Dooley 12914016e4aSConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 13014016e4aSConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 13114016e4aSConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 13214016e4aSConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 13314016e4aSConor Dooley 13414016e4aSConor Dooley rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 13514016e4aSConor Dooley 13614016e4aSConor Dooley return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 13714016e4aSConor Dooley msspll_hw->flags); 13814016e4aSConor Dooley } 13914016e4aSConor Dooley 14014016e4aSConor Dooley static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 14114016e4aSConor Dooley { 14214016e4aSConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 14314016e4aSConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 14414016e4aSConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 14514016e4aSConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 14614016e4aSConor Dooley u32 mult, ref_div, postdiv; 14714016e4aSConor Dooley int divider_setting; 14814016e4aSConor Dooley unsigned long rate_before_ctrl, flags; 14914016e4aSConor Dooley 15014016e4aSConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 15114016e4aSConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 15214016e4aSConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 15314016e4aSConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 15414016e4aSConor Dooley 15514016e4aSConor Dooley rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 15614016e4aSConor Dooley divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 15714016e4aSConor Dooley msspll_hw->flags); 15814016e4aSConor Dooley 15914016e4aSConor Dooley if (divider_setting < 0) 16014016e4aSConor Dooley return divider_setting; 16114016e4aSConor Dooley 16214016e4aSConor Dooley spin_lock_irqsave(&mpfs_clk_lock, flags); 16314016e4aSConor Dooley 16414016e4aSConor Dooley postdiv = readl_relaxed(postdiv_addr); 16514016e4aSConor Dooley postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); 16614016e4aSConor Dooley writel_relaxed(postdiv, postdiv_addr); 16714016e4aSConor Dooley 16814016e4aSConor Dooley spin_unlock_irqrestore(&mpfs_clk_lock, flags); 16914016e4aSConor Dooley 17014016e4aSConor Dooley return 0; 17114016e4aSConor Dooley } 17214016e4aSConor Dooley 173445c2da8SConor Dooley static const struct clk_ops mpfs_clk_msspll_ops = { 174445c2da8SConor Dooley .recalc_rate = mpfs_clk_msspll_recalc_rate, 17514016e4aSConor Dooley .round_rate = mpfs_clk_msspll_round_rate, 17614016e4aSConor Dooley .set_rate = mpfs_clk_msspll_set_rate, 177445c2da8SConor Dooley }; 178445c2da8SConor Dooley 179445c2da8SConor Dooley #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 180445c2da8SConor Dooley .id = _id, \ 181445c2da8SConor Dooley .shift = _shift, \ 182445c2da8SConor Dooley .width = _width, \ 183445c2da8SConor Dooley .reg_offset = _offset, \ 184445c2da8SConor Dooley .flags = _flags, \ 185445c2da8SConor Dooley .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 186445c2da8SConor Dooley } 187445c2da8SConor Dooley 188445c2da8SConor Dooley static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 189445c2da8SConor Dooley CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 190445c2da8SConor Dooley MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 191445c2da8SConor Dooley }; 192445c2da8SConor Dooley 193445c2da8SConor Dooley static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 194445c2da8SConor Dooley unsigned int num_clks, struct mpfs_clock_data *data) 195445c2da8SConor Dooley { 196445c2da8SConor Dooley unsigned int i; 197445c2da8SConor Dooley int ret; 198445c2da8SConor Dooley 199445c2da8SConor Dooley for (i = 0; i < num_clks; i++) { 200445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 201445c2da8SConor Dooley 202e7df7ba0SConor Dooley msspll_hw->base = data->msspll_base; 203e7df7ba0SConor Dooley ret = devm_clk_hw_register(dev, &msspll_hw->hw); 204445c2da8SConor Dooley if (ret) 205445c2da8SConor Dooley return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 206445c2da8SConor Dooley CLK_MSSPLL); 207445c2da8SConor Dooley 208445c2da8SConor Dooley data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 209445c2da8SConor Dooley } 210445c2da8SConor Dooley 211445c2da8SConor Dooley return 0; 212445c2da8SConor Dooley } 213445c2da8SConor Dooley 214445c2da8SConor Dooley /* 215445c2da8SConor Dooley * "CFG" clocks 216445c2da8SConor Dooley */ 217445c2da8SConor Dooley 218445c2da8SConor Dooley #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 21952fe6b52SConor Dooley .id = _id, \ 220635e5e73SDaire McNamara .cfg.shift = _shift, \ 221635e5e73SDaire McNamara .cfg.width = _width, \ 222635e5e73SDaire McNamara .cfg.table = _table, \ 22352fe6b52SConor Dooley .reg_offset = _offset, \ 224445c2da8SConor Dooley .cfg.flags = _flags, \ 225*4da2404bSConor Dooley .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ 226*4da2404bSConor Dooley .cfg.lock = &mpfs_clk_lock, \ 227635e5e73SDaire McNamara } 228635e5e73SDaire McNamara 2295da39ac5SConor Dooley #define CLK_CPU_OFFSET 0u 2305da39ac5SConor Dooley #define CLK_AXI_OFFSET 1u 2315da39ac5SConor Dooley #define CLK_AHB_OFFSET 2u 2325da39ac5SConor Dooley #define CLK_RTCREF_OFFSET 3u 2335da39ac5SConor Dooley 234635e5e73SDaire McNamara static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 235445c2da8SConor Dooley CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 236445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 237445c2da8SConor Dooley CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 238445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 239445c2da8SConor Dooley CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 240445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 2411c6a7ea3SConor Dooley { 24252fe6b52SConor Dooley .id = CLK_RTCREF, 2431c6a7ea3SConor Dooley .cfg.shift = 0, 2441c6a7ea3SConor Dooley .cfg.width = 12, 2451c6a7ea3SConor Dooley .cfg.table = mpfs_div_rtcref_table, 24652fe6b52SConor Dooley .reg_offset = REG_RTC_CLOCK_CR, 2471c6a7ea3SConor Dooley .cfg.flags = CLK_DIVIDER_ONE_BASED, 248*4da2404bSConor Dooley .cfg.hw.init = 249*4da2404bSConor Dooley CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0), 2501c6a7ea3SConor Dooley } 251635e5e73SDaire McNamara }; 252635e5e73SDaire McNamara 253635e5e73SDaire McNamara static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 254635e5e73SDaire McNamara unsigned int num_clks, struct mpfs_clock_data *data) 255635e5e73SDaire McNamara { 256635e5e73SDaire McNamara unsigned int i, id; 257635e5e73SDaire McNamara int ret; 258635e5e73SDaire McNamara 259635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 260635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 261635e5e73SDaire McNamara 262e7df7ba0SConor Dooley cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; 263*4da2404bSConor Dooley ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw); 264635e5e73SDaire McNamara if (ret) 265635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 26652fe6b52SConor Dooley cfg_hw->id); 267635e5e73SDaire McNamara 26852fe6b52SConor Dooley id = cfg_hw->id; 269*4da2404bSConor Dooley data->hw_data.hws[id] = &cfg_hw->cfg.hw; 270635e5e73SDaire McNamara } 271635e5e73SDaire McNamara 272635e5e73SDaire McNamara return 0; 273635e5e73SDaire McNamara } 274635e5e73SDaire McNamara 275445c2da8SConor Dooley /* 276445c2da8SConor Dooley * peripheral clocks - devices connected to axi or ahb buses. 277445c2da8SConor Dooley */ 278445c2da8SConor Dooley 279635e5e73SDaire McNamara static int mpfs_periph_clk_enable(struct clk_hw *hw) 280635e5e73SDaire McNamara { 281635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 282635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 283635e5e73SDaire McNamara u32 reg, val; 284635e5e73SDaire McNamara unsigned long flags; 285635e5e73SDaire McNamara 286635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 287635e5e73SDaire McNamara 2885fa27b77SConor Dooley reg = readl_relaxed(periph->reg); 289635e5e73SDaire McNamara val = reg | (1u << periph->shift); 2905fa27b77SConor Dooley writel_relaxed(val, periph->reg); 291635e5e73SDaire McNamara 292635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 293635e5e73SDaire McNamara 294635e5e73SDaire McNamara return 0; 295635e5e73SDaire McNamara } 296635e5e73SDaire McNamara 297635e5e73SDaire McNamara static void mpfs_periph_clk_disable(struct clk_hw *hw) 298635e5e73SDaire McNamara { 299635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 300635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 301635e5e73SDaire McNamara u32 reg, val; 302635e5e73SDaire McNamara unsigned long flags; 303635e5e73SDaire McNamara 304635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 305635e5e73SDaire McNamara 3065fa27b77SConor Dooley reg = readl_relaxed(periph->reg); 307635e5e73SDaire McNamara val = reg & ~(1u << periph->shift); 3085fa27b77SConor Dooley writel_relaxed(val, periph->reg); 309635e5e73SDaire McNamara 310635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 311635e5e73SDaire McNamara } 312635e5e73SDaire McNamara 313635e5e73SDaire McNamara static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 314635e5e73SDaire McNamara { 315635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 316635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 317635e5e73SDaire McNamara u32 reg; 318635e5e73SDaire McNamara 3195fa27b77SConor Dooley reg = readl_relaxed(periph->reg); 320635e5e73SDaire McNamara if (reg & (1u << periph->shift)) 321635e5e73SDaire McNamara return 1; 322635e5e73SDaire McNamara 323635e5e73SDaire McNamara return 0; 324635e5e73SDaire McNamara } 325635e5e73SDaire McNamara 326635e5e73SDaire McNamara static const struct clk_ops mpfs_periph_clk_ops = { 327635e5e73SDaire McNamara .enable = mpfs_periph_clk_enable, 328635e5e73SDaire McNamara .disable = mpfs_periph_clk_disable, 329635e5e73SDaire McNamara .is_enabled = mpfs_periph_clk_is_enabled, 330635e5e73SDaire McNamara }; 331635e5e73SDaire McNamara 332635e5e73SDaire McNamara #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 33352fe6b52SConor Dooley .id = _id, \ 334635e5e73SDaire McNamara .periph.shift = _shift, \ 335635e5e73SDaire McNamara .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 336635e5e73SDaire McNamara _flags), \ 337635e5e73SDaire McNamara } 338635e5e73SDaire McNamara 339*4da2404bSConor Dooley #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) 340635e5e73SDaire McNamara 341635e5e73SDaire McNamara /* 342635e5e73SDaire McNamara * Critical clocks: 343635e5e73SDaire McNamara * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 344635e5e73SDaire McNamara * trap handler 345635e5e73SDaire McNamara * - CLK_MMUART0: reserved by the hss 346635e5e73SDaire McNamara * - CLK_DDRC: provides clock to the ddr subsystem 34705d27090SConor Dooley * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 34805d27090SConor Dooley * if the AHB interface clock is disabled 349a2438f82SConor Dooley * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 350a2438f82SConor Dooley * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 351a2438f82SConor Dooley * causes the FPGA fabric to go into reset. 352a2438f82SConor Dooley * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 353635e5e73SDaire McNamara */ 354635e5e73SDaire McNamara 355635e5e73SDaire McNamara static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 356635e5e73SDaire McNamara CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 357635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 358635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 359635e5e73SDaire McNamara CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 3601c6a7ea3SConor Dooley CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), 361635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 362635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 363635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 364635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 365635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 366635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 367635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 368635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 369635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 370635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 371635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 372635e5e73SDaire McNamara CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 37305d27090SConor Dooley CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 374635e5e73SDaire McNamara CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 375635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 376635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 377635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 378635e5e73SDaire McNamara CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 3798f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 3808f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 3818f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 3828f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 383a2438f82SConor Dooley CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 384635e5e73SDaire McNamara CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 385635e5e73SDaire McNamara }; 386635e5e73SDaire McNamara 387635e5e73SDaire McNamara static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 388635e5e73SDaire McNamara int num_clks, struct mpfs_clock_data *data) 389635e5e73SDaire McNamara { 390635e5e73SDaire McNamara unsigned int i, id; 391635e5e73SDaire McNamara int ret; 392635e5e73SDaire McNamara 393635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 394635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 395635e5e73SDaire McNamara 396e7df7ba0SConor Dooley periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; 397e7df7ba0SConor Dooley ret = devm_clk_hw_register(dev, &periph_hw->hw); 398635e5e73SDaire McNamara if (ret) 399635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 40052fe6b52SConor Dooley periph_hw->id); 401635e5e73SDaire McNamara 40252fe6b52SConor Dooley id = periph_hws[i].id; 403635e5e73SDaire McNamara data->hw_data.hws[id] = &periph_hw->hw; 404635e5e73SDaire McNamara } 405635e5e73SDaire McNamara 406635e5e73SDaire McNamara return 0; 407635e5e73SDaire McNamara } 408635e5e73SDaire McNamara 409b56bae2dSConor Dooley /* 410b56bae2dSConor Dooley * Peripheral clock resets 411b56bae2dSConor Dooley */ 412b56bae2dSConor Dooley 413b56bae2dSConor Dooley #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 414b56bae2dSConor Dooley 415b56bae2dSConor Dooley u32 mpfs_reset_read(struct device *dev) 416b56bae2dSConor Dooley { 417b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 418b56bae2dSConor Dooley 419b56bae2dSConor Dooley return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 420b56bae2dSConor Dooley } 421b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 422b56bae2dSConor Dooley 423b56bae2dSConor Dooley void mpfs_reset_write(struct device *dev, u32 val) 424b56bae2dSConor Dooley { 425b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 426b56bae2dSConor Dooley 427b56bae2dSConor Dooley writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 428b56bae2dSConor Dooley } 429b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 430b56bae2dSConor Dooley 431b56bae2dSConor Dooley static void mpfs_reset_unregister_adev(void *_adev) 432b56bae2dSConor Dooley { 433b56bae2dSConor Dooley struct auxiliary_device *adev = _adev; 434b56bae2dSConor Dooley 435b56bae2dSConor Dooley auxiliary_device_delete(adev); 436b56bae2dSConor Dooley } 437b56bae2dSConor Dooley 438b56bae2dSConor Dooley static void mpfs_reset_adev_release(struct device *dev) 439b56bae2dSConor Dooley { 440b56bae2dSConor Dooley struct auxiliary_device *adev = to_auxiliary_dev(dev); 441b56bae2dSConor Dooley 442b56bae2dSConor Dooley auxiliary_device_uninit(adev); 443b56bae2dSConor Dooley 444b56bae2dSConor Dooley kfree(adev); 445b56bae2dSConor Dooley } 446b56bae2dSConor Dooley 447b56bae2dSConor Dooley static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 448b56bae2dSConor Dooley { 449b56bae2dSConor Dooley struct auxiliary_device *adev; 450b56bae2dSConor Dooley int ret; 451b56bae2dSConor Dooley 452b56bae2dSConor Dooley adev = kzalloc(sizeof(*adev), GFP_KERNEL); 453b56bae2dSConor Dooley if (!adev) 454b56bae2dSConor Dooley return ERR_PTR(-ENOMEM); 455b56bae2dSConor Dooley 456b56bae2dSConor Dooley adev->name = "reset-mpfs"; 457b56bae2dSConor Dooley adev->dev.parent = clk_data->dev; 458b56bae2dSConor Dooley adev->dev.release = mpfs_reset_adev_release; 459b56bae2dSConor Dooley adev->id = 666u; 460b56bae2dSConor Dooley 461b56bae2dSConor Dooley ret = auxiliary_device_init(adev); 462b56bae2dSConor Dooley if (ret) { 463b56bae2dSConor Dooley kfree(adev); 464b56bae2dSConor Dooley return ERR_PTR(ret); 465b56bae2dSConor Dooley } 466b56bae2dSConor Dooley 467b56bae2dSConor Dooley return adev; 468b56bae2dSConor Dooley } 469b56bae2dSConor Dooley 470b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 471b56bae2dSConor Dooley { 472b56bae2dSConor Dooley struct auxiliary_device *adev; 473b56bae2dSConor Dooley int ret; 474b56bae2dSConor Dooley 475b56bae2dSConor Dooley adev = mpfs_reset_adev_alloc(clk_data); 476b56bae2dSConor Dooley if (IS_ERR(adev)) 477b56bae2dSConor Dooley return PTR_ERR(adev); 478b56bae2dSConor Dooley 479b56bae2dSConor Dooley ret = auxiliary_device_add(adev); 480b56bae2dSConor Dooley if (ret) { 481b56bae2dSConor Dooley auxiliary_device_uninit(adev); 482b56bae2dSConor Dooley return ret; 483b56bae2dSConor Dooley } 484b56bae2dSConor Dooley 485b56bae2dSConor Dooley return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 486b56bae2dSConor Dooley } 487b56bae2dSConor Dooley 488b56bae2dSConor Dooley #else /* !CONFIG_RESET_CONTROLLER */ 489b56bae2dSConor Dooley 490b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 491b56bae2dSConor Dooley { 492b56bae2dSConor Dooley return 0; 493b56bae2dSConor Dooley } 494b56bae2dSConor Dooley 495b56bae2dSConor Dooley #endif /* !CONFIG_RESET_CONTROLLER */ 496b56bae2dSConor Dooley 497635e5e73SDaire McNamara static int mpfs_clk_probe(struct platform_device *pdev) 498635e5e73SDaire McNamara { 499635e5e73SDaire McNamara struct device *dev = &pdev->dev; 500635e5e73SDaire McNamara struct mpfs_clock_data *clk_data; 501635e5e73SDaire McNamara unsigned int num_clks; 502635e5e73SDaire McNamara int ret; 503635e5e73SDaire McNamara 504445c2da8SConor Dooley /* CLK_RESERVED is not part of clock arrays, so add 1 */ 505445c2da8SConor Dooley num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 506445c2da8SConor Dooley + ARRAY_SIZE(mpfs_periph_clks) + 1; 507635e5e73SDaire McNamara 508635e5e73SDaire McNamara clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 509635e5e73SDaire McNamara if (!clk_data) 510635e5e73SDaire McNamara return -ENOMEM; 511635e5e73SDaire McNamara 512635e5e73SDaire McNamara clk_data->base = devm_platform_ioremap_resource(pdev, 0); 513635e5e73SDaire McNamara if (IS_ERR(clk_data->base)) 514635e5e73SDaire McNamara return PTR_ERR(clk_data->base); 515635e5e73SDaire McNamara 516445c2da8SConor Dooley clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 517445c2da8SConor Dooley if (IS_ERR(clk_data->msspll_base)) 518445c2da8SConor Dooley return PTR_ERR(clk_data->msspll_base); 519445c2da8SConor Dooley 520635e5e73SDaire McNamara clk_data->hw_data.num = num_clks; 521b56bae2dSConor Dooley clk_data->dev = dev; 522b56bae2dSConor Dooley dev_set_drvdata(dev, clk_data); 523635e5e73SDaire McNamara 524445c2da8SConor Dooley ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 525445c2da8SConor Dooley clk_data); 526445c2da8SConor Dooley if (ret) 527445c2da8SConor Dooley return ret; 528445c2da8SConor Dooley 529635e5e73SDaire McNamara ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 530635e5e73SDaire McNamara if (ret) 531635e5e73SDaire McNamara return ret; 532635e5e73SDaire McNamara 533635e5e73SDaire McNamara ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 534635e5e73SDaire McNamara clk_data); 535635e5e73SDaire McNamara if (ret) 536635e5e73SDaire McNamara return ret; 537635e5e73SDaire McNamara 538635e5e73SDaire McNamara ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 539635e5e73SDaire McNamara if (ret) 540635e5e73SDaire McNamara return ret; 541635e5e73SDaire McNamara 542b56bae2dSConor Dooley return mpfs_reset_controller_register(clk_data); 543635e5e73SDaire McNamara } 544635e5e73SDaire McNamara 545635e5e73SDaire McNamara static const struct of_device_id mpfs_clk_of_match_table[] = { 546635e5e73SDaire McNamara { .compatible = "microchip,mpfs-clkcfg", }, 547635e5e73SDaire McNamara {} 548635e5e73SDaire McNamara }; 549b56bae2dSConor Dooley MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); 550635e5e73SDaire McNamara 551635e5e73SDaire McNamara static struct platform_driver mpfs_clk_driver = { 552635e5e73SDaire McNamara .probe = mpfs_clk_probe, 553635e5e73SDaire McNamara .driver = { 554635e5e73SDaire McNamara .name = "microchip-mpfs-clkcfg", 555635e5e73SDaire McNamara .of_match_table = mpfs_clk_of_match_table, 556635e5e73SDaire McNamara }, 557635e5e73SDaire McNamara }; 558635e5e73SDaire McNamara 559635e5e73SDaire McNamara static int __init clk_mpfs_init(void) 560635e5e73SDaire McNamara { 561635e5e73SDaire McNamara return platform_driver_register(&mpfs_clk_driver); 562635e5e73SDaire McNamara } 563635e5e73SDaire McNamara core_initcall(clk_mpfs_init); 564635e5e73SDaire McNamara 565635e5e73SDaire McNamara static void __exit clk_mpfs_exit(void) 566635e5e73SDaire McNamara { 567635e5e73SDaire McNamara platform_driver_unregister(&mpfs_clk_driver); 568635e5e73SDaire McNamara } 569635e5e73SDaire McNamara module_exit(clk_mpfs_exit); 570635e5e73SDaire McNamara 571635e5e73SDaire McNamara MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 572635e5e73SDaire McNamara MODULE_LICENSE("GPL v2"); 573