1635e5e73SDaire McNamara // SPDX-License-Identifier: GPL-2.0-only 2635e5e73SDaire McNamara /* 3635e5e73SDaire McNamara * Daire McNamara,<daire.mcnamara@microchip.com> 4635e5e73SDaire McNamara * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5635e5e73SDaire McNamara */ 6635e5e73SDaire McNamara #include <linux/clk-provider.h> 7635e5e73SDaire McNamara #include <linux/io.h> 8635e5e73SDaire McNamara #include <linux/module.h> 9635e5e73SDaire McNamara #include <linux/platform_device.h> 10635e5e73SDaire McNamara #include <linux/slab.h> 11635e5e73SDaire McNamara #include <dt-bindings/clock/microchip,mpfs-clock.h> 12635e5e73SDaire McNamara 13635e5e73SDaire McNamara /* address offset of control registers */ 14*445c2da8SConor Dooley #define REG_MSSPLL_REF_CR 0x08u 15*445c2da8SConor Dooley #define REG_MSSPLL_POSTDIV_CR 0x10u 16*445c2da8SConor Dooley #define REG_MSSPLL_SSCG_2_CR 0x2Cu 17635e5e73SDaire McNamara #define REG_CLOCK_CONFIG_CR 0x08u 18635e5e73SDaire McNamara #define REG_SUBBLK_CLOCK_CR 0x84u 19635e5e73SDaire McNamara #define REG_SUBBLK_RESET_CR 0x88u 20635e5e73SDaire McNamara 21*445c2da8SConor Dooley #define MSSPLL_FBDIV_SHIFT 0x00u 22*445c2da8SConor Dooley #define MSSPLL_FBDIV_WIDTH 0x0Cu 23*445c2da8SConor Dooley #define MSSPLL_REFDIV_SHIFT 0x08u 24*445c2da8SConor Dooley #define MSSPLL_REFDIV_WIDTH 0x06u 25*445c2da8SConor Dooley #define MSSPLL_POSTDIV_SHIFT 0x08u 26*445c2da8SConor Dooley #define MSSPLL_POSTDIV_WIDTH 0x07u 27*445c2da8SConor Dooley #define MSSPLL_FIXED_DIV 4u 28*445c2da8SConor Dooley 29635e5e73SDaire McNamara struct mpfs_clock_data { 30635e5e73SDaire McNamara void __iomem *base; 31*445c2da8SConor Dooley void __iomem *msspll_base; 32635e5e73SDaire McNamara struct clk_hw_onecell_data hw_data; 33635e5e73SDaire McNamara }; 34635e5e73SDaire McNamara 35*445c2da8SConor Dooley struct mpfs_msspll_hw_clock { 36*445c2da8SConor Dooley void __iomem *base; 37*445c2da8SConor Dooley unsigned int id; 38*445c2da8SConor Dooley u32 reg_offset; 39*445c2da8SConor Dooley u32 shift; 40*445c2da8SConor Dooley u32 width; 41*445c2da8SConor Dooley u32 flags; 42*445c2da8SConor Dooley struct clk_hw hw; 43*445c2da8SConor Dooley struct clk_init_data init; 44*445c2da8SConor Dooley }; 45*445c2da8SConor Dooley 46*445c2da8SConor Dooley #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 47*445c2da8SConor Dooley 48635e5e73SDaire McNamara struct mpfs_cfg_clock { 49635e5e73SDaire McNamara const struct clk_div_table *table; 50635e5e73SDaire McNamara unsigned int id; 51*445c2da8SConor Dooley u32 reg_offset; 52635e5e73SDaire McNamara u8 shift; 53635e5e73SDaire McNamara u8 width; 54*445c2da8SConor Dooley u8 flags; 55635e5e73SDaire McNamara }; 56635e5e73SDaire McNamara 57635e5e73SDaire McNamara struct mpfs_cfg_hw_clock { 58635e5e73SDaire McNamara struct mpfs_cfg_clock cfg; 59635e5e73SDaire McNamara void __iomem *sys_base; 60635e5e73SDaire McNamara struct clk_hw hw; 61635e5e73SDaire McNamara struct clk_init_data init; 62635e5e73SDaire McNamara }; 63635e5e73SDaire McNamara 64635e5e73SDaire McNamara #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) 65635e5e73SDaire McNamara 66635e5e73SDaire McNamara struct mpfs_periph_clock { 67635e5e73SDaire McNamara unsigned int id; 68635e5e73SDaire McNamara u8 shift; 69635e5e73SDaire McNamara }; 70635e5e73SDaire McNamara 71635e5e73SDaire McNamara struct mpfs_periph_hw_clock { 72635e5e73SDaire McNamara struct mpfs_periph_clock periph; 73635e5e73SDaire McNamara void __iomem *sys_base; 74635e5e73SDaire McNamara struct clk_hw hw; 75635e5e73SDaire McNamara }; 76635e5e73SDaire McNamara 77635e5e73SDaire McNamara #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 78635e5e73SDaire McNamara 79635e5e73SDaire McNamara /* 80635e5e73SDaire McNamara * mpfs_clk_lock prevents anything else from writing to the 81635e5e73SDaire McNamara * mpfs clk block while a software locked register is being written. 82635e5e73SDaire McNamara */ 83635e5e73SDaire McNamara static DEFINE_SPINLOCK(mpfs_clk_lock); 84635e5e73SDaire McNamara 85*445c2da8SConor Dooley static const struct clk_parent_data mpfs_ext_ref[] = { 86635e5e73SDaire McNamara { .index = 0 }, 87635e5e73SDaire McNamara }; 88635e5e73SDaire McNamara 89635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 90635e5e73SDaire McNamara { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 91635e5e73SDaire McNamara { 0, 0 } 92635e5e73SDaire McNamara }; 93635e5e73SDaire McNamara 94635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_ahb_table[] = { 95635e5e73SDaire McNamara { 1, 2 }, { 2, 4}, { 3, 8 }, 96635e5e73SDaire McNamara { 0, 0 } 97635e5e73SDaire McNamara }; 98635e5e73SDaire McNamara 99*445c2da8SConor Dooley static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 100*445c2da8SConor Dooley { 101*445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 102*445c2da8SConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 103*445c2da8SConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 104*445c2da8SConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 105*445c2da8SConor Dooley u32 mult, ref_div, postdiv; 106*445c2da8SConor Dooley 107*445c2da8SConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 108*445c2da8SConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 109*445c2da8SConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 110*445c2da8SConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 111*445c2da8SConor Dooley postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 112*445c2da8SConor Dooley postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 113*445c2da8SConor Dooley 114*445c2da8SConor Dooley return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 115*445c2da8SConor Dooley } 116*445c2da8SConor Dooley 117*445c2da8SConor Dooley static const struct clk_ops mpfs_clk_msspll_ops = { 118*445c2da8SConor Dooley .recalc_rate = mpfs_clk_msspll_recalc_rate, 119*445c2da8SConor Dooley }; 120*445c2da8SConor Dooley 121*445c2da8SConor Dooley #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 122*445c2da8SConor Dooley .id = _id, \ 123*445c2da8SConor Dooley .shift = _shift, \ 124*445c2da8SConor Dooley .width = _width, \ 125*445c2da8SConor Dooley .reg_offset = _offset, \ 126*445c2da8SConor Dooley .flags = _flags, \ 127*445c2da8SConor Dooley .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 128*445c2da8SConor Dooley } 129*445c2da8SConor Dooley 130*445c2da8SConor Dooley static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 131*445c2da8SConor Dooley CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 132*445c2da8SConor Dooley MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 133*445c2da8SConor Dooley }; 134*445c2da8SConor Dooley 135*445c2da8SConor Dooley static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, 136*445c2da8SConor Dooley void __iomem *base) 137*445c2da8SConor Dooley { 138*445c2da8SConor Dooley msspll_hw->base = base; 139*445c2da8SConor Dooley 140*445c2da8SConor Dooley return devm_clk_hw_register(dev, &msspll_hw->hw); 141*445c2da8SConor Dooley } 142*445c2da8SConor Dooley 143*445c2da8SConor Dooley static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 144*445c2da8SConor Dooley unsigned int num_clks, struct mpfs_clock_data *data) 145*445c2da8SConor Dooley { 146*445c2da8SConor Dooley void __iomem *base = data->msspll_base; 147*445c2da8SConor Dooley unsigned int i; 148*445c2da8SConor Dooley int ret; 149*445c2da8SConor Dooley 150*445c2da8SConor Dooley for (i = 0; i < num_clks; i++) { 151*445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 152*445c2da8SConor Dooley 153*445c2da8SConor Dooley ret = mpfs_clk_register_msspll(dev, msspll_hw, base); 154*445c2da8SConor Dooley if (ret) 155*445c2da8SConor Dooley return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 156*445c2da8SConor Dooley CLK_MSSPLL); 157*445c2da8SConor Dooley 158*445c2da8SConor Dooley data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 159*445c2da8SConor Dooley } 160*445c2da8SConor Dooley 161*445c2da8SConor Dooley return 0; 162*445c2da8SConor Dooley } 163*445c2da8SConor Dooley 164*445c2da8SConor Dooley /* 165*445c2da8SConor Dooley * "CFG" clocks 166*445c2da8SConor Dooley */ 167*445c2da8SConor Dooley 168635e5e73SDaire McNamara static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) 169635e5e73SDaire McNamara { 170635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 171635e5e73SDaire McNamara struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 172635e5e73SDaire McNamara void __iomem *base_addr = cfg_hw->sys_base; 173635e5e73SDaire McNamara u32 val; 174635e5e73SDaire McNamara 175*445c2da8SConor Dooley val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; 176635e5e73SDaire McNamara val &= clk_div_mask(cfg->width); 177635e5e73SDaire McNamara 178*445c2da8SConor Dooley return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); 179635e5e73SDaire McNamara } 180635e5e73SDaire McNamara 181635e5e73SDaire McNamara static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 182635e5e73SDaire McNamara { 183635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 184635e5e73SDaire McNamara struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 185635e5e73SDaire McNamara 186635e5e73SDaire McNamara return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); 187635e5e73SDaire McNamara } 188635e5e73SDaire McNamara 189635e5e73SDaire McNamara static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 190635e5e73SDaire McNamara { 191635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 192635e5e73SDaire McNamara struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 193635e5e73SDaire McNamara void __iomem *base_addr = cfg_hw->sys_base; 194635e5e73SDaire McNamara unsigned long flags; 195635e5e73SDaire McNamara u32 val; 196635e5e73SDaire McNamara int divider_setting; 197635e5e73SDaire McNamara 198635e5e73SDaire McNamara divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); 199635e5e73SDaire McNamara 200635e5e73SDaire McNamara if (divider_setting < 0) 201635e5e73SDaire McNamara return divider_setting; 202635e5e73SDaire McNamara 203635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 204*445c2da8SConor Dooley val = readl_relaxed(base_addr + cfg->reg_offset); 205635e5e73SDaire McNamara val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); 206635e5e73SDaire McNamara val |= divider_setting << cfg->shift; 207*445c2da8SConor Dooley writel_relaxed(val, base_addr + cfg->reg_offset); 208635e5e73SDaire McNamara 209635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 210635e5e73SDaire McNamara 211635e5e73SDaire McNamara return 0; 212635e5e73SDaire McNamara } 213635e5e73SDaire McNamara 214635e5e73SDaire McNamara static const struct clk_ops mpfs_clk_cfg_ops = { 215635e5e73SDaire McNamara .recalc_rate = mpfs_cfg_clk_recalc_rate, 216635e5e73SDaire McNamara .round_rate = mpfs_cfg_clk_round_rate, 217635e5e73SDaire McNamara .set_rate = mpfs_cfg_clk_set_rate, 218635e5e73SDaire McNamara }; 219635e5e73SDaire McNamara 220*445c2da8SConor Dooley #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 221635e5e73SDaire McNamara .cfg.id = _id, \ 222635e5e73SDaire McNamara .cfg.shift = _shift, \ 223635e5e73SDaire McNamara .cfg.width = _width, \ 224635e5e73SDaire McNamara .cfg.table = _table, \ 225*445c2da8SConor Dooley .cfg.reg_offset = _offset, \ 226*445c2da8SConor Dooley .cfg.flags = _flags, \ 227*445c2da8SConor Dooley .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ 228635e5e73SDaire McNamara } 229635e5e73SDaire McNamara 230635e5e73SDaire McNamara static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 231*445c2da8SConor Dooley CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 232*445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 233*445c2da8SConor Dooley CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 234*445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 235*445c2da8SConor Dooley CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 236*445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 237635e5e73SDaire McNamara }; 238635e5e73SDaire McNamara 239635e5e73SDaire McNamara static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, 240635e5e73SDaire McNamara void __iomem *sys_base) 241635e5e73SDaire McNamara { 242635e5e73SDaire McNamara cfg_hw->sys_base = sys_base; 243635e5e73SDaire McNamara 244635e5e73SDaire McNamara return devm_clk_hw_register(dev, &cfg_hw->hw); 245635e5e73SDaire McNamara } 246635e5e73SDaire McNamara 247635e5e73SDaire McNamara static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 248635e5e73SDaire McNamara unsigned int num_clks, struct mpfs_clock_data *data) 249635e5e73SDaire McNamara { 250635e5e73SDaire McNamara void __iomem *sys_base = data->base; 251635e5e73SDaire McNamara unsigned int i, id; 252635e5e73SDaire McNamara int ret; 253635e5e73SDaire McNamara 254635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 255635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 256635e5e73SDaire McNamara 257635e5e73SDaire McNamara ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); 258635e5e73SDaire McNamara if (ret) 259635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 260635e5e73SDaire McNamara cfg_hw->cfg.id); 261635e5e73SDaire McNamara 262*445c2da8SConor Dooley id = cfg_hw->cfg.id; 263635e5e73SDaire McNamara data->hw_data.hws[id] = &cfg_hw->hw; 264635e5e73SDaire McNamara } 265635e5e73SDaire McNamara 266635e5e73SDaire McNamara return 0; 267635e5e73SDaire McNamara } 268635e5e73SDaire McNamara 269*445c2da8SConor Dooley /* 270*445c2da8SConor Dooley * peripheral clocks - devices connected to axi or ahb buses. 271*445c2da8SConor Dooley */ 272*445c2da8SConor Dooley 273635e5e73SDaire McNamara static int mpfs_periph_clk_enable(struct clk_hw *hw) 274635e5e73SDaire McNamara { 275635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 276635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 277635e5e73SDaire McNamara void __iomem *base_addr = periph_hw->sys_base; 278635e5e73SDaire McNamara u32 reg, val; 279635e5e73SDaire McNamara unsigned long flags; 280635e5e73SDaire McNamara 281635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 282635e5e73SDaire McNamara 283635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); 284635e5e73SDaire McNamara val = reg & ~(1u << periph->shift); 285635e5e73SDaire McNamara writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); 286635e5e73SDaire McNamara 287635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 288635e5e73SDaire McNamara val = reg | (1u << periph->shift); 289635e5e73SDaire McNamara writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 290635e5e73SDaire McNamara 291635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 292635e5e73SDaire McNamara 293635e5e73SDaire McNamara return 0; 294635e5e73SDaire McNamara } 295635e5e73SDaire McNamara 296635e5e73SDaire McNamara static void mpfs_periph_clk_disable(struct clk_hw *hw) 297635e5e73SDaire McNamara { 298635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 299635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 300635e5e73SDaire McNamara void __iomem *base_addr = periph_hw->sys_base; 301635e5e73SDaire McNamara u32 reg, val; 302635e5e73SDaire McNamara unsigned long flags; 303635e5e73SDaire McNamara 304635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 305635e5e73SDaire McNamara 306635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 307635e5e73SDaire McNamara val = reg & ~(1u << periph->shift); 308635e5e73SDaire McNamara writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 309635e5e73SDaire McNamara 310635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 311635e5e73SDaire McNamara } 312635e5e73SDaire McNamara 313635e5e73SDaire McNamara static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 314635e5e73SDaire McNamara { 315635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 316635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 317635e5e73SDaire McNamara void __iomem *base_addr = periph_hw->sys_base; 318635e5e73SDaire McNamara u32 reg; 319635e5e73SDaire McNamara 320635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); 321635e5e73SDaire McNamara if ((reg & (1u << periph->shift)) == 0u) { 322635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 323635e5e73SDaire McNamara if (reg & (1u << periph->shift)) 324635e5e73SDaire McNamara return 1; 325635e5e73SDaire McNamara } 326635e5e73SDaire McNamara 327635e5e73SDaire McNamara return 0; 328635e5e73SDaire McNamara } 329635e5e73SDaire McNamara 330635e5e73SDaire McNamara static const struct clk_ops mpfs_periph_clk_ops = { 331635e5e73SDaire McNamara .enable = mpfs_periph_clk_enable, 332635e5e73SDaire McNamara .disable = mpfs_periph_clk_disable, 333635e5e73SDaire McNamara .is_enabled = mpfs_periph_clk_is_enabled, 334635e5e73SDaire McNamara }; 335635e5e73SDaire McNamara 336635e5e73SDaire McNamara #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 337635e5e73SDaire McNamara .periph.id = _id, \ 338635e5e73SDaire McNamara .periph.shift = _shift, \ 339635e5e73SDaire McNamara .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 340635e5e73SDaire McNamara _flags), \ 341635e5e73SDaire McNamara } 342635e5e73SDaire McNamara 343635e5e73SDaire McNamara #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].hw) 344635e5e73SDaire McNamara 345635e5e73SDaire McNamara /* 346635e5e73SDaire McNamara * Critical clocks: 347635e5e73SDaire McNamara * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 348635e5e73SDaire McNamara * trap handler 349635e5e73SDaire McNamara * - CLK_MMUART0: reserved by the hss 350635e5e73SDaire McNamara * - CLK_DDRC: provides clock to the ddr subsystem 351a2438f82SConor Dooley * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 352a2438f82SConor Dooley * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 353a2438f82SConor Dooley * causes the FPGA fabric to go into reset. 354a2438f82SConor Dooley * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 355635e5e73SDaire McNamara */ 356635e5e73SDaire McNamara 357635e5e73SDaire McNamara static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 358635e5e73SDaire McNamara CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 359635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 360635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 361635e5e73SDaire McNamara CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 362635e5e73SDaire McNamara CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(AHB), 4, 0), 363635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 364635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 365635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 366635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 367635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 368635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 369635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 370635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 371635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 372635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 373635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 374635e5e73SDaire McNamara CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 375635e5e73SDaire McNamara CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, 0), 376635e5e73SDaire McNamara CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 377635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 378635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 379635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 380635e5e73SDaire McNamara CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 3818f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 3828f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 3838f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 3848f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 385a2438f82SConor Dooley CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 386635e5e73SDaire McNamara CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 387635e5e73SDaire McNamara }; 388635e5e73SDaire McNamara 389635e5e73SDaire McNamara static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, 390635e5e73SDaire McNamara void __iomem *sys_base) 391635e5e73SDaire McNamara { 392635e5e73SDaire McNamara periph_hw->sys_base = sys_base; 393635e5e73SDaire McNamara 394635e5e73SDaire McNamara return devm_clk_hw_register(dev, &periph_hw->hw); 395635e5e73SDaire McNamara } 396635e5e73SDaire McNamara 397635e5e73SDaire McNamara static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 398635e5e73SDaire McNamara int num_clks, struct mpfs_clock_data *data) 399635e5e73SDaire McNamara { 400635e5e73SDaire McNamara void __iomem *sys_base = data->base; 401635e5e73SDaire McNamara unsigned int i, id; 402635e5e73SDaire McNamara int ret; 403635e5e73SDaire McNamara 404635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 405635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 406635e5e73SDaire McNamara 407635e5e73SDaire McNamara ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); 408635e5e73SDaire McNamara if (ret) 409635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 410635e5e73SDaire McNamara periph_hw->periph.id); 411635e5e73SDaire McNamara 412635e5e73SDaire McNamara id = periph_hws[i].periph.id; 413635e5e73SDaire McNamara data->hw_data.hws[id] = &periph_hw->hw; 414635e5e73SDaire McNamara } 415635e5e73SDaire McNamara 416635e5e73SDaire McNamara return 0; 417635e5e73SDaire McNamara } 418635e5e73SDaire McNamara 419635e5e73SDaire McNamara static int mpfs_clk_probe(struct platform_device *pdev) 420635e5e73SDaire McNamara { 421635e5e73SDaire McNamara struct device *dev = &pdev->dev; 422635e5e73SDaire McNamara struct mpfs_clock_data *clk_data; 423635e5e73SDaire McNamara unsigned int num_clks; 424635e5e73SDaire McNamara int ret; 425635e5e73SDaire McNamara 426*445c2da8SConor Dooley /* CLK_RESERVED is not part of clock arrays, so add 1 */ 427*445c2da8SConor Dooley num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 428*445c2da8SConor Dooley + ARRAY_SIZE(mpfs_periph_clks) + 1; 429635e5e73SDaire McNamara 430635e5e73SDaire McNamara clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 431635e5e73SDaire McNamara if (!clk_data) 432635e5e73SDaire McNamara return -ENOMEM; 433635e5e73SDaire McNamara 434635e5e73SDaire McNamara clk_data->base = devm_platform_ioremap_resource(pdev, 0); 435635e5e73SDaire McNamara if (IS_ERR(clk_data->base)) 436635e5e73SDaire McNamara return PTR_ERR(clk_data->base); 437635e5e73SDaire McNamara 438*445c2da8SConor Dooley clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 439*445c2da8SConor Dooley if (IS_ERR(clk_data->msspll_base)) 440*445c2da8SConor Dooley return PTR_ERR(clk_data->msspll_base); 441*445c2da8SConor Dooley 442635e5e73SDaire McNamara clk_data->hw_data.num = num_clks; 443635e5e73SDaire McNamara 444*445c2da8SConor Dooley ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 445*445c2da8SConor Dooley clk_data); 446*445c2da8SConor Dooley if (ret) 447*445c2da8SConor Dooley return ret; 448*445c2da8SConor Dooley 449635e5e73SDaire McNamara ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 450635e5e73SDaire McNamara if (ret) 451635e5e73SDaire McNamara return ret; 452635e5e73SDaire McNamara 453635e5e73SDaire McNamara ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 454635e5e73SDaire McNamara clk_data); 455635e5e73SDaire McNamara if (ret) 456635e5e73SDaire McNamara return ret; 457635e5e73SDaire McNamara 458635e5e73SDaire McNamara ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 459635e5e73SDaire McNamara if (ret) 460635e5e73SDaire McNamara return ret; 461635e5e73SDaire McNamara 462635e5e73SDaire McNamara return ret; 463635e5e73SDaire McNamara } 464635e5e73SDaire McNamara 465635e5e73SDaire McNamara static const struct of_device_id mpfs_clk_of_match_table[] = { 466635e5e73SDaire McNamara { .compatible = "microchip,mpfs-clkcfg", }, 467635e5e73SDaire McNamara {} 468635e5e73SDaire McNamara }; 469635e5e73SDaire McNamara MODULE_DEVICE_TABLE(of, mpfs_clk_match_table); 470635e5e73SDaire McNamara 471635e5e73SDaire McNamara static struct platform_driver mpfs_clk_driver = { 472635e5e73SDaire McNamara .probe = mpfs_clk_probe, 473635e5e73SDaire McNamara .driver = { 474635e5e73SDaire McNamara .name = "microchip-mpfs-clkcfg", 475635e5e73SDaire McNamara .of_match_table = mpfs_clk_of_match_table, 476635e5e73SDaire McNamara }, 477635e5e73SDaire McNamara }; 478635e5e73SDaire McNamara 479635e5e73SDaire McNamara static int __init clk_mpfs_init(void) 480635e5e73SDaire McNamara { 481635e5e73SDaire McNamara return platform_driver_register(&mpfs_clk_driver); 482635e5e73SDaire McNamara } 483635e5e73SDaire McNamara core_initcall(clk_mpfs_init); 484635e5e73SDaire McNamara 485635e5e73SDaire McNamara static void __exit clk_mpfs_exit(void) 486635e5e73SDaire McNamara { 487635e5e73SDaire McNamara platform_driver_unregister(&mpfs_clk_driver); 488635e5e73SDaire McNamara } 489635e5e73SDaire McNamara module_exit(clk_mpfs_exit); 490635e5e73SDaire McNamara 491635e5e73SDaire McNamara MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 492635e5e73SDaire McNamara MODULE_LICENSE("GPL v2"); 493