172dbb8c9SNeil Armstrong // SPDX-License-Identifier: GPL-2.0 272dbb8c9SNeil Armstrong /* 372dbb8c9SNeil Armstrong * Copyright (c) 2018 BayLibre, SAS. 472dbb8c9SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 572dbb8c9SNeil Armstrong */ 672dbb8c9SNeil Armstrong 772dbb8c9SNeil Armstrong #include <linux/clk-provider.h> 872dbb8c9SNeil Armstrong #include "clkc.h" 972dbb8c9SNeil Armstrong 1072dbb8c9SNeil Armstrong static inline struct meson_vid_pll_div_data * 1172dbb8c9SNeil Armstrong meson_vid_pll_div_data(struct clk_regmap *clk) 1272dbb8c9SNeil Armstrong { 1372dbb8c9SNeil Armstrong return (struct meson_vid_pll_div_data *)clk->data; 1472dbb8c9SNeil Armstrong } 1572dbb8c9SNeil Armstrong 1672dbb8c9SNeil Armstrong /* 1772dbb8c9SNeil Armstrong * This vid_pll divided is a fully programmable fractionnal divider to 1872dbb8c9SNeil Armstrong * achieve complex video clock rates. 1972dbb8c9SNeil Armstrong * 2072dbb8c9SNeil Armstrong * Here are provided the commonly used fraction values provided by Amlogic. 2172dbb8c9SNeil Armstrong */ 2272dbb8c9SNeil Armstrong 2372dbb8c9SNeil Armstrong struct vid_pll_div { 2472dbb8c9SNeil Armstrong unsigned int shift_val; 2572dbb8c9SNeil Armstrong unsigned int shift_sel; 2672dbb8c9SNeil Armstrong unsigned int divider; 2772dbb8c9SNeil Armstrong unsigned int multiplier; 2872dbb8c9SNeil Armstrong }; 2972dbb8c9SNeil Armstrong 3072dbb8c9SNeil Armstrong #define VID_PLL_DIV(_val, _sel, _ft, _fb) \ 3172dbb8c9SNeil Armstrong { \ 3272dbb8c9SNeil Armstrong .shift_val = (_val), \ 3372dbb8c9SNeil Armstrong .shift_sel = (_sel), \ 3472dbb8c9SNeil Armstrong .divider = (_ft), \ 3572dbb8c9SNeil Armstrong .multiplier = (_fb), \ 3672dbb8c9SNeil Armstrong } 3772dbb8c9SNeil Armstrong 3872dbb8c9SNeil Armstrong static const struct vid_pll_div vid_pll_div_table[] = { 3972dbb8c9SNeil Armstrong VID_PLL_DIV(0x0aaa, 0, 2, 1), /* 2/1 => /2 */ 4072dbb8c9SNeil Armstrong VID_PLL_DIV(0x5294, 2, 5, 2), /* 5/2 => /2.5 */ 4172dbb8c9SNeil Armstrong VID_PLL_DIV(0x0db6, 0, 3, 1), /* 3/1 => /3 */ 4272dbb8c9SNeil Armstrong VID_PLL_DIV(0x36cc, 1, 7, 2), /* 7/2 => /3.5 */ 4372dbb8c9SNeil Armstrong VID_PLL_DIV(0x6666, 2, 15, 4), /* 15/4 => /3.75 */ 4472dbb8c9SNeil Armstrong VID_PLL_DIV(0x0ccc, 0, 4, 1), /* 4/1 => /4 */ 4572dbb8c9SNeil Armstrong VID_PLL_DIV(0x739c, 2, 5, 1), /* 5/1 => /5 */ 4672dbb8c9SNeil Armstrong VID_PLL_DIV(0x0e38, 0, 6, 1), /* 6/1 => /6 */ 4772dbb8c9SNeil Armstrong VID_PLL_DIV(0x0000, 3, 25, 4), /* 25/4 => /6.25 */ 4872dbb8c9SNeil Armstrong VID_PLL_DIV(0x3c78, 1, 7, 1), /* 7/1 => /7 */ 4972dbb8c9SNeil Armstrong VID_PLL_DIV(0x78f0, 2, 15, 2), /* 15/2 => /7.5 */ 5072dbb8c9SNeil Armstrong VID_PLL_DIV(0x0fc0, 0, 12, 1), /* 12/1 => /12 */ 5172dbb8c9SNeil Armstrong VID_PLL_DIV(0x3f80, 1, 14, 1), /* 14/1 => /14 */ 5272dbb8c9SNeil Armstrong VID_PLL_DIV(0x7f80, 2, 15, 1), /* 15/1 => /15 */ 5372dbb8c9SNeil Armstrong }; 5472dbb8c9SNeil Armstrong 5572dbb8c9SNeil Armstrong #define to_meson_vid_pll_div(_hw) \ 5672dbb8c9SNeil Armstrong container_of(_hw, struct meson_vid_pll_div, hw) 5772dbb8c9SNeil Armstrong 588913e8a7SStephen Boyd static const struct vid_pll_div *_get_table_val(unsigned int shift_val, 5972dbb8c9SNeil Armstrong unsigned int shift_sel) 6072dbb8c9SNeil Armstrong { 6172dbb8c9SNeil Armstrong int i; 6272dbb8c9SNeil Armstrong 6372dbb8c9SNeil Armstrong for (i = 0 ; i < ARRAY_SIZE(vid_pll_div_table) ; ++i) { 6472dbb8c9SNeil Armstrong if (vid_pll_div_table[i].shift_val == shift_val && 6572dbb8c9SNeil Armstrong vid_pll_div_table[i].shift_sel == shift_sel) 6672dbb8c9SNeil Armstrong return &vid_pll_div_table[i]; 6772dbb8c9SNeil Armstrong } 6872dbb8c9SNeil Armstrong 6972dbb8c9SNeil Armstrong return NULL; 7072dbb8c9SNeil Armstrong } 7172dbb8c9SNeil Armstrong 7272dbb8c9SNeil Armstrong static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw, 7372dbb8c9SNeil Armstrong unsigned long parent_rate) 7472dbb8c9SNeil Armstrong { 7572dbb8c9SNeil Armstrong struct clk_regmap *clk = to_clk_regmap(hw); 7672dbb8c9SNeil Armstrong struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk); 7772dbb8c9SNeil Armstrong const struct vid_pll_div *div; 7872dbb8c9SNeil Armstrong 7972dbb8c9SNeil Armstrong div = _get_table_val(meson_parm_read(clk->map, &pll_div->val), 8072dbb8c9SNeil Armstrong meson_parm_read(clk->map, &pll_div->sel)); 8172dbb8c9SNeil Armstrong if (!div || !div->divider) { 8272dbb8c9SNeil Armstrong pr_info("%s: Invalid config value for vid_pll_div\n", __func__); 8372dbb8c9SNeil Armstrong return parent_rate; 8472dbb8c9SNeil Armstrong } 8572dbb8c9SNeil Armstrong 8672dbb8c9SNeil Armstrong return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider); 8772dbb8c9SNeil Armstrong } 8872dbb8c9SNeil Armstrong 8972dbb8c9SNeil Armstrong const struct clk_ops meson_vid_pll_div_ro_ops = { 9072dbb8c9SNeil Armstrong .recalc_rate = meson_vid_pll_div_recalc_rate, 9172dbb8c9SNeil Armstrong }; 92