172dbb8c9SNeil Armstrong // SPDX-License-Identifier: GPL-2.0
272dbb8c9SNeil Armstrong /*
372dbb8c9SNeil Armstrong * Copyright (c) 2018 BayLibre, SAS.
472dbb8c9SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com>
572dbb8c9SNeil Armstrong */
672dbb8c9SNeil Armstrong
772dbb8c9SNeil Armstrong #include <linux/clk-provider.h>
8889c2b7eSJerome Brunet #include <linux/module.h>
9889c2b7eSJerome Brunet
10889c2b7eSJerome Brunet #include "clk-regmap.h"
11889c2b7eSJerome Brunet #include "vid-pll-div.h"
1272dbb8c9SNeil Armstrong
1372dbb8c9SNeil Armstrong static inline struct meson_vid_pll_div_data *
meson_vid_pll_div_data(struct clk_regmap * clk)1472dbb8c9SNeil Armstrong meson_vid_pll_div_data(struct clk_regmap *clk)
1572dbb8c9SNeil Armstrong {
1672dbb8c9SNeil Armstrong return (struct meson_vid_pll_div_data *)clk->data;
1772dbb8c9SNeil Armstrong }
1872dbb8c9SNeil Armstrong
1972dbb8c9SNeil Armstrong /*
2072dbb8c9SNeil Armstrong * This vid_pll divided is a fully programmable fractionnal divider to
2172dbb8c9SNeil Armstrong * achieve complex video clock rates.
2272dbb8c9SNeil Armstrong *
2372dbb8c9SNeil Armstrong * Here are provided the commonly used fraction values provided by Amlogic.
2472dbb8c9SNeil Armstrong */
2572dbb8c9SNeil Armstrong
2672dbb8c9SNeil Armstrong struct vid_pll_div {
2772dbb8c9SNeil Armstrong unsigned int shift_val;
2872dbb8c9SNeil Armstrong unsigned int shift_sel;
2972dbb8c9SNeil Armstrong unsigned int divider;
3072dbb8c9SNeil Armstrong unsigned int multiplier;
3172dbb8c9SNeil Armstrong };
3272dbb8c9SNeil Armstrong
3372dbb8c9SNeil Armstrong #define VID_PLL_DIV(_val, _sel, _ft, _fb) \
3472dbb8c9SNeil Armstrong { \
3572dbb8c9SNeil Armstrong .shift_val = (_val), \
3672dbb8c9SNeil Armstrong .shift_sel = (_sel), \
3772dbb8c9SNeil Armstrong .divider = (_ft), \
3872dbb8c9SNeil Armstrong .multiplier = (_fb), \
3972dbb8c9SNeil Armstrong }
4072dbb8c9SNeil Armstrong
4172dbb8c9SNeil Armstrong static const struct vid_pll_div vid_pll_div_table[] = {
4272dbb8c9SNeil Armstrong VID_PLL_DIV(0x0aaa, 0, 2, 1), /* 2/1 => /2 */
4372dbb8c9SNeil Armstrong VID_PLL_DIV(0x5294, 2, 5, 2), /* 5/2 => /2.5 */
4472dbb8c9SNeil Armstrong VID_PLL_DIV(0x0db6, 0, 3, 1), /* 3/1 => /3 */
4572dbb8c9SNeil Armstrong VID_PLL_DIV(0x36cc, 1, 7, 2), /* 7/2 => /3.5 */
4672dbb8c9SNeil Armstrong VID_PLL_DIV(0x6666, 2, 15, 4), /* 15/4 => /3.75 */
4772dbb8c9SNeil Armstrong VID_PLL_DIV(0x0ccc, 0, 4, 1), /* 4/1 => /4 */
4872dbb8c9SNeil Armstrong VID_PLL_DIV(0x739c, 2, 5, 1), /* 5/1 => /5 */
4972dbb8c9SNeil Armstrong VID_PLL_DIV(0x0e38, 0, 6, 1), /* 6/1 => /6 */
5072dbb8c9SNeil Armstrong VID_PLL_DIV(0x0000, 3, 25, 4), /* 25/4 => /6.25 */
5172dbb8c9SNeil Armstrong VID_PLL_DIV(0x3c78, 1, 7, 1), /* 7/1 => /7 */
5272dbb8c9SNeil Armstrong VID_PLL_DIV(0x78f0, 2, 15, 2), /* 15/2 => /7.5 */
5372dbb8c9SNeil Armstrong VID_PLL_DIV(0x0fc0, 0, 12, 1), /* 12/1 => /12 */
5472dbb8c9SNeil Armstrong VID_PLL_DIV(0x3f80, 1, 14, 1), /* 14/1 => /14 */
5572dbb8c9SNeil Armstrong VID_PLL_DIV(0x7f80, 2, 15, 1), /* 15/1 => /15 */
5672dbb8c9SNeil Armstrong };
5772dbb8c9SNeil Armstrong
5872dbb8c9SNeil Armstrong #define to_meson_vid_pll_div(_hw) \
5972dbb8c9SNeil Armstrong container_of(_hw, struct meson_vid_pll_div, hw)
6072dbb8c9SNeil Armstrong
_get_table_val(unsigned int shift_val,unsigned int shift_sel)618913e8a7SStephen Boyd static const struct vid_pll_div *_get_table_val(unsigned int shift_val,
6272dbb8c9SNeil Armstrong unsigned int shift_sel)
6372dbb8c9SNeil Armstrong {
6472dbb8c9SNeil Armstrong int i;
6572dbb8c9SNeil Armstrong
6672dbb8c9SNeil Armstrong for (i = 0 ; i < ARRAY_SIZE(vid_pll_div_table) ; ++i) {
6772dbb8c9SNeil Armstrong if (vid_pll_div_table[i].shift_val == shift_val &&
6872dbb8c9SNeil Armstrong vid_pll_div_table[i].shift_sel == shift_sel)
6972dbb8c9SNeil Armstrong return &vid_pll_div_table[i];
7072dbb8c9SNeil Armstrong }
7172dbb8c9SNeil Armstrong
7272dbb8c9SNeil Armstrong return NULL;
7372dbb8c9SNeil Armstrong }
7472dbb8c9SNeil Armstrong
meson_vid_pll_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)7572dbb8c9SNeil Armstrong static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw,
7672dbb8c9SNeil Armstrong unsigned long parent_rate)
7772dbb8c9SNeil Armstrong {
7872dbb8c9SNeil Armstrong struct clk_regmap *clk = to_clk_regmap(hw);
7972dbb8c9SNeil Armstrong struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk);
8072dbb8c9SNeil Armstrong const struct vid_pll_div *div;
8172dbb8c9SNeil Armstrong
8272dbb8c9SNeil Armstrong div = _get_table_val(meson_parm_read(clk->map, &pll_div->val),
8372dbb8c9SNeil Armstrong meson_parm_read(clk->map, &pll_div->sel));
8472dbb8c9SNeil Armstrong if (!div || !div->divider) {
856620f45fSNeil Armstrong pr_debug("%s: Invalid config value for vid_pll_div\n", __func__);
866620f45fSNeil Armstrong return 0;
8772dbb8c9SNeil Armstrong }
8872dbb8c9SNeil Armstrong
8972dbb8c9SNeil Armstrong return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);
9072dbb8c9SNeil Armstrong }
9172dbb8c9SNeil Armstrong
9272dbb8c9SNeil Armstrong const struct clk_ops meson_vid_pll_div_ro_ops = {
9372dbb8c9SNeil Armstrong .recalc_rate = meson_vid_pll_div_recalc_rate,
9472dbb8c9SNeil Armstrong };
95889c2b7eSJerome Brunet EXPORT_SYMBOL_GPL(meson_vid_pll_div_ro_ops);
96889c2b7eSJerome Brunet
97889c2b7eSJerome Brunet MODULE_DESCRIPTION("Amlogic video pll divider driver");
98889c2b7eSJerome Brunet MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
99889c2b7eSJerome Brunet MODULE_LICENSE("GPL v2");
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