1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 * 6 * Copyright (c) 2016 BayLibre, Inc. 7 * Michael Turquette <mturquette@baylibre.com> 8 */ 9 10 #ifndef __MESON8B_H 11 #define __MESON8B_H 12 13 /* 14 * Clock controller register offsets 15 * 16 * Register offsets from the HardKernel[0] data sheet are listed in comment 17 * blocks below. Those offsets must be multiplied by 4 before adding them to 18 * the base address to get the right value 19 * 20 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 21 */ 22 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 23 #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 24 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 25 #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 26 #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 27 #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 28 #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 29 #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 30 #define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ 31 #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 32 #define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */ 33 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 34 #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 35 #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 36 37 /* 38 * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 39 * confirm these are the same for the S805. 40 */ 41 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 42 #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 43 #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 44 #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 45 #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 46 #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 47 #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ 48 #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ 49 #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ 50 #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ 51 52 /* 53 * CLKID index values 54 * 55 * These indices are entirely contrived and do not map onto the hardware. 56 * It has now been decided to expose everything by default in the DT header: 57 * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want 58 * to expose, such as the internal muxes and dividers of composite clocks, 59 * will remain defined here. 60 */ 61 62 #define CLKID_MPLL0_DIV 96 63 #define CLKID_MPLL1_DIV 97 64 #define CLKID_MPLL2_DIV 98 65 #define CLKID_CPU_IN_SEL 99 66 #define CLKID_CPU_IN_DIV2 100 67 #define CLKID_CPU_IN_DIV3 101 68 #define CLKID_CPU_SCALE_DIV 102 69 #define CLKID_CPU_SCALE_OUT_SEL 103 70 #define CLKID_MPLL_PREDIV 104 71 #define CLKID_FCLK_DIV2_DIV 105 72 #define CLKID_FCLK_DIV3_DIV 106 73 #define CLKID_FCLK_DIV4_DIV 107 74 #define CLKID_FCLK_DIV5_DIV 108 75 #define CLKID_FCLK_DIV7_DIV 109 76 #define CLKID_NAND_SEL 110 77 #define CLKID_NAND_DIV 111 78 #define CLKID_PLL_FIXED_DCO 113 79 #define CLKID_PLL_VID_DCO 114 80 #define CLKID_PLL_SYS_DCO 115 81 #define CLKID_CPU_CLK_DIV2 116 82 #define CLKID_CPU_CLK_DIV3 117 83 #define CLKID_CPU_CLK_DIV4 118 84 #define CLKID_CPU_CLK_DIV5 119 85 #define CLKID_CPU_CLK_DIV6 120 86 #define CLKID_CPU_CLK_DIV7 121 87 #define CLKID_CPU_CLK_DIV8 122 88 #define CLKID_ABP_SEL 123 89 #define CLKID_PERIPH_SEL 125 90 #define CLKID_AXI_SEL 127 91 #define CLKID_L2_DRAM_SEL 129 92 93 #define CLK_NR_CLKS 131 94 95 /* 96 * include the CLKID and RESETID that have 97 * been made part of the stable DT binding 98 */ 99 #include <dt-bindings/clock/meson8b-clkc.h> 100 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 101 102 #endif /* __MESON8B_H */ 103