1 /* 2 * Copyright (c) 2015 Endless Mobile, Inc. 3 * Author: Carlo Caione <carlo@endlessm.com> 4 * 5 * Copyright (c) 2016 BayLibre, Inc. 6 * Michael Turquette <mturquette@baylibre.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef __MESON8B_H 22 #define __MESON8B_H 23 24 /* 25 * Clock controller register offsets 26 * 27 * Register offsets from the HardKernel[0] data sheet are listed in comment 28 * blocks below. Those offsets must be multiplied by 4 before adding them to 29 * the base address to get the right value 30 * 31 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 32 */ 33 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 34 #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 35 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 36 #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 37 #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 38 #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 39 #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 40 #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 41 #define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ 42 #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 43 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 44 #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 45 #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 46 47 /* 48 * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 49 * confirm these are the same for the S805. 50 */ 51 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 52 #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 53 #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 54 #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 55 #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 56 #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 57 #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ 58 #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ 59 #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ 60 #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ 61 62 /* 63 * CLKID index values 64 * 65 * These indices are entirely contrived and do not map onto the hardware. 66 * It has now been decided to expose everything by default in the DT header: 67 * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want 68 * to expose, such as the internal muxes and dividers of composite clocks, 69 * will remain defined here. 70 */ 71 72 #define CLK_NR_CLKS 96 73 74 /* 75 * include the CLKID and RESETID that have 76 * been made part of the stable DT binding 77 */ 78 #include <dt-bindings/clock/meson8b-clkc.h> 79 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 80 81 #endif /* __MESON8B_H */ 82