1d0c175daSAlexander Müller /* 2d0c175daSAlexander Müller * Copyright (c) 2015 Endless Mobile, Inc. 3d0c175daSAlexander Müller * Author: Carlo Caione <carlo@endlessm.com> 4d0c175daSAlexander Müller * 5d0c175daSAlexander Müller * Copyright (c) 2016 BayLibre, Inc. 6d0c175daSAlexander Müller * Michael Turquette <mturquette@baylibre.com> 7d0c175daSAlexander Müller * 8d0c175daSAlexander Müller * This program is free software; you can redistribute it and/or modify it 9d0c175daSAlexander Müller * under the terms and conditions of the GNU General Public License, 10d0c175daSAlexander Müller * version 2, as published by the Free Software Foundation. 11d0c175daSAlexander Müller * 12d0c175daSAlexander Müller * This program is distributed in the hope it will be useful, but WITHOUT 13d0c175daSAlexander Müller * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14d0c175daSAlexander Müller * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15d0c175daSAlexander Müller * more details. 16d0c175daSAlexander Müller * 17d0c175daSAlexander Müller * You should have received a copy of the GNU General Public License along with 18d0c175daSAlexander Müller * this program. If not, see <http://www.gnu.org/licenses/>. 19d0c175daSAlexander Müller */ 20d0c175daSAlexander Müller 21d0c175daSAlexander Müller #ifndef __MESON8B_H 22d0c175daSAlexander Müller #define __MESON8B_H 23d0c175daSAlexander Müller 24d0c175daSAlexander Müller /* 25d0c175daSAlexander Müller * Clock controller register offsets 26d0c175daSAlexander Müller * 27d0c175daSAlexander Müller * Register offsets from the HardKernel[0] data sheet are listed in comment 28d0c175daSAlexander Müller * blocks below. Those offsets must be multiplied by 4 before adding them to 29d0c175daSAlexander Müller * the base address to get the right value 30d0c175daSAlexander Müller * 31d0c175daSAlexander Müller * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 32d0c175daSAlexander Müller */ 33e31a1900SAlexander Müller #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 34e31a1900SAlexander Müller #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 35e31a1900SAlexander Müller #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 36e31a1900SAlexander Müller #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 37e31a1900SAlexander Müller #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 38e0818a39SAlexander Müller #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 39e0818a39SAlexander Müller #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 40e0818a39SAlexander Müller #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 41e0818a39SAlexander Müller #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 42e0818a39SAlexander Müller #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 43d0c175daSAlexander Müller 440f32e64bSAlexander Müller /* 45b778f745SJerome Brunet * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 46b778f745SJerome Brunet * confirm these are the same for the S805. 47b778f745SJerome Brunet */ 48b778f745SJerome Brunet #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 49b778f745SJerome Brunet #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 50b778f745SJerome Brunet #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 51b778f745SJerome Brunet #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 52b778f745SJerome Brunet #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 53b778f745SJerome Brunet #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 54b778f745SJerome Brunet #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ 55b778f745SJerome Brunet #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ 56b778f745SJerome Brunet #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ 57b778f745SJerome Brunet #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ 58b778f745SJerome Brunet 59b778f745SJerome Brunet /* 600f32e64bSAlexander Müller * CLKID index values 610f32e64bSAlexander Müller * 620f32e64bSAlexander Müller * These indices are entirely contrived and do not map onto the hardware. 630f32e64bSAlexander Müller * Migrate them out of this header and into the DT header file when they need 640f32e64bSAlexander Müller * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h 650f32e64bSAlexander Müller */ 660f32e64bSAlexander Müller 670f32e64bSAlexander Müller /* CLKID_UNUSED */ 680f32e64bSAlexander Müller /* CLKID_XTAL */ 690f32e64bSAlexander Müller /* CLKID_PLL_FIXED */ 700f32e64bSAlexander Müller /* CLKID_PLL_VID */ 710f32e64bSAlexander Müller /* CLKID_PLL_SYS */ 720f32e64bSAlexander Müller /* CLKID_FCLK_DIV2 */ 730f32e64bSAlexander Müller /* CLKID_FCLK_DIV3 */ 740f32e64bSAlexander Müller /* CLKID_FCLK_DIV4 */ 750f32e64bSAlexander Müller /* CLKID_FCLK_DIV5 */ 760f32e64bSAlexander Müller /* CLKID_FCLK_DIV7 */ 770f32e64bSAlexander Müller /* CLKID_CLK81 */ 780f32e64bSAlexander Müller /* CLKID_MALI */ 790f32e64bSAlexander Müller /* CLKID_CPUCLK */ 800f32e64bSAlexander Müller /* CLKID_ZERO */ 810f32e64bSAlexander Müller /* CLKID_MPEG_SEL */ 820f32e64bSAlexander Müller /* CLKID_MPEG_DIV */ 830f32e64bSAlexander Müller #define CLKID_DDR 16 840f32e64bSAlexander Müller #define CLKID_DOS 17 850f32e64bSAlexander Müller #define CLKID_ISA 18 860f32e64bSAlexander Müller #define CLKID_PL301 19 870f32e64bSAlexander Müller #define CLKID_PERIPHS 20 880f32e64bSAlexander Müller #define CLKID_SPICC 21 890f32e64bSAlexander Müller #define CLKID_I2C 22 900f32e64bSAlexander Müller #define CLKID_SAR_ADC 23 910f32e64bSAlexander Müller #define CLKID_SMART_CARD 24 920f32e64bSAlexander Müller #define CLKID_RNG0 25 930f32e64bSAlexander Müller #define CLKID_UART0 26 940f32e64bSAlexander Müller #define CLKID_SDHC 27 950f32e64bSAlexander Müller #define CLKID_STREAM 28 960f32e64bSAlexander Müller #define CLKID_ASYNC_FIFO 29 970f32e64bSAlexander Müller #define CLKID_SDIO 30 980f32e64bSAlexander Müller #define CLKID_ABUF 31 990f32e64bSAlexander Müller #define CLKID_HIU_IFACE 32 1000f32e64bSAlexander Müller #define CLKID_ASSIST_MISC 33 1010f32e64bSAlexander Müller #define CLKID_SPI 34 1020f32e64bSAlexander Müller #define CLKID_I2S_SPDIF 35 1030f32e64bSAlexander Müller #define CLKID_ETH 36 1040f32e64bSAlexander Müller #define CLKID_DEMUX 37 1050f32e64bSAlexander Müller #define CLKID_AIU_GLUE 38 1060f32e64bSAlexander Müller #define CLKID_IEC958 39 1070f32e64bSAlexander Müller #define CLKID_I2S_OUT 40 1080f32e64bSAlexander Müller #define CLKID_AMCLK 41 1090f32e64bSAlexander Müller #define CLKID_AIFIFO2 42 1100f32e64bSAlexander Müller #define CLKID_MIXER 43 1110f32e64bSAlexander Müller #define CLKID_MIXER_IFACE 44 1120f32e64bSAlexander Müller #define CLKID_ADC 45 1130f32e64bSAlexander Müller #define CLKID_BLKMV 46 1140f32e64bSAlexander Müller #define CLKID_AIU 47 1150f32e64bSAlexander Müller #define CLKID_UART1 48 1160f32e64bSAlexander Müller #define CLKID_G2D 49 1170f32e64bSAlexander Müller #define CLKID_USB0 50 1180f32e64bSAlexander Müller #define CLKID_USB1 51 1190f32e64bSAlexander Müller #define CLKID_RESET 52 1200f32e64bSAlexander Müller #define CLKID_NAND 53 1210f32e64bSAlexander Müller #define CLKID_DOS_PARSER 54 1220f32e64bSAlexander Müller #define CLKID_USB 55 1230f32e64bSAlexander Müller #define CLKID_VDIN1 56 1240f32e64bSAlexander Müller #define CLKID_AHB_ARB0 57 1250f32e64bSAlexander Müller #define CLKID_EFUSE 58 1260f32e64bSAlexander Müller #define CLKID_BOOT_ROM 59 1270f32e64bSAlexander Müller #define CLKID_AHB_DATA_BUS 60 1280f32e64bSAlexander Müller #define CLKID_AHB_CTRL_BUS 61 1290f32e64bSAlexander Müller #define CLKID_HDMI_INTR_SYNC 62 1300f32e64bSAlexander Müller #define CLKID_HDMI_PCLK 63 1310f32e64bSAlexander Müller #define CLKID_USB1_DDR_BRIDGE 64 1320f32e64bSAlexander Müller #define CLKID_USB0_DDR_BRIDGE 65 1330f32e64bSAlexander Müller #define CLKID_MMC_PCLK 66 1340f32e64bSAlexander Müller #define CLKID_DVIN 67 1350f32e64bSAlexander Müller #define CLKID_UART2 68 1360f32e64bSAlexander Müller #define CLKID_SANA 69 1370f32e64bSAlexander Müller #define CLKID_VPU_INTR 70 1380f32e64bSAlexander Müller #define CLKID_SEC_AHB_AHB3_BRIDGE 71 1390f32e64bSAlexander Müller #define CLKID_CLK81_A9 72 1400f32e64bSAlexander Müller #define CLKID_VCLK2_VENCI0 73 1410f32e64bSAlexander Müller #define CLKID_VCLK2_VENCI1 74 1420f32e64bSAlexander Müller #define CLKID_VCLK2_VENCP0 75 1430f32e64bSAlexander Müller #define CLKID_VCLK2_VENCP1 76 1440f32e64bSAlexander Müller #define CLKID_GCLK_VENCI_INT 77 1450f32e64bSAlexander Müller #define CLKID_GCLK_VENCP_INT 78 1460f32e64bSAlexander Müller #define CLKID_DAC_CLK 79 1470f32e64bSAlexander Müller #define CLKID_AOCLK_GATE 80 1480f32e64bSAlexander Müller #define CLKID_IEC958_GATE 81 1490f32e64bSAlexander Müller #define CLKID_ENC480P 82 1500f32e64bSAlexander Müller #define CLKID_RNG1 83 1510f32e64bSAlexander Müller #define CLKID_GCLK_VENCL_INT 84 1520f32e64bSAlexander Müller #define CLKID_VCLK2_VENCLMCC 85 1530f32e64bSAlexander Müller #define CLKID_VCLK2_VENCL 86 1540f32e64bSAlexander Müller #define CLKID_VCLK2_OTHER 87 1550f32e64bSAlexander Müller #define CLKID_EDP 88 1560f32e64bSAlexander Müller #define CLKID_AO_MEDIA_CPU 89 1570f32e64bSAlexander Müller #define CLKID_AO_AHB_SRAM 90 1580f32e64bSAlexander Müller #define CLKID_AO_AHB_BUS 91 1590f32e64bSAlexander Müller #define CLKID_AO_IFACE 92 160b778f745SJerome Brunet #define CLKID_MPLL0 93 161b778f745SJerome Brunet #define CLKID_MPLL1 94 162b778f745SJerome Brunet #define CLKID_MPLL2 95 1630f32e64bSAlexander Müller 164b778f745SJerome Brunet #define CLK_NR_CLKS 96 1650f32e64bSAlexander Müller 1660f32e64bSAlexander Müller /* include the CLKIDs that have been made part of the stable DT binding */ 1670f32e64bSAlexander Müller #include <dt-bindings/clock/meson8b-clkc.h> 1680f32e64bSAlexander Müller 169d0c175daSAlexander Müller #endif /* __MESON8B_H */ 170