122f65a38SJerome Brunet /* SPDX-License-Identifier: GPL-2.0 */ 2d0c175daSAlexander Müller /* 3d0c175daSAlexander Müller * Copyright (c) 2015 Endless Mobile, Inc. 4d0c175daSAlexander Müller * Author: Carlo Caione <carlo@endlessm.com> 5d0c175daSAlexander Müller * 6d0c175daSAlexander Müller * Copyright (c) 2016 BayLibre, Inc. 7d0c175daSAlexander Müller * Michael Turquette <mturquette@baylibre.com> 8d0c175daSAlexander Müller */ 9d0c175daSAlexander Müller 10d0c175daSAlexander Müller #ifndef __MESON8B_H 11d0c175daSAlexander Müller #define __MESON8B_H 12d0c175daSAlexander Müller 13d0c175daSAlexander Müller /* 14d0c175daSAlexander Müller * Clock controller register offsets 15d0c175daSAlexander Müller * 16d0c175daSAlexander Müller * Register offsets from the HardKernel[0] data sheet are listed in comment 17d0c175daSAlexander Müller * blocks below. Those offsets must be multiplied by 4 before adding them to 18d0c175daSAlexander Müller * the base address to get the right value 19d0c175daSAlexander Müller * 20d0c175daSAlexander Müller * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 21d0c175daSAlexander Müller */ 22e31a1900SAlexander Müller #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 23e31a1900SAlexander Müller #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 24e31a1900SAlexander Müller #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 25e31a1900SAlexander Müller #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 26e31a1900SAlexander Müller #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 27e0818a39SAlexander Müller #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 28e0818a39SAlexander Müller #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 2918962172SMartin Blumenstingl #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 3018962172SMartin Blumenstingl #define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ 3118962172SMartin Blumenstingl #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 32b8c1ddadSMartin Blumenstingl #define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */ 33e0818a39SAlexander Müller #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 34e0818a39SAlexander Müller #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 35e0818a39SAlexander Müller #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 36d0c175daSAlexander Müller 370f32e64bSAlexander Müller /* 38b778f745SJerome Brunet * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 39b778f745SJerome Brunet * confirm these are the same for the S805. 40b778f745SJerome Brunet */ 41b778f745SJerome Brunet #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 42b778f745SJerome Brunet #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 43b778f745SJerome Brunet #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 44b778f745SJerome Brunet #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 45b778f745SJerome Brunet #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 46b778f745SJerome Brunet #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 47b778f745SJerome Brunet #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ 48b778f745SJerome Brunet #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ 49b778f745SJerome Brunet #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ 50b778f745SJerome Brunet #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ 51b778f745SJerome Brunet 52b778f745SJerome Brunet /* 530f32e64bSAlexander Müller * CLKID index values 540f32e64bSAlexander Müller * 550f32e64bSAlexander Müller * These indices are entirely contrived and do not map onto the hardware. 5631128822SJerome Brunet * It has now been decided to expose everything by default in the DT header: 5731128822SJerome Brunet * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want 5831128822SJerome Brunet * to expose, such as the internal muxes and dividers of composite clocks, 5931128822SJerome Brunet * will remain defined here. 600f32e64bSAlexander Müller */ 610f32e64bSAlexander Müller 62d610b54fSJerome Brunet #define CLKID_MPLL0_DIV 96 63d610b54fSJerome Brunet #define CLKID_MPLL1_DIV 97 64d610b54fSJerome Brunet #define CLKID_MPLL2_DIV 98 65251b6fd3SJerome Brunet #define CLKID_CPU_IN_SEL 99 66700ecf7fSMartin Blumenstingl #define CLKID_CPU_IN_DIV2 100 67700ecf7fSMartin Blumenstingl #define CLKID_CPU_IN_DIV3 101 68251b6fd3SJerome Brunet #define CLKID_CPU_SCALE_DIV 102 69251b6fd3SJerome Brunet #define CLKID_CPU_SCALE_OUT_SEL 103 70513b67acSJerome Brunet #define CLKID_MPLL_PREDIV 104 7105f81440SJerome Brunet #define CLKID_FCLK_DIV2_DIV 105 7205f81440SJerome Brunet #define CLKID_FCLK_DIV3_DIV 106 7305f81440SJerome Brunet #define CLKID_FCLK_DIV4_DIV 107 7405f81440SJerome Brunet #define CLKID_FCLK_DIV5_DIV 108 7505f81440SJerome Brunet #define CLKID_FCLK_DIV7_DIV 109 76b8c1ddadSMartin Blumenstingl #define CLKID_NAND_SEL 110 77b8c1ddadSMartin Blumenstingl #define CLKID_NAND_DIV 111 7887173557SJerome Brunet #define CLKID_PLL_FIXED_DCO 113 7987173557SJerome Brunet #define CLKID_PLL_VID_DCO 114 8087173557SJerome Brunet #define CLKID_PLL_SYS_DCO 115 81a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV2 116 82a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV3 117 83a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV4 118 84a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV5 119 85a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV6 120 86a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV7 121 87a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV8 122 88a7d19b05SMartin Blumenstingl #define CLKID_ABP_SEL 123 89a7d19b05SMartin Blumenstingl #define CLKID_PERIPH_SEL 125 90a7d19b05SMartin Blumenstingl #define CLKID_AXI_SEL 127 91a7d19b05SMartin Blumenstingl #define CLKID_L2_DRAM_SEL 129 92d610b54fSJerome Brunet 93a7d19b05SMartin Blumenstingl #define CLK_NR_CLKS 131 940f32e64bSAlexander Müller 9518962172SMartin Blumenstingl /* 9618962172SMartin Blumenstingl * include the CLKID and RESETID that have 9718962172SMartin Blumenstingl * been made part of the stable DT binding 9818962172SMartin Blumenstingl */ 990f32e64bSAlexander Müller #include <dt-bindings/clock/meson8b-clkc.h> 10018962172SMartin Blumenstingl #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 1010f32e64bSAlexander Müller 102d0c175daSAlexander Müller #endif /* __MESON8B_H */ 103