122f65a38SJerome Brunet /* SPDX-License-Identifier: GPL-2.0 */ 2d0c175daSAlexander Müller /* 3d0c175daSAlexander Müller * Copyright (c) 2015 Endless Mobile, Inc. 4d0c175daSAlexander Müller * Author: Carlo Caione <carlo@endlessm.com> 5d0c175daSAlexander Müller * 6d0c175daSAlexander Müller * Copyright (c) 2016 BayLibre, Inc. 7d0c175daSAlexander Müller * Michael Turquette <mturquette@baylibre.com> 8d0c175daSAlexander Müller */ 9d0c175daSAlexander Müller 10d0c175daSAlexander Müller #ifndef __MESON8B_H 11d0c175daSAlexander Müller #define __MESON8B_H 12d0c175daSAlexander Müller 13d0c175daSAlexander Müller /* 14d0c175daSAlexander Müller * Clock controller register offsets 15d0c175daSAlexander Müller * 16d0c175daSAlexander Müller * Register offsets from the HardKernel[0] data sheet are listed in comment 17d0c175daSAlexander Müller * blocks below. Those offsets must be multiplied by 4 before adding them to 18d0c175daSAlexander Müller * the base address to get the right value 19d0c175daSAlexander Müller * 20d0c175daSAlexander Müller * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 21d0c175daSAlexander Müller */ 226cb57c67SMartin Blumenstingl #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ 236cb57c67SMartin Blumenstingl #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ 24e31a1900SAlexander Müller #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 25e31a1900SAlexander Müller #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 26e31a1900SAlexander Müller #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 27e31a1900SAlexander Müller #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 28e31a1900SAlexander Müller #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 29e0818a39SAlexander Müller #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 306cb57c67SMartin Blumenstingl #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ 31e0818a39SAlexander Müller #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 3218962172SMartin Blumenstingl #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 336cb57c67SMartin Blumenstingl #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ 3418962172SMartin Blumenstingl #define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ 3518962172SMartin Blumenstingl #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 366cb57c67SMartin Blumenstingl #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ 37b8c1ddadSMartin Blumenstingl #define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */ 38e0818a39SAlexander Müller #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 39e0818a39SAlexander Müller #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 40e0818a39SAlexander Müller #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 41007f3da7SMartin Blumenstingl #define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ 42d0c175daSAlexander Müller 430f32e64bSAlexander Müller /* 44b778f745SJerome Brunet * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 45b778f745SJerome Brunet * confirm these are the same for the S805. 46b778f745SJerome Brunet */ 47b778f745SJerome Brunet #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 48b778f745SJerome Brunet #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 49b778f745SJerome Brunet #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 50b778f745SJerome Brunet #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 51b778f745SJerome Brunet #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 52b778f745SJerome Brunet #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 53b778f745SJerome Brunet #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ 54b778f745SJerome Brunet #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ 55b778f745SJerome Brunet #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ 56b778f745SJerome Brunet #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ 57b778f745SJerome Brunet 58b778f745SJerome Brunet /* 590f32e64bSAlexander Müller * CLKID index values 600f32e64bSAlexander Müller * 610f32e64bSAlexander Müller * These indices are entirely contrived and do not map onto the hardware. 6231128822SJerome Brunet * It has now been decided to expose everything by default in the DT header: 6331128822SJerome Brunet * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want 6431128822SJerome Brunet * to expose, such as the internal muxes and dividers of composite clocks, 6531128822SJerome Brunet * will remain defined here. 660f32e64bSAlexander Müller */ 670f32e64bSAlexander Müller 68d610b54fSJerome Brunet #define CLKID_MPLL0_DIV 96 69d610b54fSJerome Brunet #define CLKID_MPLL1_DIV 97 70d610b54fSJerome Brunet #define CLKID_MPLL2_DIV 98 71251b6fd3SJerome Brunet #define CLKID_CPU_IN_SEL 99 72700ecf7fSMartin Blumenstingl #define CLKID_CPU_IN_DIV2 100 73700ecf7fSMartin Blumenstingl #define CLKID_CPU_IN_DIV3 101 74251b6fd3SJerome Brunet #define CLKID_CPU_SCALE_DIV 102 75251b6fd3SJerome Brunet #define CLKID_CPU_SCALE_OUT_SEL 103 76513b67acSJerome Brunet #define CLKID_MPLL_PREDIV 104 7705f81440SJerome Brunet #define CLKID_FCLK_DIV2_DIV 105 7805f81440SJerome Brunet #define CLKID_FCLK_DIV3_DIV 106 7905f81440SJerome Brunet #define CLKID_FCLK_DIV4_DIV 107 8005f81440SJerome Brunet #define CLKID_FCLK_DIV5_DIV 108 8105f81440SJerome Brunet #define CLKID_FCLK_DIV7_DIV 109 82b8c1ddadSMartin Blumenstingl #define CLKID_NAND_SEL 110 83b8c1ddadSMartin Blumenstingl #define CLKID_NAND_DIV 111 8487173557SJerome Brunet #define CLKID_PLL_FIXED_DCO 113 856cb57c67SMartin Blumenstingl #define CLKID_HDMI_PLL_DCO 114 8687173557SJerome Brunet #define CLKID_PLL_SYS_DCO 115 87a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV2 116 88a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV3 117 89a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV4 118 90a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV5 119 91a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV6 120 92a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV7 121 93a7d19b05SMartin Blumenstingl #define CLKID_CPU_CLK_DIV8 122 94a7d19b05SMartin Blumenstingl #define CLKID_ABP_SEL 123 95a7d19b05SMartin Blumenstingl #define CLKID_PERIPH_SEL 125 96a7d19b05SMartin Blumenstingl #define CLKID_AXI_SEL 127 97a7d19b05SMartin Blumenstingl #define CLKID_L2_DRAM_SEL 129 986cb57c67SMartin Blumenstingl #define CLKID_HDMI_PLL_LVDS_OUT 131 996cb57c67SMartin Blumenstingl #define CLKID_HDMI_PLL_HDMI_OUT 132 1006cb57c67SMartin Blumenstingl #define CLKID_VID_PLL_IN_SEL 133 1016cb57c67SMartin Blumenstingl #define CLKID_VID_PLL_IN_EN 134 1026cb57c67SMartin Blumenstingl #define CLKID_VID_PLL_PRE_DIV 135 1036cb57c67SMartin Blumenstingl #define CLKID_VID_PLL_POST_DIV 136 1046cb57c67SMartin Blumenstingl #define CLKID_VID_PLL_FINAL_DIV 137 1056cb57c67SMartin Blumenstingl #define CLKID_VCLK_IN_SEL 138 1066cb57c67SMartin Blumenstingl #define CLKID_VCLK_IN_EN 139 1076cb57c67SMartin Blumenstingl #define CLKID_VCLK_DIV1 140 1086cb57c67SMartin Blumenstingl #define CLKID_VCLK_DIV2_DIV 141 1096cb57c67SMartin Blumenstingl #define CLKID_VCLK_DIV2 142 1106cb57c67SMartin Blumenstingl #define CLKID_VCLK_DIV4_DIV 143 1116cb57c67SMartin Blumenstingl #define CLKID_VCLK_DIV4 144 1126cb57c67SMartin Blumenstingl #define CLKID_VCLK_DIV6_DIV 145 1136cb57c67SMartin Blumenstingl #define CLKID_VCLK_DIV6 146 1146cb57c67SMartin Blumenstingl #define CLKID_VCLK_DIV12_DIV 147 1156cb57c67SMartin Blumenstingl #define CLKID_VCLK_DIV12 148 1166cb57c67SMartin Blumenstingl #define CLKID_VCLK2_IN_SEL 149 1176cb57c67SMartin Blumenstingl #define CLKID_VCLK2_IN_EN 150 1186cb57c67SMartin Blumenstingl #define CLKID_VCLK2_DIV1 151 1196cb57c67SMartin Blumenstingl #define CLKID_VCLK2_DIV2_DIV 152 1206cb57c67SMartin Blumenstingl #define CLKID_VCLK2_DIV2 153 1216cb57c67SMartin Blumenstingl #define CLKID_VCLK2_DIV4_DIV 154 1226cb57c67SMartin Blumenstingl #define CLKID_VCLK2_DIV4 155 1236cb57c67SMartin Blumenstingl #define CLKID_VCLK2_DIV6_DIV 156 1246cb57c67SMartin Blumenstingl #define CLKID_VCLK2_DIV6 157 1256cb57c67SMartin Blumenstingl #define CLKID_VCLK2_DIV12_DIV 158 1266cb57c67SMartin Blumenstingl #define CLKID_VCLK2_DIV12 159 1276cb57c67SMartin Blumenstingl #define CLKID_CTS_ENCT_SEL 160 1286cb57c67SMartin Blumenstingl #define CLKID_CTS_ENCT 161 1296cb57c67SMartin Blumenstingl #define CLKID_CTS_ENCP_SEL 162 1306cb57c67SMartin Blumenstingl #define CLKID_CTS_ENCP 163 1316cb57c67SMartin Blumenstingl #define CLKID_CTS_ENCI_SEL 164 1326cb57c67SMartin Blumenstingl #define CLKID_CTS_ENCI 165 1336cb57c67SMartin Blumenstingl #define CLKID_HDMI_TX_PIXEL_SEL 166 1346cb57c67SMartin Blumenstingl #define CLKID_HDMI_TX_PIXEL 167 1356cb57c67SMartin Blumenstingl #define CLKID_CTS_ENCL_SEL 168 1366cb57c67SMartin Blumenstingl #define CLKID_CTS_ENCL 169 1376cb57c67SMartin Blumenstingl #define CLKID_CTS_VDAC0_SEL 170 1386cb57c67SMartin Blumenstingl #define CLKID_CTS_VDAC0 171 1396cb57c67SMartin Blumenstingl #define CLKID_HDMI_SYS_SEL 172 1406cb57c67SMartin Blumenstingl #define CLKID_HDMI_SYS_DIV 173 1416cb57c67SMartin Blumenstingl #define CLKID_HDMI_SYS 174 142d610b54fSJerome Brunet 1436cb57c67SMartin Blumenstingl #define CLK_NR_CLKS 175 1440f32e64bSAlexander Müller 14518962172SMartin Blumenstingl /* 14618962172SMartin Blumenstingl * include the CLKID and RESETID that have 14718962172SMartin Blumenstingl * been made part of the stable DT binding 14818962172SMartin Blumenstingl */ 1490f32e64bSAlexander Müller #include <dt-bindings/clock/meson8b-clkc.h> 15018962172SMartin Blumenstingl #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 1510f32e64bSAlexander Müller 152d0c175daSAlexander Müller #endif /* __MESON8B_H */ 153