1d0c175daSAlexander Müller /* 2d0c175daSAlexander Müller * Copyright (c) 2015 Endless Mobile, Inc. 3d0c175daSAlexander Müller * Author: Carlo Caione <carlo@endlessm.com> 4d0c175daSAlexander Müller * 5d0c175daSAlexander Müller * Copyright (c) 2016 BayLibre, Inc. 6d0c175daSAlexander Müller * Michael Turquette <mturquette@baylibre.com> 7d0c175daSAlexander Müller * 8d0c175daSAlexander Müller * This program is free software; you can redistribute it and/or modify it 9d0c175daSAlexander Müller * under the terms and conditions of the GNU General Public License, 10d0c175daSAlexander Müller * version 2, as published by the Free Software Foundation. 11d0c175daSAlexander Müller * 12d0c175daSAlexander Müller * This program is distributed in the hope it will be useful, but WITHOUT 13d0c175daSAlexander Müller * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14d0c175daSAlexander Müller * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15d0c175daSAlexander Müller * more details. 16d0c175daSAlexander Müller * 17d0c175daSAlexander Müller * You should have received a copy of the GNU General Public License along with 18d0c175daSAlexander Müller * this program. If not, see <http://www.gnu.org/licenses/>. 19d0c175daSAlexander Müller */ 20d0c175daSAlexander Müller 21d0c175daSAlexander Müller #ifndef __MESON8B_H 22d0c175daSAlexander Müller #define __MESON8B_H 23d0c175daSAlexander Müller 24d0c175daSAlexander Müller /* 25d0c175daSAlexander Müller * Clock controller register offsets 26d0c175daSAlexander Müller * 27d0c175daSAlexander Müller * Register offsets from the HardKernel[0] data sheet are listed in comment 28d0c175daSAlexander Müller * blocks below. Those offsets must be multiplied by 4 before adding them to 29d0c175daSAlexander Müller * the base address to get the right value 30d0c175daSAlexander Müller * 31d0c175daSAlexander Müller * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 32d0c175daSAlexander Müller */ 33e31a1900SAlexander Müller #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 34e31a1900SAlexander Müller #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 35e31a1900SAlexander Müller #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 36e31a1900SAlexander Müller #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 37e31a1900SAlexander Müller #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 38e0818a39SAlexander Müller #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 39e0818a39SAlexander Müller #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 4018962172SMartin Blumenstingl #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 4118962172SMartin Blumenstingl #define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ 4218962172SMartin Blumenstingl #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 43e0818a39SAlexander Müller #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 44e0818a39SAlexander Müller #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 45e0818a39SAlexander Müller #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 46d0c175daSAlexander Müller 470f32e64bSAlexander Müller /* 48b778f745SJerome Brunet * MPLL register offeset taken from the S905 datasheet. Vendor kernel source 49b778f745SJerome Brunet * confirm these are the same for the S805. 50b778f745SJerome Brunet */ 51b778f745SJerome Brunet #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 52b778f745SJerome Brunet #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 53b778f745SJerome Brunet #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 54b778f745SJerome Brunet #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 55b778f745SJerome Brunet #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 56b778f745SJerome Brunet #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 57b778f745SJerome Brunet #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ 58b778f745SJerome Brunet #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ 59b778f745SJerome Brunet #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ 60b778f745SJerome Brunet #define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ 61b778f745SJerome Brunet 62b778f745SJerome Brunet /* 630f32e64bSAlexander Müller * CLKID index values 640f32e64bSAlexander Müller * 650f32e64bSAlexander Müller * These indices are entirely contrived and do not map onto the hardware. 6631128822SJerome Brunet * It has now been decided to expose everything by default in the DT header: 6731128822SJerome Brunet * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want 6831128822SJerome Brunet * to expose, such as the internal muxes and dividers of composite clocks, 6931128822SJerome Brunet * will remain defined here. 700f32e64bSAlexander Müller */ 710f32e64bSAlexander Müller 72b778f745SJerome Brunet #define CLK_NR_CLKS 96 730f32e64bSAlexander Müller 7418962172SMartin Blumenstingl /* 7518962172SMartin Blumenstingl * include the CLKID and RESETID that have 7618962172SMartin Blumenstingl * been made part of the stable DT binding 7718962172SMartin Blumenstingl */ 780f32e64bSAlexander Müller #include <dt-bindings/clock/meson8b-clkc.h> 7918962172SMartin Blumenstingl #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 800f32e64bSAlexander Müller 81d0c175daSAlexander Müller #endif /* __MESON8B_H */ 82