1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 * 6 * Copyright (c) 2016 BayLibre, Inc. 7 * Michael Turquette <mturquette@baylibre.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/init.h> 13 #include <linux/of_address.h> 14 #include <linux/reset-controller.h> 15 #include <linux/slab.h> 16 #include <linux/regmap.h> 17 18 #include "clkc.h" 19 #include "meson8b.h" 20 #include "clk-regmap.h" 21 22 static DEFINE_SPINLOCK(meson_clk_lock); 23 24 struct meson8b_clk_reset { 25 struct reset_controller_dev reset; 26 struct regmap *regmap; 27 }; 28 29 static const struct pll_params_table sys_pll_params_table[] = { 30 PLL_PARAMS(50, 1), 31 PLL_PARAMS(51, 1), 32 PLL_PARAMS(52, 1), 33 PLL_PARAMS(53, 1), 34 PLL_PARAMS(54, 1), 35 PLL_PARAMS(55, 1), 36 PLL_PARAMS(56, 1), 37 PLL_PARAMS(57, 1), 38 PLL_PARAMS(58, 1), 39 PLL_PARAMS(59, 1), 40 PLL_PARAMS(60, 1), 41 PLL_PARAMS(61, 1), 42 PLL_PARAMS(62, 1), 43 PLL_PARAMS(63, 1), 44 PLL_PARAMS(64, 1), 45 { /* sentinel */ }, 46 }; 47 48 static struct clk_fixed_rate meson8b_xtal = { 49 .fixed_rate = 24000000, 50 .hw.init = &(struct clk_init_data){ 51 .name = "xtal", 52 .num_parents = 0, 53 .ops = &clk_fixed_rate_ops, 54 }, 55 }; 56 57 static struct clk_regmap meson8b_fixed_pll_dco = { 58 .data = &(struct meson_clk_pll_data){ 59 .en = { 60 .reg_off = HHI_MPLL_CNTL, 61 .shift = 30, 62 .width = 1, 63 }, 64 .m = { 65 .reg_off = HHI_MPLL_CNTL, 66 .shift = 0, 67 .width = 9, 68 }, 69 .n = { 70 .reg_off = HHI_MPLL_CNTL, 71 .shift = 9, 72 .width = 5, 73 }, 74 .frac = { 75 .reg_off = HHI_MPLL_CNTL2, 76 .shift = 0, 77 .width = 12, 78 }, 79 .l = { 80 .reg_off = HHI_MPLL_CNTL, 81 .shift = 31, 82 .width = 1, 83 }, 84 .rst = { 85 .reg_off = HHI_MPLL_CNTL, 86 .shift = 29, 87 .width = 1, 88 }, 89 }, 90 .hw.init = &(struct clk_init_data){ 91 .name = "fixed_pll_dco", 92 .ops = &meson_clk_pll_ro_ops, 93 .parent_names = (const char *[]){ "xtal" }, 94 .num_parents = 1, 95 }, 96 }; 97 98 static struct clk_regmap meson8b_fixed_pll = { 99 .data = &(struct clk_regmap_div_data){ 100 .offset = HHI_MPLL_CNTL, 101 .shift = 16, 102 .width = 2, 103 .flags = CLK_DIVIDER_POWER_OF_TWO, 104 }, 105 .hw.init = &(struct clk_init_data){ 106 .name = "fixed_pll", 107 .ops = &clk_regmap_divider_ro_ops, 108 .parent_names = (const char *[]){ "fixed_pll_dco" }, 109 .num_parents = 1, 110 /* 111 * This clock won't ever change at runtime so 112 * CLK_SET_RATE_PARENT is not required 113 */ 114 }, 115 }; 116 117 static struct clk_regmap meson8b_vid_pll_dco = { 118 .data = &(struct meson_clk_pll_data){ 119 .en = { 120 .reg_off = HHI_VID_PLL_CNTL, 121 .shift = 30, 122 .width = 1, 123 }, 124 .m = { 125 .reg_off = HHI_VID_PLL_CNTL, 126 .shift = 0, 127 .width = 9, 128 }, 129 .n = { 130 .reg_off = HHI_VID_PLL_CNTL, 131 .shift = 9, 132 .width = 5, 133 }, 134 .l = { 135 .reg_off = HHI_VID_PLL_CNTL, 136 .shift = 31, 137 .width = 1, 138 }, 139 .rst = { 140 .reg_off = HHI_VID_PLL_CNTL, 141 .shift = 29, 142 .width = 1, 143 }, 144 }, 145 .hw.init = &(struct clk_init_data){ 146 .name = "vid_pll_dco", 147 .ops = &meson_clk_pll_ro_ops, 148 .parent_names = (const char *[]){ "xtal" }, 149 .num_parents = 1, 150 }, 151 }; 152 153 static struct clk_regmap meson8b_vid_pll = { 154 .data = &(struct clk_regmap_div_data){ 155 .offset = HHI_VID_PLL_CNTL, 156 .shift = 16, 157 .width = 2, 158 .flags = CLK_DIVIDER_POWER_OF_TWO, 159 }, 160 .hw.init = &(struct clk_init_data){ 161 .name = "vid_pll", 162 .ops = &clk_regmap_divider_ro_ops, 163 .parent_names = (const char *[]){ "vid_pll_dco" }, 164 .num_parents = 1, 165 .flags = CLK_SET_RATE_PARENT, 166 }, 167 }; 168 169 static struct clk_regmap meson8b_sys_pll_dco = { 170 .data = &(struct meson_clk_pll_data){ 171 .en = { 172 .reg_off = HHI_SYS_PLL_CNTL, 173 .shift = 30, 174 .width = 1, 175 }, 176 .m = { 177 .reg_off = HHI_SYS_PLL_CNTL, 178 .shift = 0, 179 .width = 9, 180 }, 181 .n = { 182 .reg_off = HHI_SYS_PLL_CNTL, 183 .shift = 9, 184 .width = 5, 185 }, 186 .l = { 187 .reg_off = HHI_SYS_PLL_CNTL, 188 .shift = 31, 189 .width = 1, 190 }, 191 .rst = { 192 .reg_off = HHI_SYS_PLL_CNTL, 193 .shift = 29, 194 .width = 1, 195 }, 196 .table = sys_pll_params_table, 197 }, 198 .hw.init = &(struct clk_init_data){ 199 .name = "sys_pll_dco", 200 .ops = &meson_clk_pll_ro_ops, 201 .parent_names = (const char *[]){ "xtal" }, 202 .num_parents = 1, 203 }, 204 }; 205 206 static struct clk_regmap meson8b_sys_pll = { 207 .data = &(struct clk_regmap_div_data){ 208 .offset = HHI_SYS_PLL_CNTL, 209 .shift = 16, 210 .width = 2, 211 .flags = CLK_DIVIDER_POWER_OF_TWO, 212 }, 213 .hw.init = &(struct clk_init_data){ 214 .name = "sys_pll", 215 .ops = &clk_regmap_divider_ro_ops, 216 .parent_names = (const char *[]){ "sys_pll_dco" }, 217 .num_parents = 1, 218 .flags = CLK_SET_RATE_PARENT, 219 }, 220 }; 221 222 static struct clk_fixed_factor meson8b_fclk_div2_div = { 223 .mult = 1, 224 .div = 2, 225 .hw.init = &(struct clk_init_data){ 226 .name = "fclk_div2_div", 227 .ops = &clk_fixed_factor_ops, 228 .parent_names = (const char *[]){ "fixed_pll" }, 229 .num_parents = 1, 230 }, 231 }; 232 233 static struct clk_regmap meson8b_fclk_div2 = { 234 .data = &(struct clk_regmap_gate_data){ 235 .offset = HHI_MPLL_CNTL6, 236 .bit_idx = 27, 237 }, 238 .hw.init = &(struct clk_init_data){ 239 .name = "fclk_div2", 240 .ops = &clk_regmap_gate_ops, 241 .parent_names = (const char *[]){ "fclk_div2_div" }, 242 .num_parents = 1, 243 /* 244 * FIXME: Ethernet with a RGMII PHYs is not working if 245 * fclk_div2 is disabled. it is currently unclear why this 246 * is. keep it enabled until the Ethernet driver knows how 247 * to manage this clock. 248 */ 249 .flags = CLK_IS_CRITICAL, 250 }, 251 }; 252 253 static struct clk_fixed_factor meson8b_fclk_div3_div = { 254 .mult = 1, 255 .div = 3, 256 .hw.init = &(struct clk_init_data){ 257 .name = "fclk_div3_div", 258 .ops = &clk_fixed_factor_ops, 259 .parent_names = (const char *[]){ "fixed_pll" }, 260 .num_parents = 1, 261 }, 262 }; 263 264 static struct clk_regmap meson8b_fclk_div3 = { 265 .data = &(struct clk_regmap_gate_data){ 266 .offset = HHI_MPLL_CNTL6, 267 .bit_idx = 28, 268 }, 269 .hw.init = &(struct clk_init_data){ 270 .name = "fclk_div3", 271 .ops = &clk_regmap_gate_ops, 272 .parent_names = (const char *[]){ "fclk_div3_div" }, 273 .num_parents = 1, 274 }, 275 }; 276 277 static struct clk_fixed_factor meson8b_fclk_div4_div = { 278 .mult = 1, 279 .div = 4, 280 .hw.init = &(struct clk_init_data){ 281 .name = "fclk_div4_div", 282 .ops = &clk_fixed_factor_ops, 283 .parent_names = (const char *[]){ "fixed_pll" }, 284 .num_parents = 1, 285 }, 286 }; 287 288 static struct clk_regmap meson8b_fclk_div4 = { 289 .data = &(struct clk_regmap_gate_data){ 290 .offset = HHI_MPLL_CNTL6, 291 .bit_idx = 29, 292 }, 293 .hw.init = &(struct clk_init_data){ 294 .name = "fclk_div4", 295 .ops = &clk_regmap_gate_ops, 296 .parent_names = (const char *[]){ "fclk_div4_div" }, 297 .num_parents = 1, 298 }, 299 }; 300 301 static struct clk_fixed_factor meson8b_fclk_div5_div = { 302 .mult = 1, 303 .div = 5, 304 .hw.init = &(struct clk_init_data){ 305 .name = "fclk_div5_div", 306 .ops = &clk_fixed_factor_ops, 307 .parent_names = (const char *[]){ "fixed_pll" }, 308 .num_parents = 1, 309 }, 310 }; 311 312 static struct clk_regmap meson8b_fclk_div5 = { 313 .data = &(struct clk_regmap_gate_data){ 314 .offset = HHI_MPLL_CNTL6, 315 .bit_idx = 30, 316 }, 317 .hw.init = &(struct clk_init_data){ 318 .name = "fclk_div5", 319 .ops = &clk_regmap_gate_ops, 320 .parent_names = (const char *[]){ "fclk_div5_div" }, 321 .num_parents = 1, 322 }, 323 }; 324 325 static struct clk_fixed_factor meson8b_fclk_div7_div = { 326 .mult = 1, 327 .div = 7, 328 .hw.init = &(struct clk_init_data){ 329 .name = "fclk_div7_div", 330 .ops = &clk_fixed_factor_ops, 331 .parent_names = (const char *[]){ "fixed_pll" }, 332 .num_parents = 1, 333 }, 334 }; 335 336 static struct clk_regmap meson8b_fclk_div7 = { 337 .data = &(struct clk_regmap_gate_data){ 338 .offset = HHI_MPLL_CNTL6, 339 .bit_idx = 31, 340 }, 341 .hw.init = &(struct clk_init_data){ 342 .name = "fclk_div7", 343 .ops = &clk_regmap_gate_ops, 344 .parent_names = (const char *[]){ "fclk_div7_div" }, 345 .num_parents = 1, 346 }, 347 }; 348 349 static struct clk_regmap meson8b_mpll_prediv = { 350 .data = &(struct clk_regmap_div_data){ 351 .offset = HHI_MPLL_CNTL5, 352 .shift = 12, 353 .width = 1, 354 }, 355 .hw.init = &(struct clk_init_data){ 356 .name = "mpll_prediv", 357 .ops = &clk_regmap_divider_ro_ops, 358 .parent_names = (const char *[]){ "fixed_pll" }, 359 .num_parents = 1, 360 }, 361 }; 362 363 static struct clk_regmap meson8b_mpll0_div = { 364 .data = &(struct meson_clk_mpll_data){ 365 .sdm = { 366 .reg_off = HHI_MPLL_CNTL7, 367 .shift = 0, 368 .width = 14, 369 }, 370 .sdm_en = { 371 .reg_off = HHI_MPLL_CNTL7, 372 .shift = 15, 373 .width = 1, 374 }, 375 .n2 = { 376 .reg_off = HHI_MPLL_CNTL7, 377 .shift = 16, 378 .width = 9, 379 }, 380 .ssen = { 381 .reg_off = HHI_MPLL_CNTL, 382 .shift = 25, 383 .width = 1, 384 }, 385 .lock = &meson_clk_lock, 386 }, 387 .hw.init = &(struct clk_init_data){ 388 .name = "mpll0_div", 389 .ops = &meson_clk_mpll_ops, 390 .parent_names = (const char *[]){ "mpll_prediv" }, 391 .num_parents = 1, 392 }, 393 }; 394 395 static struct clk_regmap meson8b_mpll0 = { 396 .data = &(struct clk_regmap_gate_data){ 397 .offset = HHI_MPLL_CNTL7, 398 .bit_idx = 14, 399 }, 400 .hw.init = &(struct clk_init_data){ 401 .name = "mpll0", 402 .ops = &clk_regmap_gate_ops, 403 .parent_names = (const char *[]){ "mpll0_div" }, 404 .num_parents = 1, 405 .flags = CLK_SET_RATE_PARENT, 406 }, 407 }; 408 409 static struct clk_regmap meson8b_mpll1_div = { 410 .data = &(struct meson_clk_mpll_data){ 411 .sdm = { 412 .reg_off = HHI_MPLL_CNTL8, 413 .shift = 0, 414 .width = 14, 415 }, 416 .sdm_en = { 417 .reg_off = HHI_MPLL_CNTL8, 418 .shift = 15, 419 .width = 1, 420 }, 421 .n2 = { 422 .reg_off = HHI_MPLL_CNTL8, 423 .shift = 16, 424 .width = 9, 425 }, 426 .lock = &meson_clk_lock, 427 }, 428 .hw.init = &(struct clk_init_data){ 429 .name = "mpll1_div", 430 .ops = &meson_clk_mpll_ops, 431 .parent_names = (const char *[]){ "mpll_prediv" }, 432 .num_parents = 1, 433 }, 434 }; 435 436 static struct clk_regmap meson8b_mpll1 = { 437 .data = &(struct clk_regmap_gate_data){ 438 .offset = HHI_MPLL_CNTL8, 439 .bit_idx = 14, 440 }, 441 .hw.init = &(struct clk_init_data){ 442 .name = "mpll1", 443 .ops = &clk_regmap_gate_ops, 444 .parent_names = (const char *[]){ "mpll1_div" }, 445 .num_parents = 1, 446 .flags = CLK_SET_RATE_PARENT, 447 }, 448 }; 449 450 static struct clk_regmap meson8b_mpll2_div = { 451 .data = &(struct meson_clk_mpll_data){ 452 .sdm = { 453 .reg_off = HHI_MPLL_CNTL9, 454 .shift = 0, 455 .width = 14, 456 }, 457 .sdm_en = { 458 .reg_off = HHI_MPLL_CNTL9, 459 .shift = 15, 460 .width = 1, 461 }, 462 .n2 = { 463 .reg_off = HHI_MPLL_CNTL9, 464 .shift = 16, 465 .width = 9, 466 }, 467 .lock = &meson_clk_lock, 468 }, 469 .hw.init = &(struct clk_init_data){ 470 .name = "mpll2_div", 471 .ops = &meson_clk_mpll_ops, 472 .parent_names = (const char *[]){ "mpll_prediv" }, 473 .num_parents = 1, 474 }, 475 }; 476 477 static struct clk_regmap meson8b_mpll2 = { 478 .data = &(struct clk_regmap_gate_data){ 479 .offset = HHI_MPLL_CNTL9, 480 .bit_idx = 14, 481 }, 482 .hw.init = &(struct clk_init_data){ 483 .name = "mpll2", 484 .ops = &clk_regmap_gate_ops, 485 .parent_names = (const char *[]){ "mpll2_div" }, 486 .num_parents = 1, 487 .flags = CLK_SET_RATE_PARENT, 488 }, 489 }; 490 491 static u32 mux_table_clk81[] = { 6, 5, 7 }; 492 static struct clk_regmap meson8b_mpeg_clk_sel = { 493 .data = &(struct clk_regmap_mux_data){ 494 .offset = HHI_MPEG_CLK_CNTL, 495 .mask = 0x7, 496 .shift = 12, 497 .table = mux_table_clk81, 498 }, 499 .hw.init = &(struct clk_init_data){ 500 .name = "mpeg_clk_sel", 501 .ops = &clk_regmap_mux_ro_ops, 502 /* 503 * FIXME bits 14:12 selects from 8 possible parents: 504 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 505 * fclk_div4, fclk_div3, fclk_div5 506 */ 507 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", 508 "fclk_div5" }, 509 .num_parents = 3, 510 }, 511 }; 512 513 static struct clk_regmap meson8b_mpeg_clk_div = { 514 .data = &(struct clk_regmap_div_data){ 515 .offset = HHI_MPEG_CLK_CNTL, 516 .shift = 0, 517 .width = 7, 518 }, 519 .hw.init = &(struct clk_init_data){ 520 .name = "mpeg_clk_div", 521 .ops = &clk_regmap_divider_ro_ops, 522 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 523 .num_parents = 1, 524 }, 525 }; 526 527 static struct clk_regmap meson8b_clk81 = { 528 .data = &(struct clk_regmap_gate_data){ 529 .offset = HHI_MPEG_CLK_CNTL, 530 .bit_idx = 7, 531 }, 532 .hw.init = &(struct clk_init_data){ 533 .name = "clk81", 534 .ops = &clk_regmap_gate_ops, 535 .parent_names = (const char *[]){ "mpeg_clk_div" }, 536 .num_parents = 1, 537 .flags = CLK_IS_CRITICAL, 538 }, 539 }; 540 541 static struct clk_regmap meson8b_cpu_in_sel = { 542 .data = &(struct clk_regmap_mux_data){ 543 .offset = HHI_SYS_CPU_CLK_CNTL0, 544 .mask = 0x1, 545 .shift = 0, 546 }, 547 .hw.init = &(struct clk_init_data){ 548 .name = "cpu_in_sel", 549 .ops = &clk_regmap_mux_ro_ops, 550 .parent_names = (const char *[]){ "xtal", "sys_pll" }, 551 .num_parents = 2, 552 .flags = (CLK_SET_RATE_PARENT | 553 CLK_SET_RATE_NO_REPARENT), 554 }, 555 }; 556 557 static struct clk_fixed_factor meson8b_cpu_div2 = { 558 .mult = 1, 559 .div = 2, 560 .hw.init = &(struct clk_init_data){ 561 .name = "cpu_div2", 562 .ops = &clk_fixed_factor_ops, 563 .parent_names = (const char *[]){ "cpu_in_sel" }, 564 .num_parents = 1, 565 .flags = CLK_SET_RATE_PARENT, 566 }, 567 }; 568 569 static struct clk_fixed_factor meson8b_cpu_div3 = { 570 .mult = 1, 571 .div = 3, 572 .hw.init = &(struct clk_init_data){ 573 .name = "cpu_div3", 574 .ops = &clk_fixed_factor_ops, 575 .parent_names = (const char *[]){ "cpu_in_sel" }, 576 .num_parents = 1, 577 .flags = CLK_SET_RATE_PARENT, 578 }, 579 }; 580 581 static const struct clk_div_table cpu_scale_table[] = { 582 { .val = 2, .div = 4 }, 583 { .val = 3, .div = 6 }, 584 { .val = 4, .div = 8 }, 585 { .val = 5, .div = 10 }, 586 { .val = 6, .div = 12 }, 587 { .val = 7, .div = 14 }, 588 { .val = 8, .div = 16 }, 589 { /* sentinel */ }, 590 }; 591 592 static struct clk_regmap meson8b_cpu_scale_div = { 593 .data = &(struct clk_regmap_div_data){ 594 .offset = HHI_SYS_CPU_CLK_CNTL1, 595 .shift = 20, 596 .width = 9, 597 .table = cpu_scale_table, 598 .flags = CLK_DIVIDER_ALLOW_ZERO, 599 }, 600 .hw.init = &(struct clk_init_data){ 601 .name = "cpu_scale_div", 602 .ops = &clk_regmap_divider_ro_ops, 603 .parent_names = (const char *[]){ "cpu_in_sel" }, 604 .num_parents = 1, 605 .flags = CLK_SET_RATE_PARENT, 606 }, 607 }; 608 609 static struct clk_regmap meson8b_cpu_scale_out_sel = { 610 .data = &(struct clk_regmap_mux_data){ 611 .offset = HHI_SYS_CPU_CLK_CNTL0, 612 .mask = 0x3, 613 .shift = 2, 614 }, 615 .hw.init = &(struct clk_init_data){ 616 .name = "cpu_scale_out_sel", 617 .ops = &clk_regmap_mux_ro_ops, 618 .parent_names = (const char *[]) { "cpu_in_sel", 619 "cpu_div2", 620 "cpu_div3", 621 "cpu_scale_div" }, 622 .num_parents = 4, 623 .flags = CLK_SET_RATE_PARENT, 624 }, 625 }; 626 627 static struct clk_regmap meson8b_cpu_clk = { 628 .data = &(struct clk_regmap_mux_data){ 629 .offset = HHI_SYS_CPU_CLK_CNTL0, 630 .mask = 0x1, 631 .shift = 7, 632 }, 633 .hw.init = &(struct clk_init_data){ 634 .name = "cpu_clk", 635 .ops = &clk_regmap_mux_ro_ops, 636 .parent_names = (const char *[]){ "xtal", 637 "cpu_scale_out_sel" }, 638 .num_parents = 2, 639 .flags = (CLK_SET_RATE_PARENT | 640 CLK_SET_RATE_NO_REPARENT), 641 }, 642 }; 643 644 static struct clk_regmap meson8b_nand_clk_sel = { 645 .data = &(struct clk_regmap_mux_data){ 646 .offset = HHI_NAND_CLK_CNTL, 647 .mask = 0x7, 648 .shift = 9, 649 .flags = CLK_MUX_ROUND_CLOSEST, 650 }, 651 .hw.init = &(struct clk_init_data){ 652 .name = "nand_clk_sel", 653 .ops = &clk_regmap_mux_ops, 654 /* FIXME all other parents are unknown: */ 655 .parent_names = (const char *[]){ "fclk_div4", "fclk_div3", 656 "fclk_div5", "fclk_div7", "xtal" }, 657 .num_parents = 5, 658 .flags = CLK_SET_RATE_PARENT, 659 }, 660 }; 661 662 static struct clk_regmap meson8b_nand_clk_div = { 663 .data = &(struct clk_regmap_div_data){ 664 .offset = HHI_NAND_CLK_CNTL, 665 .shift = 0, 666 .width = 7, 667 .flags = CLK_DIVIDER_ROUND_CLOSEST, 668 }, 669 .hw.init = &(struct clk_init_data){ 670 .name = "nand_clk_div", 671 .ops = &clk_regmap_divider_ops, 672 .parent_names = (const char *[]){ "nand_clk_sel" }, 673 .num_parents = 1, 674 .flags = CLK_SET_RATE_PARENT, 675 }, 676 }; 677 678 static struct clk_regmap meson8b_nand_clk_gate = { 679 .data = &(struct clk_regmap_gate_data){ 680 .offset = HHI_NAND_CLK_CNTL, 681 .bit_idx = 8, 682 }, 683 .hw.init = &(struct clk_init_data){ 684 .name = "nand_clk_gate", 685 .ops = &clk_regmap_gate_ops, 686 .parent_names = (const char *[]){ "nand_clk_div" }, 687 .num_parents = 1, 688 .flags = CLK_SET_RATE_PARENT, 689 }, 690 }; 691 692 /* Everything Else (EE) domain gates */ 693 694 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); 695 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1); 696 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5); 697 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6); 698 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7); 699 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8); 700 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9); 701 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10); 702 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11); 703 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12); 704 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13); 705 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14); 706 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15); 707 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16); 708 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17); 709 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18); 710 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19); 711 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23); 712 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30); 713 714 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2); 715 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3); 716 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4); 717 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6); 718 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7); 719 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8); 720 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9); 721 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10); 722 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11); 723 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12); 724 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13); 725 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14); 726 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15); 727 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16); 728 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20); 729 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21); 730 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22); 731 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23); 732 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24); 733 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25); 734 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26); 735 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28); 736 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29); 737 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30); 738 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31); 739 740 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1); 741 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 742 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 743 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4); 744 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 745 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 746 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11); 747 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12); 748 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15); 749 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22); 750 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25); 751 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 752 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29); 753 754 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1); 755 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2); 756 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3); 757 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4); 758 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8); 759 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9); 760 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10); 761 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14); 762 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16); 763 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20); 764 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21); 765 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22); 766 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 767 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25); 768 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26); 769 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31); 770 771 /* Always On (AO) domain gates */ 772 773 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0); 774 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1); 775 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2); 776 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3); 777 778 static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 779 .hws = { 780 [CLKID_XTAL] = &meson8b_xtal.hw, 781 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, 782 [CLKID_PLL_VID] = &meson8b_vid_pll.hw, 783 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, 784 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, 785 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, 786 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, 787 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, 788 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, 789 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, 790 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, 791 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, 792 [CLKID_CLK81] = &meson8b_clk81.hw, 793 [CLKID_DDR] = &meson8b_ddr.hw, 794 [CLKID_DOS] = &meson8b_dos.hw, 795 [CLKID_ISA] = &meson8b_isa.hw, 796 [CLKID_PL301] = &meson8b_pl301.hw, 797 [CLKID_PERIPHS] = &meson8b_periphs.hw, 798 [CLKID_SPICC] = &meson8b_spicc.hw, 799 [CLKID_I2C] = &meson8b_i2c.hw, 800 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, 801 [CLKID_SMART_CARD] = &meson8b_smart_card.hw, 802 [CLKID_RNG0] = &meson8b_rng0.hw, 803 [CLKID_UART0] = &meson8b_uart0.hw, 804 [CLKID_SDHC] = &meson8b_sdhc.hw, 805 [CLKID_STREAM] = &meson8b_stream.hw, 806 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, 807 [CLKID_SDIO] = &meson8b_sdio.hw, 808 [CLKID_ABUF] = &meson8b_abuf.hw, 809 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, 810 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, 811 [CLKID_SPI] = &meson8b_spi.hw, 812 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, 813 [CLKID_ETH] = &meson8b_eth.hw, 814 [CLKID_DEMUX] = &meson8b_demux.hw, 815 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, 816 [CLKID_IEC958] = &meson8b_iec958.hw, 817 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, 818 [CLKID_AMCLK] = &meson8b_amclk.hw, 819 [CLKID_AIFIFO2] = &meson8b_aififo2.hw, 820 [CLKID_MIXER] = &meson8b_mixer.hw, 821 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, 822 [CLKID_ADC] = &meson8b_adc.hw, 823 [CLKID_BLKMV] = &meson8b_blkmv.hw, 824 [CLKID_AIU] = &meson8b_aiu.hw, 825 [CLKID_UART1] = &meson8b_uart1.hw, 826 [CLKID_G2D] = &meson8b_g2d.hw, 827 [CLKID_USB0] = &meson8b_usb0.hw, 828 [CLKID_USB1] = &meson8b_usb1.hw, 829 [CLKID_RESET] = &meson8b_reset.hw, 830 [CLKID_NAND] = &meson8b_nand.hw, 831 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, 832 [CLKID_USB] = &meson8b_usb.hw, 833 [CLKID_VDIN1] = &meson8b_vdin1.hw, 834 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, 835 [CLKID_EFUSE] = &meson8b_efuse.hw, 836 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, 837 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, 838 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, 839 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, 840 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, 841 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, 842 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, 843 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, 844 [CLKID_DVIN] = &meson8b_dvin.hw, 845 [CLKID_UART2] = &meson8b_uart2.hw, 846 [CLKID_SANA] = &meson8b_sana.hw, 847 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, 848 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, 849 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, 850 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, 851 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, 852 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, 853 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, 854 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, 855 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, 856 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, 857 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, 858 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, 859 [CLKID_ENC480P] = &meson8b_enc480p.hw, 860 [CLKID_RNG1] = &meson8b_rng1.hw, 861 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, 862 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, 863 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, 864 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, 865 [CLKID_EDP] = &meson8b_edp.hw, 866 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, 867 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 868 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 869 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 870 [CLKID_MPLL0] = &meson8b_mpll0.hw, 871 [CLKID_MPLL1] = &meson8b_mpll1.hw, 872 [CLKID_MPLL2] = &meson8b_mpll2.hw, 873 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, 874 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, 875 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, 876 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, 877 [CLKID_CPU_DIV2] = &meson8b_cpu_div2.hw, 878 [CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw, 879 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, 880 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, 881 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, 882 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, 883 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, 884 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 885 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 886 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 887 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 888 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 889 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, 890 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, 891 [CLKID_PLL_VID_DCO] = &meson8b_vid_pll_dco.hw, 892 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, 893 [CLK_NR_CLKS] = NULL, 894 }, 895 .num = CLK_NR_CLKS, 896 }; 897 898 static struct clk_regmap *const meson8b_clk_regmaps[] = { 899 &meson8b_clk81, 900 &meson8b_ddr, 901 &meson8b_dos, 902 &meson8b_isa, 903 &meson8b_pl301, 904 &meson8b_periphs, 905 &meson8b_spicc, 906 &meson8b_i2c, 907 &meson8b_sar_adc, 908 &meson8b_smart_card, 909 &meson8b_rng0, 910 &meson8b_uart0, 911 &meson8b_sdhc, 912 &meson8b_stream, 913 &meson8b_async_fifo, 914 &meson8b_sdio, 915 &meson8b_abuf, 916 &meson8b_hiu_iface, 917 &meson8b_assist_misc, 918 &meson8b_spi, 919 &meson8b_i2s_spdif, 920 &meson8b_eth, 921 &meson8b_demux, 922 &meson8b_aiu_glue, 923 &meson8b_iec958, 924 &meson8b_i2s_out, 925 &meson8b_amclk, 926 &meson8b_aififo2, 927 &meson8b_mixer, 928 &meson8b_mixer_iface, 929 &meson8b_adc, 930 &meson8b_blkmv, 931 &meson8b_aiu, 932 &meson8b_uart1, 933 &meson8b_g2d, 934 &meson8b_usb0, 935 &meson8b_usb1, 936 &meson8b_reset, 937 &meson8b_nand, 938 &meson8b_dos_parser, 939 &meson8b_usb, 940 &meson8b_vdin1, 941 &meson8b_ahb_arb0, 942 &meson8b_efuse, 943 &meson8b_boot_rom, 944 &meson8b_ahb_data_bus, 945 &meson8b_ahb_ctrl_bus, 946 &meson8b_hdmi_intr_sync, 947 &meson8b_hdmi_pclk, 948 &meson8b_usb1_ddr_bridge, 949 &meson8b_usb0_ddr_bridge, 950 &meson8b_mmc_pclk, 951 &meson8b_dvin, 952 &meson8b_uart2, 953 &meson8b_sana, 954 &meson8b_vpu_intr, 955 &meson8b_sec_ahb_ahb3_bridge, 956 &meson8b_clk81_a9, 957 &meson8b_vclk2_venci0, 958 &meson8b_vclk2_venci1, 959 &meson8b_vclk2_vencp0, 960 &meson8b_vclk2_vencp1, 961 &meson8b_gclk_venci_int, 962 &meson8b_gclk_vencp_int, 963 &meson8b_dac_clk, 964 &meson8b_aoclk_gate, 965 &meson8b_iec958_gate, 966 &meson8b_enc480p, 967 &meson8b_rng1, 968 &meson8b_gclk_vencl_int, 969 &meson8b_vclk2_venclmcc, 970 &meson8b_vclk2_vencl, 971 &meson8b_vclk2_other, 972 &meson8b_edp, 973 &meson8b_ao_media_cpu, 974 &meson8b_ao_ahb_sram, 975 &meson8b_ao_ahb_bus, 976 &meson8b_ao_iface, 977 &meson8b_mpeg_clk_div, 978 &meson8b_mpeg_clk_sel, 979 &meson8b_mpll0, 980 &meson8b_mpll1, 981 &meson8b_mpll2, 982 &meson8b_mpll0_div, 983 &meson8b_mpll1_div, 984 &meson8b_mpll2_div, 985 &meson8b_fixed_pll, 986 &meson8b_vid_pll, 987 &meson8b_sys_pll, 988 &meson8b_cpu_in_sel, 989 &meson8b_cpu_scale_div, 990 &meson8b_cpu_scale_out_sel, 991 &meson8b_cpu_clk, 992 &meson8b_mpll_prediv, 993 &meson8b_fclk_div2, 994 &meson8b_fclk_div3, 995 &meson8b_fclk_div4, 996 &meson8b_fclk_div5, 997 &meson8b_fclk_div7, 998 &meson8b_nand_clk_sel, 999 &meson8b_nand_clk_div, 1000 &meson8b_nand_clk_gate, 1001 &meson8b_fixed_pll_dco, 1002 &meson8b_vid_pll_dco, 1003 &meson8b_sys_pll_dco, 1004 }; 1005 1006 static const struct meson8b_clk_reset_line { 1007 u32 reg; 1008 u8 bit_idx; 1009 } meson8b_clk_reset_bits[] = { 1010 [CLKC_RESET_L2_CACHE_SOFT_RESET] = { 1011 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30 1012 }, 1013 [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = { 1014 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29 1015 }, 1016 [CLKC_RESET_SCU_SOFT_RESET] = { 1017 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28 1018 }, 1019 [CLKC_RESET_CPU3_SOFT_RESET] = { 1020 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27 1021 }, 1022 [CLKC_RESET_CPU2_SOFT_RESET] = { 1023 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26 1024 }, 1025 [CLKC_RESET_CPU1_SOFT_RESET] = { 1026 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25 1027 }, 1028 [CLKC_RESET_CPU0_SOFT_RESET] = { 1029 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24 1030 }, 1031 [CLKC_RESET_A5_GLOBAL_RESET] = { 1032 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18 1033 }, 1034 [CLKC_RESET_A5_AXI_SOFT_RESET] = { 1035 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17 1036 }, 1037 [CLKC_RESET_A5_ABP_SOFT_RESET] = { 1038 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16 1039 }, 1040 [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = { 1041 .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30 1042 }, 1043 [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = { 1044 .reg = HHI_VID_CLK_CNTL, .bit_idx = 15 1045 }, 1046 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = { 1047 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7 1048 }, 1049 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = { 1050 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3 1051 }, 1052 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = { 1053 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1 1054 }, 1055 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = { 1056 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0 1057 }, 1058 }; 1059 1060 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev, 1061 unsigned long id, bool assert) 1062 { 1063 struct meson8b_clk_reset *meson8b_clk_reset = 1064 container_of(rcdev, struct meson8b_clk_reset, reset); 1065 unsigned long flags; 1066 const struct meson8b_clk_reset_line *reset; 1067 1068 if (id >= ARRAY_SIZE(meson8b_clk_reset_bits)) 1069 return -EINVAL; 1070 1071 reset = &meson8b_clk_reset_bits[id]; 1072 1073 spin_lock_irqsave(&meson_clk_lock, flags); 1074 1075 if (assert) 1076 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, 1077 BIT(reset->bit_idx), BIT(reset->bit_idx)); 1078 else 1079 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, 1080 BIT(reset->bit_idx), 0); 1081 1082 spin_unlock_irqrestore(&meson_clk_lock, flags); 1083 1084 return 0; 1085 } 1086 1087 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev, 1088 unsigned long id) 1089 { 1090 return meson8b_clk_reset_update(rcdev, id, true); 1091 } 1092 1093 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev, 1094 unsigned long id) 1095 { 1096 return meson8b_clk_reset_update(rcdev, id, false); 1097 } 1098 1099 static const struct reset_control_ops meson8b_clk_reset_ops = { 1100 .assert = meson8b_clk_reset_assert, 1101 .deassert = meson8b_clk_reset_deassert, 1102 }; 1103 1104 static const struct regmap_config clkc_regmap_config = { 1105 .reg_bits = 32, 1106 .val_bits = 32, 1107 .reg_stride = 4, 1108 }; 1109 1110 static void __init meson8b_clkc_init(struct device_node *np) 1111 { 1112 struct meson8b_clk_reset *rstc; 1113 void __iomem *clk_base; 1114 struct regmap *map; 1115 int i, ret; 1116 1117 /* Generic clocks, PLLs and some of the reset-bits */ 1118 clk_base = of_iomap(np, 1); 1119 if (!clk_base) { 1120 pr_err("%s: Unable to map clk base\n", __func__); 1121 return; 1122 } 1123 1124 map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config); 1125 if (IS_ERR(map)) 1126 return; 1127 1128 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); 1129 if (!rstc) 1130 return; 1131 1132 /* Reset Controller */ 1133 rstc->regmap = map; 1134 rstc->reset.ops = &meson8b_clk_reset_ops; 1135 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits); 1136 rstc->reset.of_node = np; 1137 ret = reset_controller_register(&rstc->reset); 1138 if (ret) { 1139 pr_err("%s: Failed to register clkc reset controller: %d\n", 1140 __func__, ret); 1141 return; 1142 } 1143 1144 /* Populate regmap for the regmap backed clocks */ 1145 for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++) 1146 meson8b_clk_regmaps[i]->map = map; 1147 1148 /* 1149 * register all clks 1150 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 1151 */ 1152 for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) { 1153 /* array might be sparse */ 1154 if (!meson8b_hw_onecell_data.hws[i]) 1155 continue; 1156 1157 ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[i]); 1158 if (ret) 1159 return; 1160 } 1161 1162 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, 1163 &meson8b_hw_onecell_data); 1164 if (ret) 1165 pr_err("%s: failed to register clock provider\n", __func__); 1166 } 1167 1168 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc", 1169 meson8b_clkc_init); 1170 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc", 1171 meson8b_clkc_init); 1172 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc", 1173 meson8b_clkc_init); 1174