1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 *
6 * Copyright (c) 2016 BayLibre, Inc.
7 * Michael Turquette <mturquette@baylibre.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/init.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of_address.h>
15 #include <linux/reset-controller.h>
16 #include <linux/slab.h>
17 #include <linux/regmap.h>
18
19 #include "meson8b.h"
20 #include "clk-regmap.h"
21 #include "meson-clkc-utils.h"
22 #include "clk-pll.h"
23 #include "clk-mpll.h"
24
25 #include <dt-bindings/clock/meson8b-clkc.h>
26 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
27
28 static DEFINE_SPINLOCK(meson_clk_lock);
29
30 struct meson8b_clk_reset {
31 struct reset_controller_dev reset;
32 struct regmap *regmap;
33 };
34
35 static const struct pll_params_table sys_pll_params_table[] = {
36 PLL_PARAMS(50, 1),
37 PLL_PARAMS(51, 1),
38 PLL_PARAMS(52, 1),
39 PLL_PARAMS(53, 1),
40 PLL_PARAMS(54, 1),
41 PLL_PARAMS(55, 1),
42 PLL_PARAMS(56, 1),
43 PLL_PARAMS(57, 1),
44 PLL_PARAMS(58, 1),
45 PLL_PARAMS(59, 1),
46 PLL_PARAMS(60, 1),
47 PLL_PARAMS(61, 1),
48 PLL_PARAMS(62, 1),
49 PLL_PARAMS(63, 1),
50 PLL_PARAMS(64, 1),
51 PLL_PARAMS(65, 1),
52 PLL_PARAMS(66, 1),
53 PLL_PARAMS(67, 1),
54 PLL_PARAMS(68, 1),
55 PLL_PARAMS(84, 1),
56 { /* sentinel */ },
57 };
58
59 static struct clk_regmap meson8b_fixed_pll_dco = {
60 .data = &(struct meson_clk_pll_data){
61 .en = {
62 .reg_off = HHI_MPLL_CNTL,
63 .shift = 30,
64 .width = 1,
65 },
66 .m = {
67 .reg_off = HHI_MPLL_CNTL,
68 .shift = 0,
69 .width = 9,
70 },
71 .n = {
72 .reg_off = HHI_MPLL_CNTL,
73 .shift = 9,
74 .width = 5,
75 },
76 .frac = {
77 .reg_off = HHI_MPLL_CNTL2,
78 .shift = 0,
79 .width = 12,
80 },
81 .l = {
82 .reg_off = HHI_MPLL_CNTL,
83 .shift = 31,
84 .width = 1,
85 },
86 .rst = {
87 .reg_off = HHI_MPLL_CNTL,
88 .shift = 29,
89 .width = 1,
90 },
91 },
92 .hw.init = &(struct clk_init_data){
93 .name = "fixed_pll_dco",
94 .ops = &meson_clk_pll_ro_ops,
95 .parent_data = &(const struct clk_parent_data) {
96 .fw_name = "xtal",
97 .name = "xtal",
98 .index = -1,
99 },
100 .num_parents = 1,
101 },
102 };
103
104 static struct clk_regmap meson8b_fixed_pll = {
105 .data = &(struct clk_regmap_div_data){
106 .offset = HHI_MPLL_CNTL,
107 .shift = 16,
108 .width = 2,
109 .flags = CLK_DIVIDER_POWER_OF_TWO,
110 },
111 .hw.init = &(struct clk_init_data){
112 .name = "fixed_pll",
113 .ops = &clk_regmap_divider_ro_ops,
114 .parent_hws = (const struct clk_hw *[]) {
115 &meson8b_fixed_pll_dco.hw
116 },
117 .num_parents = 1,
118 /*
119 * This clock won't ever change at runtime so
120 * CLK_SET_RATE_PARENT is not required
121 */
122 },
123 };
124
125 static struct clk_fixed_factor hdmi_pll_dco_in = {
126 .mult = 2,
127 .div = 1,
128 .hw.init = &(struct clk_init_data){
129 .name = "hdmi_pll_dco_in",
130 .ops = &clk_fixed_factor_ops,
131 .parent_data = &(const struct clk_parent_data) {
132 .fw_name = "xtal",
133 .index = -1,
134 },
135 .num_parents = 1,
136 },
137 };
138
139 /*
140 * Taken from the vendor driver for the 2970/2975MHz (both only differ in the
141 * FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8,
142 * Meson8b and Meson8m2. This doubles the input (or output - it's not clear
143 * which one but the result is the same) clock. The vendor driver additionally
144 * has the following comment about: "optimise HPLL VCO 2.97GHz performance".
145 */
146 static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = {
147 { .reg = HHI_VID_PLL_CNTL2, .def = 0x69c84000 },
148 { .reg = HHI_VID_PLL_CNTL3, .def = 0x8a46c023 },
149 { .reg = HHI_VID_PLL_CNTL4, .def = 0x4123b100 },
150 { .reg = HHI_VID_PLL_CNTL5, .def = 0x00012385 },
151 { .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 },
152 };
153
154 static const struct pll_params_table hdmi_pll_params_table[] = {
155 PLL_PARAMS(40, 1),
156 PLL_PARAMS(42, 1),
157 PLL_PARAMS(44, 1),
158 PLL_PARAMS(45, 1),
159 PLL_PARAMS(49, 1),
160 PLL_PARAMS(52, 1),
161 PLL_PARAMS(54, 1),
162 PLL_PARAMS(56, 1),
163 PLL_PARAMS(59, 1),
164 PLL_PARAMS(60, 1),
165 PLL_PARAMS(61, 1),
166 PLL_PARAMS(62, 1),
167 PLL_PARAMS(64, 1),
168 PLL_PARAMS(66, 1),
169 PLL_PARAMS(68, 1),
170 PLL_PARAMS(71, 1),
171 PLL_PARAMS(82, 1),
172 { /* sentinel */ }
173 };
174
175 static struct clk_regmap meson8b_hdmi_pll_dco = {
176 .data = &(struct meson_clk_pll_data){
177 .en = {
178 .reg_off = HHI_VID_PLL_CNTL,
179 .shift = 30,
180 .width = 1,
181 },
182 .m = {
183 .reg_off = HHI_VID_PLL_CNTL,
184 .shift = 0,
185 .width = 9,
186 },
187 .n = {
188 .reg_off = HHI_VID_PLL_CNTL,
189 .shift = 10,
190 .width = 5,
191 },
192 .frac = {
193 .reg_off = HHI_VID_PLL_CNTL2,
194 .shift = 0,
195 .width = 12,
196 },
197 .l = {
198 .reg_off = HHI_VID_PLL_CNTL,
199 .shift = 31,
200 .width = 1,
201 },
202 .rst = {
203 .reg_off = HHI_VID_PLL_CNTL,
204 .shift = 29,
205 .width = 1,
206 },
207 .table = hdmi_pll_params_table,
208 .init_regs = meson8b_hdmi_pll_init_regs,
209 .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs),
210 },
211 .hw.init = &(struct clk_init_data){
212 /* sometimes also called "HPLL" or "HPLL PLL" */
213 .name = "hdmi_pll_dco",
214 .ops = &meson_clk_pll_ops,
215 .parent_hws = (const struct clk_hw *[]) {
216 &hdmi_pll_dco_in.hw
217 },
218 .num_parents = 1,
219 },
220 };
221
222 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
223 .data = &(struct clk_regmap_div_data){
224 .offset = HHI_VID_PLL_CNTL,
225 .shift = 16,
226 .width = 2,
227 .flags = CLK_DIVIDER_POWER_OF_TWO,
228 },
229 .hw.init = &(struct clk_init_data){
230 .name = "hdmi_pll_lvds_out",
231 .ops = &clk_regmap_divider_ops,
232 .parent_hws = (const struct clk_hw *[]) {
233 &meson8b_hdmi_pll_dco.hw
234 },
235 .num_parents = 1,
236 .flags = CLK_SET_RATE_PARENT,
237 },
238 };
239
240 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
241 .data = &(struct clk_regmap_div_data){
242 .offset = HHI_VID_PLL_CNTL,
243 .shift = 18,
244 .width = 2,
245 .flags = CLK_DIVIDER_POWER_OF_TWO,
246 },
247 .hw.init = &(struct clk_init_data){
248 .name = "hdmi_pll_hdmi_out",
249 .ops = &clk_regmap_divider_ops,
250 .parent_hws = (const struct clk_hw *[]) {
251 &meson8b_hdmi_pll_dco.hw
252 },
253 .num_parents = 1,
254 .flags = CLK_SET_RATE_PARENT,
255 },
256 };
257
258 static struct clk_regmap meson8b_sys_pll_dco = {
259 .data = &(struct meson_clk_pll_data){
260 .en = {
261 .reg_off = HHI_SYS_PLL_CNTL,
262 .shift = 30,
263 .width = 1,
264 },
265 .m = {
266 .reg_off = HHI_SYS_PLL_CNTL,
267 .shift = 0,
268 .width = 9,
269 },
270 .n = {
271 .reg_off = HHI_SYS_PLL_CNTL,
272 .shift = 9,
273 .width = 5,
274 },
275 .l = {
276 .reg_off = HHI_SYS_PLL_CNTL,
277 .shift = 31,
278 .width = 1,
279 },
280 .rst = {
281 .reg_off = HHI_SYS_PLL_CNTL,
282 .shift = 29,
283 .width = 1,
284 },
285 .table = sys_pll_params_table,
286 },
287 .hw.init = &(struct clk_init_data){
288 .name = "sys_pll_dco",
289 .ops = &meson_clk_pll_ops,
290 .parent_data = &(const struct clk_parent_data) {
291 .fw_name = "xtal",
292 .name = "xtal",
293 .index = -1,
294 },
295 .num_parents = 1,
296 },
297 };
298
299 static struct clk_regmap meson8b_sys_pll = {
300 .data = &(struct clk_regmap_div_data){
301 .offset = HHI_SYS_PLL_CNTL,
302 .shift = 16,
303 .width = 2,
304 .flags = CLK_DIVIDER_POWER_OF_TWO,
305 },
306 .hw.init = &(struct clk_init_data){
307 .name = "sys_pll",
308 .ops = &clk_regmap_divider_ops,
309 .parent_hws = (const struct clk_hw *[]) {
310 &meson8b_sys_pll_dco.hw
311 },
312 .num_parents = 1,
313 .flags = CLK_SET_RATE_PARENT,
314 },
315 };
316
317 static struct clk_fixed_factor meson8b_fclk_div2_div = {
318 .mult = 1,
319 .div = 2,
320 .hw.init = &(struct clk_init_data){
321 .name = "fclk_div2_div",
322 .ops = &clk_fixed_factor_ops,
323 .parent_hws = (const struct clk_hw *[]) {
324 &meson8b_fixed_pll.hw
325 },
326 .num_parents = 1,
327 },
328 };
329
330 static struct clk_regmap meson8b_fclk_div2 = {
331 .data = &(struct clk_regmap_gate_data){
332 .offset = HHI_MPLL_CNTL6,
333 .bit_idx = 27,
334 },
335 .hw.init = &(struct clk_init_data){
336 .name = "fclk_div2",
337 .ops = &clk_regmap_gate_ops,
338 .parent_hws = (const struct clk_hw *[]) {
339 &meson8b_fclk_div2_div.hw
340 },
341 .num_parents = 1,
342 },
343 };
344
345 static struct clk_fixed_factor meson8b_fclk_div3_div = {
346 .mult = 1,
347 .div = 3,
348 .hw.init = &(struct clk_init_data){
349 .name = "fclk_div3_div",
350 .ops = &clk_fixed_factor_ops,
351 .parent_hws = (const struct clk_hw *[]) {
352 &meson8b_fixed_pll.hw
353 },
354 .num_parents = 1,
355 },
356 };
357
358 static struct clk_regmap meson8b_fclk_div3 = {
359 .data = &(struct clk_regmap_gate_data){
360 .offset = HHI_MPLL_CNTL6,
361 .bit_idx = 28,
362 },
363 .hw.init = &(struct clk_init_data){
364 .name = "fclk_div3",
365 .ops = &clk_regmap_gate_ops,
366 .parent_hws = (const struct clk_hw *[]) {
367 &meson8b_fclk_div3_div.hw
368 },
369 .num_parents = 1,
370 },
371 };
372
373 static struct clk_fixed_factor meson8b_fclk_div4_div = {
374 .mult = 1,
375 .div = 4,
376 .hw.init = &(struct clk_init_data){
377 .name = "fclk_div4_div",
378 .ops = &clk_fixed_factor_ops,
379 .parent_hws = (const struct clk_hw *[]) {
380 &meson8b_fixed_pll.hw
381 },
382 .num_parents = 1,
383 },
384 };
385
386 static struct clk_regmap meson8b_fclk_div4 = {
387 .data = &(struct clk_regmap_gate_data){
388 .offset = HHI_MPLL_CNTL6,
389 .bit_idx = 29,
390 },
391 .hw.init = &(struct clk_init_data){
392 .name = "fclk_div4",
393 .ops = &clk_regmap_gate_ops,
394 .parent_hws = (const struct clk_hw *[]) {
395 &meson8b_fclk_div4_div.hw
396 },
397 .num_parents = 1,
398 },
399 };
400
401 static struct clk_fixed_factor meson8b_fclk_div5_div = {
402 .mult = 1,
403 .div = 5,
404 .hw.init = &(struct clk_init_data){
405 .name = "fclk_div5_div",
406 .ops = &clk_fixed_factor_ops,
407 .parent_hws = (const struct clk_hw *[]) {
408 &meson8b_fixed_pll.hw
409 },
410 .num_parents = 1,
411 },
412 };
413
414 static struct clk_regmap meson8b_fclk_div5 = {
415 .data = &(struct clk_regmap_gate_data){
416 .offset = HHI_MPLL_CNTL6,
417 .bit_idx = 30,
418 },
419 .hw.init = &(struct clk_init_data){
420 .name = "fclk_div5",
421 .ops = &clk_regmap_gate_ops,
422 .parent_hws = (const struct clk_hw *[]) {
423 &meson8b_fclk_div5_div.hw
424 },
425 .num_parents = 1,
426 },
427 };
428
429 static struct clk_fixed_factor meson8b_fclk_div7_div = {
430 .mult = 1,
431 .div = 7,
432 .hw.init = &(struct clk_init_data){
433 .name = "fclk_div7_div",
434 .ops = &clk_fixed_factor_ops,
435 .parent_hws = (const struct clk_hw *[]) {
436 &meson8b_fixed_pll.hw
437 },
438 .num_parents = 1,
439 },
440 };
441
442 static struct clk_regmap meson8b_fclk_div7 = {
443 .data = &(struct clk_regmap_gate_data){
444 .offset = HHI_MPLL_CNTL6,
445 .bit_idx = 31,
446 },
447 .hw.init = &(struct clk_init_data){
448 .name = "fclk_div7",
449 .ops = &clk_regmap_gate_ops,
450 .parent_hws = (const struct clk_hw *[]) {
451 &meson8b_fclk_div7_div.hw
452 },
453 .num_parents = 1,
454 },
455 };
456
457 static struct clk_regmap meson8b_mpll_prediv = {
458 .data = &(struct clk_regmap_div_data){
459 .offset = HHI_MPLL_CNTL5,
460 .shift = 12,
461 .width = 1,
462 },
463 .hw.init = &(struct clk_init_data){
464 .name = "mpll_prediv",
465 .ops = &clk_regmap_divider_ro_ops,
466 .parent_hws = (const struct clk_hw *[]) {
467 &meson8b_fixed_pll.hw
468 },
469 .num_parents = 1,
470 },
471 };
472
473 static struct clk_regmap meson8b_mpll0_div = {
474 .data = &(struct meson_clk_mpll_data){
475 .sdm = {
476 .reg_off = HHI_MPLL_CNTL7,
477 .shift = 0,
478 .width = 14,
479 },
480 .sdm_en = {
481 .reg_off = HHI_MPLL_CNTL7,
482 .shift = 15,
483 .width = 1,
484 },
485 .n2 = {
486 .reg_off = HHI_MPLL_CNTL7,
487 .shift = 16,
488 .width = 9,
489 },
490 .ssen = {
491 .reg_off = HHI_MPLL_CNTL,
492 .shift = 25,
493 .width = 1,
494 },
495 .lock = &meson_clk_lock,
496 },
497 .hw.init = &(struct clk_init_data){
498 .name = "mpll0_div",
499 .ops = &meson_clk_mpll_ops,
500 .parent_hws = (const struct clk_hw *[]) {
501 &meson8b_mpll_prediv.hw
502 },
503 .num_parents = 1,
504 },
505 };
506
507 static struct clk_regmap meson8b_mpll0 = {
508 .data = &(struct clk_regmap_gate_data){
509 .offset = HHI_MPLL_CNTL7,
510 .bit_idx = 14,
511 },
512 .hw.init = &(struct clk_init_data){
513 .name = "mpll0",
514 .ops = &clk_regmap_gate_ops,
515 .parent_hws = (const struct clk_hw *[]) {
516 &meson8b_mpll0_div.hw
517 },
518 .num_parents = 1,
519 .flags = CLK_SET_RATE_PARENT,
520 },
521 };
522
523 static struct clk_regmap meson8b_mpll1_div = {
524 .data = &(struct meson_clk_mpll_data){
525 .sdm = {
526 .reg_off = HHI_MPLL_CNTL8,
527 .shift = 0,
528 .width = 14,
529 },
530 .sdm_en = {
531 .reg_off = HHI_MPLL_CNTL8,
532 .shift = 15,
533 .width = 1,
534 },
535 .n2 = {
536 .reg_off = HHI_MPLL_CNTL8,
537 .shift = 16,
538 .width = 9,
539 },
540 .lock = &meson_clk_lock,
541 },
542 .hw.init = &(struct clk_init_data){
543 .name = "mpll1_div",
544 .ops = &meson_clk_mpll_ops,
545 .parent_hws = (const struct clk_hw *[]) {
546 &meson8b_mpll_prediv.hw
547 },
548 .num_parents = 1,
549 },
550 };
551
552 static struct clk_regmap meson8b_mpll1 = {
553 .data = &(struct clk_regmap_gate_data){
554 .offset = HHI_MPLL_CNTL8,
555 .bit_idx = 14,
556 },
557 .hw.init = &(struct clk_init_data){
558 .name = "mpll1",
559 .ops = &clk_regmap_gate_ops,
560 .parent_hws = (const struct clk_hw *[]) {
561 &meson8b_mpll1_div.hw
562 },
563 .num_parents = 1,
564 .flags = CLK_SET_RATE_PARENT,
565 },
566 };
567
568 static struct clk_regmap meson8b_mpll2_div = {
569 .data = &(struct meson_clk_mpll_data){
570 .sdm = {
571 .reg_off = HHI_MPLL_CNTL9,
572 .shift = 0,
573 .width = 14,
574 },
575 .sdm_en = {
576 .reg_off = HHI_MPLL_CNTL9,
577 .shift = 15,
578 .width = 1,
579 },
580 .n2 = {
581 .reg_off = HHI_MPLL_CNTL9,
582 .shift = 16,
583 .width = 9,
584 },
585 .lock = &meson_clk_lock,
586 },
587 .hw.init = &(struct clk_init_data){
588 .name = "mpll2_div",
589 .ops = &meson_clk_mpll_ops,
590 .parent_hws = (const struct clk_hw *[]) {
591 &meson8b_mpll_prediv.hw
592 },
593 .num_parents = 1,
594 },
595 };
596
597 static struct clk_regmap meson8b_mpll2 = {
598 .data = &(struct clk_regmap_gate_data){
599 .offset = HHI_MPLL_CNTL9,
600 .bit_idx = 14,
601 },
602 .hw.init = &(struct clk_init_data){
603 .name = "mpll2",
604 .ops = &clk_regmap_gate_ops,
605 .parent_hws = (const struct clk_hw *[]) {
606 &meson8b_mpll2_div.hw
607 },
608 .num_parents = 1,
609 .flags = CLK_SET_RATE_PARENT,
610 },
611 };
612
613 static u32 mux_table_clk81[] = { 6, 5, 7 };
614 static struct clk_regmap meson8b_mpeg_clk_sel = {
615 .data = &(struct clk_regmap_mux_data){
616 .offset = HHI_MPEG_CLK_CNTL,
617 .mask = 0x7,
618 .shift = 12,
619 .table = mux_table_clk81,
620 },
621 .hw.init = &(struct clk_init_data){
622 .name = "mpeg_clk_sel",
623 .ops = &clk_regmap_mux_ro_ops,
624 /*
625 * FIXME bits 14:12 selects from 8 possible parents:
626 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
627 * fclk_div4, fclk_div3, fclk_div5
628 */
629 .parent_hws = (const struct clk_hw *[]) {
630 &meson8b_fclk_div3.hw,
631 &meson8b_fclk_div4.hw,
632 &meson8b_fclk_div5.hw,
633 },
634 .num_parents = 3,
635 },
636 };
637
638 static struct clk_regmap meson8b_mpeg_clk_div = {
639 .data = &(struct clk_regmap_div_data){
640 .offset = HHI_MPEG_CLK_CNTL,
641 .shift = 0,
642 .width = 7,
643 },
644 .hw.init = &(struct clk_init_data){
645 .name = "mpeg_clk_div",
646 .ops = &clk_regmap_divider_ro_ops,
647 .parent_hws = (const struct clk_hw *[]) {
648 &meson8b_mpeg_clk_sel.hw
649 },
650 .num_parents = 1,
651 },
652 };
653
654 static struct clk_regmap meson8b_clk81 = {
655 .data = &(struct clk_regmap_gate_data){
656 .offset = HHI_MPEG_CLK_CNTL,
657 .bit_idx = 7,
658 },
659 .hw.init = &(struct clk_init_data){
660 .name = "clk81",
661 .ops = &clk_regmap_gate_ops,
662 .parent_hws = (const struct clk_hw *[]) {
663 &meson8b_mpeg_clk_div.hw
664 },
665 .num_parents = 1,
666 .flags = CLK_IS_CRITICAL,
667 },
668 };
669
670 static struct clk_regmap meson8b_cpu_in_sel = {
671 .data = &(struct clk_regmap_mux_data){
672 .offset = HHI_SYS_CPU_CLK_CNTL0,
673 .mask = 0x1,
674 .shift = 0,
675 },
676 .hw.init = &(struct clk_init_data){
677 .name = "cpu_in_sel",
678 .ops = &clk_regmap_mux_ops,
679 .parent_data = (const struct clk_parent_data[]) {
680 { .fw_name = "xtal", .name = "xtal", .index = -1, },
681 { .hw = &meson8b_sys_pll.hw, },
682 },
683 .num_parents = 2,
684 .flags = (CLK_SET_RATE_PARENT |
685 CLK_SET_RATE_NO_REPARENT),
686 },
687 };
688
689 static struct clk_fixed_factor meson8b_cpu_in_div2 = {
690 .mult = 1,
691 .div = 2,
692 .hw.init = &(struct clk_init_data){
693 .name = "cpu_in_div2",
694 .ops = &clk_fixed_factor_ops,
695 .parent_hws = (const struct clk_hw *[]) {
696 &meson8b_cpu_in_sel.hw
697 },
698 .num_parents = 1,
699 .flags = CLK_SET_RATE_PARENT,
700 },
701 };
702
703 static struct clk_fixed_factor meson8b_cpu_in_div3 = {
704 .mult = 1,
705 .div = 3,
706 .hw.init = &(struct clk_init_data){
707 .name = "cpu_in_div3",
708 .ops = &clk_fixed_factor_ops,
709 .parent_hws = (const struct clk_hw *[]) {
710 &meson8b_cpu_in_sel.hw
711 },
712 .num_parents = 1,
713 .flags = CLK_SET_RATE_PARENT,
714 },
715 };
716
717 static const struct clk_div_table cpu_scale_table[] = {
718 { .val = 1, .div = 4 },
719 { .val = 2, .div = 6 },
720 { .val = 3, .div = 8 },
721 { .val = 4, .div = 10 },
722 { .val = 5, .div = 12 },
723 { .val = 6, .div = 14 },
724 { .val = 7, .div = 16 },
725 { .val = 8, .div = 18 },
726 { /* sentinel */ },
727 };
728
729 static struct clk_regmap meson8b_cpu_scale_div = {
730 .data = &(struct clk_regmap_div_data){
731 .offset = HHI_SYS_CPU_CLK_CNTL1,
732 .shift = 20,
733 .width = 10,
734 .table = cpu_scale_table,
735 .flags = CLK_DIVIDER_ALLOW_ZERO,
736 },
737 .hw.init = &(struct clk_init_data){
738 .name = "cpu_scale_div",
739 .ops = &clk_regmap_divider_ops,
740 .parent_hws = (const struct clk_hw *[]) {
741 &meson8b_cpu_in_sel.hw
742 },
743 .num_parents = 1,
744 .flags = CLK_SET_RATE_PARENT,
745 },
746 };
747
748 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
749 static struct clk_regmap meson8b_cpu_scale_out_sel = {
750 .data = &(struct clk_regmap_mux_data){
751 .offset = HHI_SYS_CPU_CLK_CNTL0,
752 .mask = 0x3,
753 .shift = 2,
754 .table = mux_table_cpu_scale_out_sel,
755 },
756 .hw.init = &(struct clk_init_data){
757 .name = "cpu_scale_out_sel",
758 .ops = &clk_regmap_mux_ops,
759 /*
760 * NOTE: We are skipping the parent with value 0x2 (which is
761 * meson8b_cpu_in_div3) because it results in a duty cycle of
762 * 33% which makes the system unstable and can result in a
763 * lockup of the whole system.
764 */
765 .parent_hws = (const struct clk_hw *[]) {
766 &meson8b_cpu_in_sel.hw,
767 &meson8b_cpu_in_div2.hw,
768 &meson8b_cpu_scale_div.hw,
769 },
770 .num_parents = 3,
771 .flags = CLK_SET_RATE_PARENT,
772 },
773 };
774
775 static struct clk_regmap meson8b_cpu_clk = {
776 .data = &(struct clk_regmap_mux_data){
777 .offset = HHI_SYS_CPU_CLK_CNTL0,
778 .mask = 0x1,
779 .shift = 7,
780 },
781 .hw.init = &(struct clk_init_data){
782 .name = "cpu_clk",
783 .ops = &clk_regmap_mux_ops,
784 .parent_data = (const struct clk_parent_data[]) {
785 { .fw_name = "xtal", .name = "xtal", .index = -1, },
786 { .hw = &meson8b_cpu_scale_out_sel.hw, },
787 },
788 .num_parents = 2,
789 .flags = (CLK_SET_RATE_PARENT |
790 CLK_SET_RATE_NO_REPARENT |
791 CLK_IS_CRITICAL),
792 },
793 };
794
795 static struct clk_regmap meson8b_nand_clk_sel = {
796 .data = &(struct clk_regmap_mux_data){
797 .offset = HHI_NAND_CLK_CNTL,
798 .mask = 0x7,
799 .shift = 9,
800 .flags = CLK_MUX_ROUND_CLOSEST,
801 },
802 .hw.init = &(struct clk_init_data){
803 .name = "nand_clk_sel",
804 .ops = &clk_regmap_mux_ops,
805 /* FIXME all other parents are unknown: */
806 .parent_data = (const struct clk_parent_data[]) {
807 { .hw = &meson8b_fclk_div4.hw, },
808 { .hw = &meson8b_fclk_div3.hw, },
809 { .hw = &meson8b_fclk_div5.hw, },
810 { .hw = &meson8b_fclk_div7.hw, },
811 { .fw_name = "xtal", .name = "xtal", .index = -1, },
812 },
813 .num_parents = 5,
814 .flags = CLK_SET_RATE_PARENT,
815 },
816 };
817
818 static struct clk_regmap meson8b_nand_clk_div = {
819 .data = &(struct clk_regmap_div_data){
820 .offset = HHI_NAND_CLK_CNTL,
821 .shift = 0,
822 .width = 7,
823 .flags = CLK_DIVIDER_ROUND_CLOSEST,
824 },
825 .hw.init = &(struct clk_init_data){
826 .name = "nand_clk_div",
827 .ops = &clk_regmap_divider_ops,
828 .parent_hws = (const struct clk_hw *[]) {
829 &meson8b_nand_clk_sel.hw
830 },
831 .num_parents = 1,
832 .flags = CLK_SET_RATE_PARENT,
833 },
834 };
835
836 static struct clk_regmap meson8b_nand_clk_gate = {
837 .data = &(struct clk_regmap_gate_data){
838 .offset = HHI_NAND_CLK_CNTL,
839 .bit_idx = 8,
840 },
841 .hw.init = &(struct clk_init_data){
842 .name = "nand_clk_gate",
843 .ops = &clk_regmap_gate_ops,
844 .parent_hws = (const struct clk_hw *[]) {
845 &meson8b_nand_clk_div.hw
846 },
847 .num_parents = 1,
848 .flags = CLK_SET_RATE_PARENT,
849 },
850 };
851
852 static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
853 .mult = 1,
854 .div = 2,
855 .hw.init = &(struct clk_init_data){
856 .name = "cpu_clk_div2",
857 .ops = &clk_fixed_factor_ops,
858 .parent_hws = (const struct clk_hw *[]) {
859 &meson8b_cpu_clk.hw
860 },
861 .num_parents = 1,
862 },
863 };
864
865 static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
866 .mult = 1,
867 .div = 3,
868 .hw.init = &(struct clk_init_data){
869 .name = "cpu_clk_div3",
870 .ops = &clk_fixed_factor_ops,
871 .parent_hws = (const struct clk_hw *[]) {
872 &meson8b_cpu_clk.hw
873 },
874 .num_parents = 1,
875 },
876 };
877
878 static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
879 .mult = 1,
880 .div = 4,
881 .hw.init = &(struct clk_init_data){
882 .name = "cpu_clk_div4",
883 .ops = &clk_fixed_factor_ops,
884 .parent_hws = (const struct clk_hw *[]) {
885 &meson8b_cpu_clk.hw
886 },
887 .num_parents = 1,
888 },
889 };
890
891 static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
892 .mult = 1,
893 .div = 5,
894 .hw.init = &(struct clk_init_data){
895 .name = "cpu_clk_div5",
896 .ops = &clk_fixed_factor_ops,
897 .parent_hws = (const struct clk_hw *[]) {
898 &meson8b_cpu_clk.hw
899 },
900 .num_parents = 1,
901 },
902 };
903
904 static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
905 .mult = 1,
906 .div = 6,
907 .hw.init = &(struct clk_init_data){
908 .name = "cpu_clk_div6",
909 .ops = &clk_fixed_factor_ops,
910 .parent_hws = (const struct clk_hw *[]) {
911 &meson8b_cpu_clk.hw
912 },
913 .num_parents = 1,
914 },
915 };
916
917 static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
918 .mult = 1,
919 .div = 7,
920 .hw.init = &(struct clk_init_data){
921 .name = "cpu_clk_div7",
922 .ops = &clk_fixed_factor_ops,
923 .parent_hws = (const struct clk_hw *[]) {
924 &meson8b_cpu_clk.hw
925 },
926 .num_parents = 1,
927 },
928 };
929
930 static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
931 .mult = 1,
932 .div = 8,
933 .hw.init = &(struct clk_init_data){
934 .name = "cpu_clk_div8",
935 .ops = &clk_fixed_factor_ops,
936 .parent_hws = (const struct clk_hw *[]) {
937 &meson8b_cpu_clk.hw
938 },
939 .num_parents = 1,
940 },
941 };
942
943 static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
944 static struct clk_regmap meson8b_apb_clk_sel = {
945 .data = &(struct clk_regmap_mux_data){
946 .offset = HHI_SYS_CPU_CLK_CNTL1,
947 .mask = 0x7,
948 .shift = 3,
949 .table = mux_table_apb,
950 },
951 .hw.init = &(struct clk_init_data){
952 .name = "apb_clk_sel",
953 .ops = &clk_regmap_mux_ops,
954 .parent_hws = (const struct clk_hw *[]) {
955 &meson8b_cpu_clk_div2.hw,
956 &meson8b_cpu_clk_div3.hw,
957 &meson8b_cpu_clk_div4.hw,
958 &meson8b_cpu_clk_div5.hw,
959 &meson8b_cpu_clk_div6.hw,
960 &meson8b_cpu_clk_div7.hw,
961 &meson8b_cpu_clk_div8.hw,
962 },
963 .num_parents = 7,
964 },
965 };
966
967 static struct clk_regmap meson8b_apb_clk_gate = {
968 .data = &(struct clk_regmap_gate_data){
969 .offset = HHI_SYS_CPU_CLK_CNTL1,
970 .bit_idx = 16,
971 .flags = CLK_GATE_SET_TO_DISABLE,
972 },
973 .hw.init = &(struct clk_init_data){
974 .name = "apb_clk_dis",
975 .ops = &clk_regmap_gate_ro_ops,
976 .parent_hws = (const struct clk_hw *[]) {
977 &meson8b_apb_clk_sel.hw
978 },
979 .num_parents = 1,
980 .flags = CLK_SET_RATE_PARENT,
981 },
982 };
983
984 static struct clk_regmap meson8b_periph_clk_sel = {
985 .data = &(struct clk_regmap_mux_data){
986 .offset = HHI_SYS_CPU_CLK_CNTL1,
987 .mask = 0x7,
988 .shift = 6,
989 },
990 .hw.init = &(struct clk_init_data){
991 .name = "periph_clk_sel",
992 .ops = &clk_regmap_mux_ops,
993 .parent_hws = (const struct clk_hw *[]) {
994 &meson8b_cpu_clk_div2.hw,
995 &meson8b_cpu_clk_div3.hw,
996 &meson8b_cpu_clk_div4.hw,
997 &meson8b_cpu_clk_div5.hw,
998 &meson8b_cpu_clk_div6.hw,
999 &meson8b_cpu_clk_div7.hw,
1000 &meson8b_cpu_clk_div8.hw,
1001 },
1002 .num_parents = 7,
1003 },
1004 };
1005
1006 static struct clk_regmap meson8b_periph_clk_gate = {
1007 .data = &(struct clk_regmap_gate_data){
1008 .offset = HHI_SYS_CPU_CLK_CNTL1,
1009 .bit_idx = 17,
1010 .flags = CLK_GATE_SET_TO_DISABLE,
1011 },
1012 .hw.init = &(struct clk_init_data){
1013 .name = "periph_clk_dis",
1014 .ops = &clk_regmap_gate_ro_ops,
1015 .parent_hws = (const struct clk_hw *[]) {
1016 &meson8b_periph_clk_sel.hw
1017 },
1018 .num_parents = 1,
1019 .flags = CLK_SET_RATE_PARENT,
1020 },
1021 };
1022
1023 static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
1024 static struct clk_regmap meson8b_axi_clk_sel = {
1025 .data = &(struct clk_regmap_mux_data){
1026 .offset = HHI_SYS_CPU_CLK_CNTL1,
1027 .mask = 0x7,
1028 .shift = 9,
1029 .table = mux_table_axi,
1030 },
1031 .hw.init = &(struct clk_init_data){
1032 .name = "axi_clk_sel",
1033 .ops = &clk_regmap_mux_ops,
1034 .parent_hws = (const struct clk_hw *[]) {
1035 &meson8b_cpu_clk_div2.hw,
1036 &meson8b_cpu_clk_div3.hw,
1037 &meson8b_cpu_clk_div4.hw,
1038 &meson8b_cpu_clk_div5.hw,
1039 &meson8b_cpu_clk_div6.hw,
1040 &meson8b_cpu_clk_div7.hw,
1041 &meson8b_cpu_clk_div8.hw,
1042 },
1043 .num_parents = 7,
1044 },
1045 };
1046
1047 static struct clk_regmap meson8b_axi_clk_gate = {
1048 .data = &(struct clk_regmap_gate_data){
1049 .offset = HHI_SYS_CPU_CLK_CNTL1,
1050 .bit_idx = 18,
1051 .flags = CLK_GATE_SET_TO_DISABLE,
1052 },
1053 .hw.init = &(struct clk_init_data){
1054 .name = "axi_clk_dis",
1055 .ops = &clk_regmap_gate_ro_ops,
1056 .parent_hws = (const struct clk_hw *[]) {
1057 &meson8b_axi_clk_sel.hw
1058 },
1059 .num_parents = 1,
1060 .flags = CLK_SET_RATE_PARENT,
1061 },
1062 };
1063
1064 static struct clk_regmap meson8b_l2_dram_clk_sel = {
1065 .data = &(struct clk_regmap_mux_data){
1066 .offset = HHI_SYS_CPU_CLK_CNTL1,
1067 .mask = 0x7,
1068 .shift = 12,
1069 },
1070 .hw.init = &(struct clk_init_data){
1071 .name = "l2_dram_clk_sel",
1072 .ops = &clk_regmap_mux_ops,
1073 .parent_hws = (const struct clk_hw *[]) {
1074 &meson8b_cpu_clk_div2.hw,
1075 &meson8b_cpu_clk_div3.hw,
1076 &meson8b_cpu_clk_div4.hw,
1077 &meson8b_cpu_clk_div5.hw,
1078 &meson8b_cpu_clk_div6.hw,
1079 &meson8b_cpu_clk_div7.hw,
1080 &meson8b_cpu_clk_div8.hw,
1081 },
1082 .num_parents = 7,
1083 },
1084 };
1085
1086 static struct clk_regmap meson8b_l2_dram_clk_gate = {
1087 .data = &(struct clk_regmap_gate_data){
1088 .offset = HHI_SYS_CPU_CLK_CNTL1,
1089 .bit_idx = 19,
1090 .flags = CLK_GATE_SET_TO_DISABLE,
1091 },
1092 .hw.init = &(struct clk_init_data){
1093 .name = "l2_dram_clk_dis",
1094 .ops = &clk_regmap_gate_ro_ops,
1095 .parent_hws = (const struct clk_hw *[]) {
1096 &meson8b_l2_dram_clk_sel.hw
1097 },
1098 .num_parents = 1,
1099 .flags = CLK_SET_RATE_PARENT,
1100 },
1101 };
1102
1103 /* also called LVDS_CLK_EN */
1104 static struct clk_regmap meson8b_vid_pll_lvds_en = {
1105 .data = &(struct clk_regmap_gate_data){
1106 .offset = HHI_VID_DIVIDER_CNTL,
1107 .bit_idx = 11,
1108 },
1109 .hw.init = &(struct clk_init_data){
1110 .name = "vid_pll_lvds_en",
1111 .ops = &clk_regmap_gate_ops,
1112 .parent_hws = (const struct clk_hw *[]) {
1113 &meson8b_hdmi_pll_lvds_out.hw
1114 },
1115 .num_parents = 1,
1116 .flags = CLK_SET_RATE_PARENT,
1117 },
1118 };
1119
1120 static struct clk_regmap meson8b_vid_pll_in_sel = {
1121 .data = &(struct clk_regmap_mux_data){
1122 .offset = HHI_VID_DIVIDER_CNTL,
1123 .mask = 0x1,
1124 .shift = 15,
1125 },
1126 .hw.init = &(struct clk_init_data){
1127 .name = "vid_pll_in_sel",
1128 .ops = &clk_regmap_mux_ops,
1129 /*
1130 * TODO: depending on the SoC there is also a second parent:
1131 * Meson8: unknown
1132 * Meson8b: hdmi_pll_dco
1133 * Meson8m2: vid2_pll
1134 */
1135 .parent_hws = (const struct clk_hw *[]) {
1136 &meson8b_vid_pll_lvds_en.hw
1137 },
1138 .num_parents = 1,
1139 .flags = CLK_SET_RATE_PARENT,
1140 },
1141 };
1142
1143 static struct clk_regmap meson8b_vid_pll_in_en = {
1144 .data = &(struct clk_regmap_gate_data){
1145 .offset = HHI_VID_DIVIDER_CNTL,
1146 .bit_idx = 16,
1147 },
1148 .hw.init = &(struct clk_init_data){
1149 .name = "vid_pll_in_en",
1150 .ops = &clk_regmap_gate_ops,
1151 .parent_hws = (const struct clk_hw *[]) {
1152 &meson8b_vid_pll_in_sel.hw
1153 },
1154 .num_parents = 1,
1155 .flags = CLK_SET_RATE_PARENT,
1156 },
1157 };
1158
1159 static struct clk_regmap meson8b_vid_pll_pre_div = {
1160 .data = &(struct clk_regmap_div_data){
1161 .offset = HHI_VID_DIVIDER_CNTL,
1162 .shift = 4,
1163 .width = 3,
1164 },
1165 .hw.init = &(struct clk_init_data){
1166 .name = "vid_pll_pre_div",
1167 .ops = &clk_regmap_divider_ops,
1168 .parent_hws = (const struct clk_hw *[]) {
1169 &meson8b_vid_pll_in_en.hw
1170 },
1171 .num_parents = 1,
1172 .flags = CLK_SET_RATE_PARENT,
1173 },
1174 };
1175
1176 static struct clk_regmap meson8b_vid_pll_post_div = {
1177 .data = &(struct clk_regmap_div_data){
1178 .offset = HHI_VID_DIVIDER_CNTL,
1179 .shift = 12,
1180 .width = 3,
1181 },
1182 .hw.init = &(struct clk_init_data){
1183 .name = "vid_pll_post_div",
1184 .ops = &clk_regmap_divider_ops,
1185 .parent_hws = (const struct clk_hw *[]) {
1186 &meson8b_vid_pll_pre_div.hw
1187 },
1188 .num_parents = 1,
1189 .flags = CLK_SET_RATE_PARENT,
1190 },
1191 };
1192
1193 static struct clk_regmap meson8b_vid_pll = {
1194 .data = &(struct clk_regmap_mux_data){
1195 .offset = HHI_VID_DIVIDER_CNTL,
1196 .mask = 0x3,
1197 .shift = 8,
1198 },
1199 .hw.init = &(struct clk_init_data){
1200 .name = "vid_pll",
1201 .ops = &clk_regmap_mux_ops,
1202 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
1203 .parent_hws = (const struct clk_hw *[]) {
1204 &meson8b_vid_pll_pre_div.hw,
1205 &meson8b_vid_pll_post_div.hw,
1206 },
1207 .num_parents = 2,
1208 .flags = CLK_SET_RATE_PARENT,
1209 },
1210 };
1211
1212 static struct clk_regmap meson8b_vid_pll_final_div = {
1213 .data = &(struct clk_regmap_div_data){
1214 .offset = HHI_VID_CLK_DIV,
1215 .shift = 0,
1216 .width = 8,
1217 },
1218 .hw.init = &(struct clk_init_data){
1219 .name = "vid_pll_final_div",
1220 .ops = &clk_regmap_divider_ops,
1221 .parent_hws = (const struct clk_hw *[]) {
1222 &meson8b_vid_pll.hw
1223 },
1224 .num_parents = 1,
1225 .flags = CLK_SET_RATE_PARENT,
1226 },
1227 };
1228
1229 static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
1230 &meson8b_vid_pll_final_div.hw,
1231 &meson8b_fclk_div4.hw,
1232 &meson8b_fclk_div3.hw,
1233 &meson8b_fclk_div5.hw,
1234 &meson8b_vid_pll_final_div.hw,
1235 &meson8b_fclk_div7.hw,
1236 &meson8b_mpll1.hw,
1237 };
1238
1239 static struct clk_regmap meson8b_vclk_in_sel = {
1240 .data = &(struct clk_regmap_mux_data){
1241 .offset = HHI_VID_CLK_CNTL,
1242 .mask = 0x7,
1243 .shift = 16,
1244 },
1245 .hw.init = &(struct clk_init_data){
1246 .name = "vclk_in_sel",
1247 .ops = &clk_regmap_mux_ops,
1248 .parent_hws = meson8b_vclk_mux_parent_hws,
1249 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1250 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1251 },
1252 };
1253
1254 static struct clk_regmap meson8b_vclk_in_en = {
1255 .data = &(struct clk_regmap_gate_data){
1256 .offset = HHI_VID_CLK_DIV,
1257 .bit_idx = 16,
1258 },
1259 .hw.init = &(struct clk_init_data){
1260 .name = "vclk_in_en",
1261 .ops = &clk_regmap_gate_ops,
1262 .parent_hws = (const struct clk_hw *[]) {
1263 &meson8b_vclk_in_sel.hw
1264 },
1265 .num_parents = 1,
1266 .flags = CLK_SET_RATE_PARENT,
1267 },
1268 };
1269
1270 static struct clk_regmap meson8b_vclk_en = {
1271 .data = &(struct clk_regmap_gate_data){
1272 .offset = HHI_VID_CLK_CNTL,
1273 .bit_idx = 19,
1274 },
1275 .hw.init = &(struct clk_init_data){
1276 .name = "vclk_en",
1277 .ops = &clk_regmap_gate_ops,
1278 .parent_hws = (const struct clk_hw *[]) {
1279 &meson8b_vclk_in_en.hw
1280 },
1281 .num_parents = 1,
1282 .flags = CLK_SET_RATE_PARENT,
1283 },
1284 };
1285
1286 static struct clk_regmap meson8b_vclk_div1_gate = {
1287 .data = &(struct clk_regmap_gate_data){
1288 .offset = HHI_VID_CLK_CNTL,
1289 .bit_idx = 0,
1290 },
1291 .hw.init = &(struct clk_init_data){
1292 .name = "vclk_div1_en",
1293 .ops = &clk_regmap_gate_ops,
1294 .parent_hws = (const struct clk_hw *[]) {
1295 &meson8b_vclk_en.hw
1296 },
1297 .num_parents = 1,
1298 .flags = CLK_SET_RATE_PARENT,
1299 },
1300 };
1301
1302 static struct clk_fixed_factor meson8b_vclk_div2_div = {
1303 .mult = 1,
1304 .div = 2,
1305 .hw.init = &(struct clk_init_data){
1306 .name = "vclk_div2",
1307 .ops = &clk_fixed_factor_ops,
1308 .parent_hws = (const struct clk_hw *[]) {
1309 &meson8b_vclk_en.hw
1310 },
1311 .num_parents = 1,
1312 .flags = CLK_SET_RATE_PARENT,
1313 }
1314 };
1315
1316 static struct clk_regmap meson8b_vclk_div2_div_gate = {
1317 .data = &(struct clk_regmap_gate_data){
1318 .offset = HHI_VID_CLK_CNTL,
1319 .bit_idx = 1,
1320 },
1321 .hw.init = &(struct clk_init_data){
1322 .name = "vclk_div2_en",
1323 .ops = &clk_regmap_gate_ops,
1324 .parent_hws = (const struct clk_hw *[]) {
1325 &meson8b_vclk_div2_div.hw
1326 },
1327 .num_parents = 1,
1328 .flags = CLK_SET_RATE_PARENT,
1329 },
1330 };
1331
1332 static struct clk_fixed_factor meson8b_vclk_div4_div = {
1333 .mult = 1,
1334 .div = 4,
1335 .hw.init = &(struct clk_init_data){
1336 .name = "vclk_div4",
1337 .ops = &clk_fixed_factor_ops,
1338 .parent_hws = (const struct clk_hw *[]) {
1339 &meson8b_vclk_en.hw
1340 },
1341 .num_parents = 1,
1342 .flags = CLK_SET_RATE_PARENT,
1343 }
1344 };
1345
1346 static struct clk_regmap meson8b_vclk_div4_div_gate = {
1347 .data = &(struct clk_regmap_gate_data){
1348 .offset = HHI_VID_CLK_CNTL,
1349 .bit_idx = 2,
1350 },
1351 .hw.init = &(struct clk_init_data){
1352 .name = "vclk_div4_en",
1353 .ops = &clk_regmap_gate_ops,
1354 .parent_hws = (const struct clk_hw *[]) {
1355 &meson8b_vclk_div4_div.hw
1356 },
1357 .num_parents = 1,
1358 .flags = CLK_SET_RATE_PARENT,
1359 },
1360 };
1361
1362 static struct clk_fixed_factor meson8b_vclk_div6_div = {
1363 .mult = 1,
1364 .div = 6,
1365 .hw.init = &(struct clk_init_data){
1366 .name = "vclk_div6",
1367 .ops = &clk_fixed_factor_ops,
1368 .parent_hws = (const struct clk_hw *[]) {
1369 &meson8b_vclk_en.hw
1370 },
1371 .num_parents = 1,
1372 .flags = CLK_SET_RATE_PARENT,
1373 }
1374 };
1375
1376 static struct clk_regmap meson8b_vclk_div6_div_gate = {
1377 .data = &(struct clk_regmap_gate_data){
1378 .offset = HHI_VID_CLK_CNTL,
1379 .bit_idx = 3,
1380 },
1381 .hw.init = &(struct clk_init_data){
1382 .name = "vclk_div6_en",
1383 .ops = &clk_regmap_gate_ops,
1384 .parent_hws = (const struct clk_hw *[]) {
1385 &meson8b_vclk_div6_div.hw
1386 },
1387 .num_parents = 1,
1388 .flags = CLK_SET_RATE_PARENT,
1389 },
1390 };
1391
1392 static struct clk_fixed_factor meson8b_vclk_div12_div = {
1393 .mult = 1,
1394 .div = 12,
1395 .hw.init = &(struct clk_init_data){
1396 .name = "vclk_div12",
1397 .ops = &clk_fixed_factor_ops,
1398 .parent_hws = (const struct clk_hw *[]) {
1399 &meson8b_vclk_en.hw
1400 },
1401 .num_parents = 1,
1402 .flags = CLK_SET_RATE_PARENT,
1403 }
1404 };
1405
1406 static struct clk_regmap meson8b_vclk_div12_div_gate = {
1407 .data = &(struct clk_regmap_gate_data){
1408 .offset = HHI_VID_CLK_CNTL,
1409 .bit_idx = 4,
1410 },
1411 .hw.init = &(struct clk_init_data){
1412 .name = "vclk_div12_en",
1413 .ops = &clk_regmap_gate_ops,
1414 .parent_hws = (const struct clk_hw *[]) {
1415 &meson8b_vclk_div12_div.hw
1416 },
1417 .num_parents = 1,
1418 .flags = CLK_SET_RATE_PARENT,
1419 },
1420 };
1421
1422 static struct clk_regmap meson8b_vclk2_in_sel = {
1423 .data = &(struct clk_regmap_mux_data){
1424 .offset = HHI_VIID_CLK_CNTL,
1425 .mask = 0x7,
1426 .shift = 16,
1427 },
1428 .hw.init = &(struct clk_init_data){
1429 .name = "vclk2_in_sel",
1430 .ops = &clk_regmap_mux_ops,
1431 .parent_hws = meson8b_vclk_mux_parent_hws,
1432 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1433 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1434 },
1435 };
1436
1437 static struct clk_regmap meson8b_vclk2_clk_in_en = {
1438 .data = &(struct clk_regmap_gate_data){
1439 .offset = HHI_VIID_CLK_DIV,
1440 .bit_idx = 16,
1441 },
1442 .hw.init = &(struct clk_init_data){
1443 .name = "vclk2_in_en",
1444 .ops = &clk_regmap_gate_ops,
1445 .parent_hws = (const struct clk_hw *[]) {
1446 &meson8b_vclk2_in_sel.hw
1447 },
1448 .num_parents = 1,
1449 .flags = CLK_SET_RATE_PARENT,
1450 },
1451 };
1452
1453 static struct clk_regmap meson8b_vclk2_clk_en = {
1454 .data = &(struct clk_regmap_gate_data){
1455 .offset = HHI_VIID_CLK_DIV,
1456 .bit_idx = 19,
1457 },
1458 .hw.init = &(struct clk_init_data){
1459 .name = "vclk2_en",
1460 .ops = &clk_regmap_gate_ops,
1461 .parent_hws = (const struct clk_hw *[]) {
1462 &meson8b_vclk2_clk_in_en.hw
1463 },
1464 .num_parents = 1,
1465 .flags = CLK_SET_RATE_PARENT,
1466 },
1467 };
1468
1469 static struct clk_regmap meson8b_vclk2_div1_gate = {
1470 .data = &(struct clk_regmap_gate_data){
1471 .offset = HHI_VIID_CLK_DIV,
1472 .bit_idx = 0,
1473 },
1474 .hw.init = &(struct clk_init_data){
1475 .name = "vclk2_div1_en",
1476 .ops = &clk_regmap_gate_ops,
1477 .parent_hws = (const struct clk_hw *[]) {
1478 &meson8b_vclk2_clk_en.hw
1479 },
1480 .num_parents = 1,
1481 .flags = CLK_SET_RATE_PARENT,
1482 },
1483 };
1484
1485 static struct clk_fixed_factor meson8b_vclk2_div2_div = {
1486 .mult = 1,
1487 .div = 2,
1488 .hw.init = &(struct clk_init_data){
1489 .name = "vclk2_div2",
1490 .ops = &clk_fixed_factor_ops,
1491 .parent_hws = (const struct clk_hw *[]) {
1492 &meson8b_vclk2_clk_en.hw
1493 },
1494 .num_parents = 1,
1495 .flags = CLK_SET_RATE_PARENT,
1496 }
1497 };
1498
1499 static struct clk_regmap meson8b_vclk2_div2_div_gate = {
1500 .data = &(struct clk_regmap_gate_data){
1501 .offset = HHI_VIID_CLK_DIV,
1502 .bit_idx = 1,
1503 },
1504 .hw.init = &(struct clk_init_data){
1505 .name = "vclk2_div2_en",
1506 .ops = &clk_regmap_gate_ops,
1507 .parent_hws = (const struct clk_hw *[]) {
1508 &meson8b_vclk2_div2_div.hw
1509 },
1510 .num_parents = 1,
1511 .flags = CLK_SET_RATE_PARENT,
1512 },
1513 };
1514
1515 static struct clk_fixed_factor meson8b_vclk2_div4_div = {
1516 .mult = 1,
1517 .div = 4,
1518 .hw.init = &(struct clk_init_data){
1519 .name = "vclk2_div4",
1520 .ops = &clk_fixed_factor_ops,
1521 .parent_hws = (const struct clk_hw *[]) {
1522 &meson8b_vclk2_clk_en.hw
1523 },
1524 .num_parents = 1,
1525 .flags = CLK_SET_RATE_PARENT,
1526 }
1527 };
1528
1529 static struct clk_regmap meson8b_vclk2_div4_div_gate = {
1530 .data = &(struct clk_regmap_gate_data){
1531 .offset = HHI_VIID_CLK_DIV,
1532 .bit_idx = 2,
1533 },
1534 .hw.init = &(struct clk_init_data){
1535 .name = "vclk2_div4_en",
1536 .ops = &clk_regmap_gate_ops,
1537 .parent_hws = (const struct clk_hw *[]) {
1538 &meson8b_vclk2_div4_div.hw
1539 },
1540 .num_parents = 1,
1541 .flags = CLK_SET_RATE_PARENT,
1542 },
1543 };
1544
1545 static struct clk_fixed_factor meson8b_vclk2_div6_div = {
1546 .mult = 1,
1547 .div = 6,
1548 .hw.init = &(struct clk_init_data){
1549 .name = "vclk2_div6",
1550 .ops = &clk_fixed_factor_ops,
1551 .parent_hws = (const struct clk_hw *[]) {
1552 &meson8b_vclk2_clk_en.hw
1553 },
1554 .num_parents = 1,
1555 .flags = CLK_SET_RATE_PARENT,
1556 }
1557 };
1558
1559 static struct clk_regmap meson8b_vclk2_div6_div_gate = {
1560 .data = &(struct clk_regmap_gate_data){
1561 .offset = HHI_VIID_CLK_DIV,
1562 .bit_idx = 3,
1563 },
1564 .hw.init = &(struct clk_init_data){
1565 .name = "vclk2_div6_en",
1566 .ops = &clk_regmap_gate_ops,
1567 .parent_hws = (const struct clk_hw *[]) {
1568 &meson8b_vclk2_div6_div.hw
1569 },
1570 .num_parents = 1,
1571 .flags = CLK_SET_RATE_PARENT,
1572 },
1573 };
1574
1575 static struct clk_fixed_factor meson8b_vclk2_div12_div = {
1576 .mult = 1,
1577 .div = 12,
1578 .hw.init = &(struct clk_init_data){
1579 .name = "vclk2_div12",
1580 .ops = &clk_fixed_factor_ops,
1581 .parent_hws = (const struct clk_hw *[]) {
1582 &meson8b_vclk2_clk_en.hw
1583 },
1584 .num_parents = 1,
1585 .flags = CLK_SET_RATE_PARENT,
1586 }
1587 };
1588
1589 static struct clk_regmap meson8b_vclk2_div12_div_gate = {
1590 .data = &(struct clk_regmap_gate_data){
1591 .offset = HHI_VIID_CLK_DIV,
1592 .bit_idx = 4,
1593 },
1594 .hw.init = &(struct clk_init_data){
1595 .name = "vclk2_div12_en",
1596 .ops = &clk_regmap_gate_ops,
1597 .parent_hws = (const struct clk_hw *[]) {
1598 &meson8b_vclk2_div12_div.hw
1599 },
1600 .num_parents = 1,
1601 .flags = CLK_SET_RATE_PARENT,
1602 },
1603 };
1604
1605 static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
1606 &meson8b_vclk_div1_gate.hw,
1607 &meson8b_vclk_div2_div_gate.hw,
1608 &meson8b_vclk_div4_div_gate.hw,
1609 &meson8b_vclk_div6_div_gate.hw,
1610 &meson8b_vclk_div12_div_gate.hw,
1611 };
1612
1613 static struct clk_regmap meson8b_cts_enct_sel = {
1614 .data = &(struct clk_regmap_mux_data){
1615 .offset = HHI_VID_CLK_DIV,
1616 .mask = 0xf,
1617 .shift = 20,
1618 },
1619 .hw.init = &(struct clk_init_data){
1620 .name = "cts_enct_sel",
1621 .ops = &clk_regmap_mux_ops,
1622 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1623 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1624 .flags = CLK_SET_RATE_PARENT,
1625 },
1626 };
1627
1628 static struct clk_regmap meson8b_cts_enct = {
1629 .data = &(struct clk_regmap_gate_data){
1630 .offset = HHI_VID_CLK_CNTL2,
1631 .bit_idx = 1,
1632 },
1633 .hw.init = &(struct clk_init_data){
1634 .name = "cts_enct",
1635 .ops = &clk_regmap_gate_ops,
1636 .parent_hws = (const struct clk_hw *[]) {
1637 &meson8b_cts_enct_sel.hw
1638 },
1639 .num_parents = 1,
1640 .flags = CLK_SET_RATE_PARENT,
1641 },
1642 };
1643
1644 static struct clk_regmap meson8b_cts_encp_sel = {
1645 .data = &(struct clk_regmap_mux_data){
1646 .offset = HHI_VID_CLK_DIV,
1647 .mask = 0xf,
1648 .shift = 24,
1649 },
1650 .hw.init = &(struct clk_init_data){
1651 .name = "cts_encp_sel",
1652 .ops = &clk_regmap_mux_ops,
1653 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1654 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1655 .flags = CLK_SET_RATE_PARENT,
1656 },
1657 };
1658
1659 static struct clk_regmap meson8b_cts_encp = {
1660 .data = &(struct clk_regmap_gate_data){
1661 .offset = HHI_VID_CLK_CNTL2,
1662 .bit_idx = 2,
1663 },
1664 .hw.init = &(struct clk_init_data){
1665 .name = "cts_encp",
1666 .ops = &clk_regmap_gate_ops,
1667 .parent_hws = (const struct clk_hw *[]) {
1668 &meson8b_cts_encp_sel.hw
1669 },
1670 .num_parents = 1,
1671 .flags = CLK_SET_RATE_PARENT,
1672 },
1673 };
1674
1675 static struct clk_regmap meson8b_cts_enci_sel = {
1676 .data = &(struct clk_regmap_mux_data){
1677 .offset = HHI_VID_CLK_DIV,
1678 .mask = 0xf,
1679 .shift = 28,
1680 },
1681 .hw.init = &(struct clk_init_data){
1682 .name = "cts_enci_sel",
1683 .ops = &clk_regmap_mux_ops,
1684 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1685 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1686 .flags = CLK_SET_RATE_PARENT,
1687 },
1688 };
1689
1690 static struct clk_regmap meson8b_cts_enci = {
1691 .data = &(struct clk_regmap_gate_data){
1692 .offset = HHI_VID_CLK_CNTL2,
1693 .bit_idx = 0,
1694 },
1695 .hw.init = &(struct clk_init_data){
1696 .name = "cts_enci",
1697 .ops = &clk_regmap_gate_ops,
1698 .parent_hws = (const struct clk_hw *[]) {
1699 &meson8b_cts_enci_sel.hw
1700 },
1701 .num_parents = 1,
1702 .flags = CLK_SET_RATE_PARENT,
1703 },
1704 };
1705
1706 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
1707 .data = &(struct clk_regmap_mux_data){
1708 .offset = HHI_HDMI_CLK_CNTL,
1709 .mask = 0xf,
1710 .shift = 16,
1711 },
1712 .hw.init = &(struct clk_init_data){
1713 .name = "hdmi_tx_pixel_sel",
1714 .ops = &clk_regmap_mux_ops,
1715 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1716 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1717 .flags = CLK_SET_RATE_PARENT,
1718 },
1719 };
1720
1721 static struct clk_regmap meson8b_hdmi_tx_pixel = {
1722 .data = &(struct clk_regmap_gate_data){
1723 .offset = HHI_VID_CLK_CNTL2,
1724 .bit_idx = 5,
1725 },
1726 .hw.init = &(struct clk_init_data){
1727 .name = "hdmi_tx_pixel",
1728 .ops = &clk_regmap_gate_ops,
1729 .parent_hws = (const struct clk_hw *[]) {
1730 &meson8b_hdmi_tx_pixel_sel.hw
1731 },
1732 .num_parents = 1,
1733 .flags = CLK_SET_RATE_PARENT,
1734 },
1735 };
1736
1737 static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
1738 &meson8b_vclk2_div1_gate.hw,
1739 &meson8b_vclk2_div2_div_gate.hw,
1740 &meson8b_vclk2_div4_div_gate.hw,
1741 &meson8b_vclk2_div6_div_gate.hw,
1742 &meson8b_vclk2_div12_div_gate.hw,
1743 };
1744
1745 static struct clk_regmap meson8b_cts_encl_sel = {
1746 .data = &(struct clk_regmap_mux_data){
1747 .offset = HHI_VIID_CLK_DIV,
1748 .mask = 0xf,
1749 .shift = 12,
1750 },
1751 .hw.init = &(struct clk_init_data){
1752 .name = "cts_encl_sel",
1753 .ops = &clk_regmap_mux_ops,
1754 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1755 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1756 .flags = CLK_SET_RATE_PARENT,
1757 },
1758 };
1759
1760 static struct clk_regmap meson8b_cts_encl = {
1761 .data = &(struct clk_regmap_gate_data){
1762 .offset = HHI_VID_CLK_CNTL2,
1763 .bit_idx = 3,
1764 },
1765 .hw.init = &(struct clk_init_data){
1766 .name = "cts_encl",
1767 .ops = &clk_regmap_gate_ops,
1768 .parent_hws = (const struct clk_hw *[]) {
1769 &meson8b_cts_encl_sel.hw
1770 },
1771 .num_parents = 1,
1772 .flags = CLK_SET_RATE_PARENT,
1773 },
1774 };
1775
1776 static struct clk_regmap meson8b_cts_vdac0_sel = {
1777 .data = &(struct clk_regmap_mux_data){
1778 .offset = HHI_VIID_CLK_DIV,
1779 .mask = 0xf,
1780 .shift = 28,
1781 },
1782 .hw.init = &(struct clk_init_data){
1783 .name = "cts_vdac0_sel",
1784 .ops = &clk_regmap_mux_ops,
1785 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1786 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1787 .flags = CLK_SET_RATE_PARENT,
1788 },
1789 };
1790
1791 static struct clk_regmap meson8b_cts_vdac0 = {
1792 .data = &(struct clk_regmap_gate_data){
1793 .offset = HHI_VID_CLK_CNTL2,
1794 .bit_idx = 4,
1795 },
1796 .hw.init = &(struct clk_init_data){
1797 .name = "cts_vdac0",
1798 .ops = &clk_regmap_gate_ops,
1799 .parent_hws = (const struct clk_hw *[]) {
1800 &meson8b_cts_vdac0_sel.hw
1801 },
1802 .num_parents = 1,
1803 .flags = CLK_SET_RATE_PARENT,
1804 },
1805 };
1806
1807 static struct clk_regmap meson8b_hdmi_sys_sel = {
1808 .data = &(struct clk_regmap_mux_data){
1809 .offset = HHI_HDMI_CLK_CNTL,
1810 .mask = 0x3,
1811 .shift = 9,
1812 .flags = CLK_MUX_ROUND_CLOSEST,
1813 },
1814 .hw.init = &(struct clk_init_data){
1815 .name = "hdmi_sys_sel",
1816 .ops = &clk_regmap_mux_ops,
1817 /* FIXME: all other parents are unknown */
1818 .parent_data = &(const struct clk_parent_data) {
1819 .fw_name = "xtal",
1820 .name = "xtal",
1821 .index = -1,
1822 },
1823 .num_parents = 1,
1824 .flags = CLK_SET_RATE_NO_REPARENT,
1825 },
1826 };
1827
1828 static struct clk_regmap meson8b_hdmi_sys_div = {
1829 .data = &(struct clk_regmap_div_data){
1830 .offset = HHI_HDMI_CLK_CNTL,
1831 .shift = 0,
1832 .width = 7,
1833 },
1834 .hw.init = &(struct clk_init_data){
1835 .name = "hdmi_sys_div",
1836 .ops = &clk_regmap_divider_ops,
1837 .parent_hws = (const struct clk_hw *[]) {
1838 &meson8b_hdmi_sys_sel.hw
1839 },
1840 .num_parents = 1,
1841 .flags = CLK_SET_RATE_PARENT,
1842 },
1843 };
1844
1845 static struct clk_regmap meson8b_hdmi_sys = {
1846 .data = &(struct clk_regmap_gate_data){
1847 .offset = HHI_HDMI_CLK_CNTL,
1848 .bit_idx = 8,
1849 },
1850 .hw.init = &(struct clk_init_data) {
1851 .name = "hdmi_sys",
1852 .ops = &clk_regmap_gate_ops,
1853 .parent_hws = (const struct clk_hw *[]) {
1854 &meson8b_hdmi_sys_div.hw
1855 },
1856 .num_parents = 1,
1857 .flags = CLK_SET_RATE_PARENT,
1858 },
1859 };
1860
1861 /*
1862 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1863 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
1864 * actually manage this glitch-free mux because it does top-to-bottom
1865 * updates the each clock tree and switches to the "inactive" one when
1866 * CLK_SET_RATE_GATE is set.
1867 * Meson8 only has mali_0 and no glitch-free mux.
1868 */
1869 static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {
1870 { .fw_name = "xtal", .name = "xtal", .index = -1, },
1871 { .hw = &meson8b_mpll2.hw, },
1872 { .hw = &meson8b_mpll1.hw, },
1873 { .hw = &meson8b_fclk_div7.hw, },
1874 { .hw = &meson8b_fclk_div4.hw, },
1875 { .hw = &meson8b_fclk_div3.hw, },
1876 { .hw = &meson8b_fclk_div5.hw, },
1877 };
1878
1879 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
1880
1881 static struct clk_regmap meson8b_mali_0_sel = {
1882 .data = &(struct clk_regmap_mux_data){
1883 .offset = HHI_MALI_CLK_CNTL,
1884 .mask = 0x7,
1885 .shift = 9,
1886 .table = meson8b_mali_0_1_mux_table,
1887 },
1888 .hw.init = &(struct clk_init_data){
1889 .name = "mali_0_sel",
1890 .ops = &clk_regmap_mux_ops,
1891 .parent_data = meson8b_mali_0_1_parent_data,
1892 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
1893 /*
1894 * Don't propagate rate changes up because the only changeable
1895 * parents are mpll1 and mpll2 but we need those for audio and
1896 * RGMII (Ethernet). We don't want to change the audio or
1897 * Ethernet clocks when setting the GPU frequency.
1898 */
1899 .flags = 0,
1900 },
1901 };
1902
1903 static struct clk_regmap meson8b_mali_0_div = {
1904 .data = &(struct clk_regmap_div_data){
1905 .offset = HHI_MALI_CLK_CNTL,
1906 .shift = 0,
1907 .width = 7,
1908 },
1909 .hw.init = &(struct clk_init_data){
1910 .name = "mali_0_div",
1911 .ops = &clk_regmap_divider_ops,
1912 .parent_hws = (const struct clk_hw *[]) {
1913 &meson8b_mali_0_sel.hw
1914 },
1915 .num_parents = 1,
1916 .flags = CLK_SET_RATE_PARENT,
1917 },
1918 };
1919
1920 static struct clk_regmap meson8b_mali_0 = {
1921 .data = &(struct clk_regmap_gate_data){
1922 .offset = HHI_MALI_CLK_CNTL,
1923 .bit_idx = 8,
1924 },
1925 .hw.init = &(struct clk_init_data){
1926 .name = "mali_0",
1927 .ops = &clk_regmap_gate_ops,
1928 .parent_hws = (const struct clk_hw *[]) {
1929 &meson8b_mali_0_div.hw
1930 },
1931 .num_parents = 1,
1932 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1933 },
1934 };
1935
1936 static struct clk_regmap meson8b_mali_1_sel = {
1937 .data = &(struct clk_regmap_mux_data){
1938 .offset = HHI_MALI_CLK_CNTL,
1939 .mask = 0x7,
1940 .shift = 25,
1941 .table = meson8b_mali_0_1_mux_table,
1942 },
1943 .hw.init = &(struct clk_init_data){
1944 .name = "mali_1_sel",
1945 .ops = &clk_regmap_mux_ops,
1946 .parent_data = meson8b_mali_0_1_parent_data,
1947 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
1948 /*
1949 * Don't propagate rate changes up because the only changeable
1950 * parents are mpll1 and mpll2 but we need those for audio and
1951 * RGMII (Ethernet). We don't want to change the audio or
1952 * Ethernet clocks when setting the GPU frequency.
1953 */
1954 .flags = 0,
1955 },
1956 };
1957
1958 static struct clk_regmap meson8b_mali_1_div = {
1959 .data = &(struct clk_regmap_div_data){
1960 .offset = HHI_MALI_CLK_CNTL,
1961 .shift = 16,
1962 .width = 7,
1963 },
1964 .hw.init = &(struct clk_init_data){
1965 .name = "mali_1_div",
1966 .ops = &clk_regmap_divider_ops,
1967 .parent_hws = (const struct clk_hw *[]) {
1968 &meson8b_mali_1_sel.hw
1969 },
1970 .num_parents = 1,
1971 .flags = CLK_SET_RATE_PARENT,
1972 },
1973 };
1974
1975 static struct clk_regmap meson8b_mali_1 = {
1976 .data = &(struct clk_regmap_gate_data){
1977 .offset = HHI_MALI_CLK_CNTL,
1978 .bit_idx = 24,
1979 },
1980 .hw.init = &(struct clk_init_data){
1981 .name = "mali_1",
1982 .ops = &clk_regmap_gate_ops,
1983 .parent_hws = (const struct clk_hw *[]) {
1984 &meson8b_mali_1_div.hw
1985 },
1986 .num_parents = 1,
1987 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1988 },
1989 };
1990
1991 static struct clk_regmap meson8b_mali = {
1992 .data = &(struct clk_regmap_mux_data){
1993 .offset = HHI_MALI_CLK_CNTL,
1994 .mask = 1,
1995 .shift = 31,
1996 },
1997 .hw.init = &(struct clk_init_data){
1998 .name = "mali",
1999 .ops = &clk_regmap_mux_ops,
2000 .parent_hws = (const struct clk_hw *[]) {
2001 &meson8b_mali_0.hw,
2002 &meson8b_mali_1.hw,
2003 },
2004 .num_parents = 2,
2005 .flags = CLK_SET_RATE_PARENT,
2006 },
2007 };
2008
2009 static const struct reg_sequence meson8m2_gp_pll_init_regs[] = {
2010 { .reg = HHI_GP_PLL_CNTL2, .def = 0x59c88000 },
2011 { .reg = HHI_GP_PLL_CNTL3, .def = 0xca463823 },
2012 { .reg = HHI_GP_PLL_CNTL4, .def = 0x0286a027 },
2013 { .reg = HHI_GP_PLL_CNTL5, .def = 0x00003000 },
2014 };
2015
2016 static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
2017 PLL_PARAMS(182, 3),
2018 { /* sentinel */ },
2019 };
2020
2021 static struct clk_regmap meson8m2_gp_pll_dco = {
2022 .data = &(struct meson_clk_pll_data){
2023 .en = {
2024 .reg_off = HHI_GP_PLL_CNTL,
2025 .shift = 30,
2026 .width = 1,
2027 },
2028 .m = {
2029 .reg_off = HHI_GP_PLL_CNTL,
2030 .shift = 0,
2031 .width = 9,
2032 },
2033 .n = {
2034 .reg_off = HHI_GP_PLL_CNTL,
2035 .shift = 9,
2036 .width = 5,
2037 },
2038 .l = {
2039 .reg_off = HHI_GP_PLL_CNTL,
2040 .shift = 31,
2041 .width = 1,
2042 },
2043 .rst = {
2044 .reg_off = HHI_GP_PLL_CNTL,
2045 .shift = 29,
2046 .width = 1,
2047 },
2048 .table = meson8m2_gp_pll_params_table,
2049 .init_regs = meson8m2_gp_pll_init_regs,
2050 .init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs),
2051 },
2052 .hw.init = &(struct clk_init_data){
2053 .name = "gp_pll_dco",
2054 .ops = &meson_clk_pll_ops,
2055 .parent_data = &(const struct clk_parent_data) {
2056 .fw_name = "xtal",
2057 .name = "xtal",
2058 .index = -1,
2059 },
2060 .num_parents = 1,
2061 },
2062 };
2063
2064 static struct clk_regmap meson8m2_gp_pll = {
2065 .data = &(struct clk_regmap_div_data){
2066 .offset = HHI_GP_PLL_CNTL,
2067 .shift = 16,
2068 .width = 2,
2069 .flags = CLK_DIVIDER_POWER_OF_TWO,
2070 },
2071 .hw.init = &(struct clk_init_data){
2072 .name = "gp_pll",
2073 .ops = &clk_regmap_divider_ops,
2074 .parent_hws = (const struct clk_hw *[]) {
2075 &meson8m2_gp_pll_dco.hw
2076 },
2077 .num_parents = 1,
2078 .flags = CLK_SET_RATE_PARENT,
2079 },
2080 };
2081
2082 static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
2083 &meson8b_fclk_div4.hw,
2084 &meson8b_fclk_div3.hw,
2085 &meson8b_fclk_div5.hw,
2086 &meson8b_fclk_div7.hw,
2087 };
2088
2089 static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
2090 &meson8b_fclk_div4.hw,
2091 &meson8b_fclk_div3.hw,
2092 &meson8b_fclk_div5.hw,
2093 &meson8m2_gp_pll.hw,
2094 };
2095
2096 static struct clk_regmap meson8b_vpu_0_sel = {
2097 .data = &(struct clk_regmap_mux_data){
2098 .offset = HHI_VPU_CLK_CNTL,
2099 .mask = 0x3,
2100 .shift = 9,
2101 },
2102 .hw.init = &(struct clk_init_data){
2103 .name = "vpu_0_sel",
2104 .ops = &clk_regmap_mux_ops,
2105 .parent_hws = meson8b_vpu_0_1_parent_hws,
2106 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2107 .flags = CLK_SET_RATE_PARENT,
2108 },
2109 };
2110
2111 static struct clk_regmap meson8m2_vpu_0_sel = {
2112 .data = &(struct clk_regmap_mux_data){
2113 .offset = HHI_VPU_CLK_CNTL,
2114 .mask = 0x3,
2115 .shift = 9,
2116 },
2117 .hw.init = &(struct clk_init_data){
2118 .name = "vpu_0_sel",
2119 .ops = &clk_regmap_mux_ops,
2120 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2121 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2122 .flags = CLK_SET_RATE_PARENT,
2123 },
2124 };
2125
2126 static struct clk_regmap meson8b_vpu_0_div = {
2127 .data = &(struct clk_regmap_div_data){
2128 .offset = HHI_VPU_CLK_CNTL,
2129 .shift = 0,
2130 .width = 7,
2131 },
2132 .hw.init = &(struct clk_init_data){
2133 .name = "vpu_0_div",
2134 .ops = &clk_regmap_divider_ops,
2135 .parent_data = &(const struct clk_parent_data) {
2136 /*
2137 * Note:
2138 * meson8b and meson8m2 have different vpu_0_sels (with
2139 * different struct clk_hw). We fallback to the global
2140 * naming string mechanism so vpu_0_div picks up the
2141 * appropriate one.
2142 */
2143 .name = "vpu_0_sel",
2144 .index = -1,
2145 },
2146 .num_parents = 1,
2147 .flags = CLK_SET_RATE_PARENT,
2148 },
2149 };
2150
2151 static struct clk_regmap meson8b_vpu_0 = {
2152 .data = &(struct clk_regmap_gate_data){
2153 .offset = HHI_VPU_CLK_CNTL,
2154 .bit_idx = 8,
2155 },
2156 .hw.init = &(struct clk_init_data) {
2157 .name = "vpu_0",
2158 .ops = &clk_regmap_gate_ops,
2159 .parent_hws = (const struct clk_hw *[]) {
2160 &meson8b_vpu_0_div.hw
2161 },
2162 .num_parents = 1,
2163 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
2164 },
2165 };
2166
2167 static struct clk_regmap meson8b_vpu_1_sel = {
2168 .data = &(struct clk_regmap_mux_data){
2169 .offset = HHI_VPU_CLK_CNTL,
2170 .mask = 0x3,
2171 .shift = 25,
2172 },
2173 .hw.init = &(struct clk_init_data){
2174 .name = "vpu_1_sel",
2175 .ops = &clk_regmap_mux_ops,
2176 .parent_hws = meson8b_vpu_0_1_parent_hws,
2177 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2178 .flags = CLK_SET_RATE_PARENT,
2179 },
2180 };
2181
2182 static struct clk_regmap meson8m2_vpu_1_sel = {
2183 .data = &(struct clk_regmap_mux_data){
2184 .offset = HHI_VPU_CLK_CNTL,
2185 .mask = 0x3,
2186 .shift = 25,
2187 },
2188 .hw.init = &(struct clk_init_data){
2189 .name = "vpu_1_sel",
2190 .ops = &clk_regmap_mux_ops,
2191 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2192 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2193 .flags = CLK_SET_RATE_PARENT,
2194 },
2195 };
2196
2197 static struct clk_regmap meson8b_vpu_1_div = {
2198 .data = &(struct clk_regmap_div_data){
2199 .offset = HHI_VPU_CLK_CNTL,
2200 .shift = 16,
2201 .width = 7,
2202 },
2203 .hw.init = &(struct clk_init_data){
2204 .name = "vpu_1_div",
2205 .ops = &clk_regmap_divider_ops,
2206 .parent_data = &(const struct clk_parent_data) {
2207 /*
2208 * Note:
2209 * meson8b and meson8m2 have different vpu_1_sels (with
2210 * different struct clk_hw). We fallback to the global
2211 * naming string mechanism so vpu_1_div picks up the
2212 * appropriate one.
2213 */
2214 .name = "vpu_1_sel",
2215 .index = -1,
2216 },
2217 .num_parents = 1,
2218 .flags = CLK_SET_RATE_PARENT,
2219 },
2220 };
2221
2222 static struct clk_regmap meson8b_vpu_1 = {
2223 .data = &(struct clk_regmap_gate_data){
2224 .offset = HHI_VPU_CLK_CNTL,
2225 .bit_idx = 24,
2226 },
2227 .hw.init = &(struct clk_init_data) {
2228 .name = "vpu_1",
2229 .ops = &clk_regmap_gate_ops,
2230 .parent_hws = (const struct clk_hw *[]) {
2231 &meson8b_vpu_1_div.hw
2232 },
2233 .num_parents = 1,
2234 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
2235 },
2236 };
2237
2238 /*
2239 * The VPU clock has two identical clock trees (vpu_0 and vpu_1)
2240 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
2241 * actually manage this glitch-free mux because it does top-to-bottom
2242 * updates the each clock tree and switches to the "inactive" one when
2243 * CLK_SET_RATE_GATE is set.
2244 * Meson8 only has vpu_0 and no glitch-free mux.
2245 */
2246 static struct clk_regmap meson8b_vpu = {
2247 .data = &(struct clk_regmap_mux_data){
2248 .offset = HHI_VPU_CLK_CNTL,
2249 .mask = 1,
2250 .shift = 31,
2251 },
2252 .hw.init = &(struct clk_init_data){
2253 .name = "vpu",
2254 .ops = &clk_regmap_mux_ops,
2255 .parent_hws = (const struct clk_hw *[]) {
2256 &meson8b_vpu_0.hw,
2257 &meson8b_vpu_1.hw,
2258 },
2259 .num_parents = 2,
2260 .flags = CLK_SET_RATE_PARENT,
2261 },
2262 };
2263
2264 static const struct clk_hw *meson8b_vdec_parent_hws[] = {
2265 &meson8b_fclk_div4.hw,
2266 &meson8b_fclk_div3.hw,
2267 &meson8b_fclk_div5.hw,
2268 &meson8b_fclk_div7.hw,
2269 &meson8b_mpll2.hw,
2270 &meson8b_mpll1.hw,
2271 };
2272
2273 static struct clk_regmap meson8b_vdec_1_sel = {
2274 .data = &(struct clk_regmap_mux_data){
2275 .offset = HHI_VDEC_CLK_CNTL,
2276 .mask = 0x3,
2277 .shift = 9,
2278 .flags = CLK_MUX_ROUND_CLOSEST,
2279 },
2280 .hw.init = &(struct clk_init_data){
2281 .name = "vdec_1_sel",
2282 .ops = &clk_regmap_mux_ops,
2283 .parent_hws = meson8b_vdec_parent_hws,
2284 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2285 .flags = CLK_SET_RATE_PARENT,
2286 },
2287 };
2288
2289 static struct clk_regmap meson8b_vdec_1_1_div = {
2290 .data = &(struct clk_regmap_div_data){
2291 .offset = HHI_VDEC_CLK_CNTL,
2292 .shift = 0,
2293 .width = 7,
2294 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2295 },
2296 .hw.init = &(struct clk_init_data){
2297 .name = "vdec_1_1_div",
2298 .ops = &clk_regmap_divider_ops,
2299 .parent_hws = (const struct clk_hw *[]) {
2300 &meson8b_vdec_1_sel.hw
2301 },
2302 .num_parents = 1,
2303 .flags = CLK_SET_RATE_PARENT,
2304 },
2305 };
2306
2307 static struct clk_regmap meson8b_vdec_1_1 = {
2308 .data = &(struct clk_regmap_gate_data){
2309 .offset = HHI_VDEC_CLK_CNTL,
2310 .bit_idx = 8,
2311 },
2312 .hw.init = &(struct clk_init_data) {
2313 .name = "vdec_1_1",
2314 .ops = &clk_regmap_gate_ops,
2315 .parent_hws = (const struct clk_hw *[]) {
2316 &meson8b_vdec_1_1_div.hw
2317 },
2318 .num_parents = 1,
2319 .flags = CLK_SET_RATE_PARENT,
2320 },
2321 };
2322
2323 static struct clk_regmap meson8b_vdec_1_2_div = {
2324 .data = &(struct clk_regmap_div_data){
2325 .offset = HHI_VDEC3_CLK_CNTL,
2326 .shift = 0,
2327 .width = 7,
2328 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2329 },
2330 .hw.init = &(struct clk_init_data){
2331 .name = "vdec_1_2_div",
2332 .ops = &clk_regmap_divider_ops,
2333 .parent_hws = (const struct clk_hw *[]) {
2334 &meson8b_vdec_1_sel.hw
2335 },
2336 .num_parents = 1,
2337 .flags = CLK_SET_RATE_PARENT,
2338 },
2339 };
2340
2341 static struct clk_regmap meson8b_vdec_1_2 = {
2342 .data = &(struct clk_regmap_gate_data){
2343 .offset = HHI_VDEC3_CLK_CNTL,
2344 .bit_idx = 8,
2345 },
2346 .hw.init = &(struct clk_init_data) {
2347 .name = "vdec_1_2",
2348 .ops = &clk_regmap_gate_ops,
2349 .parent_hws = (const struct clk_hw *[]) {
2350 &meson8b_vdec_1_2_div.hw
2351 },
2352 .num_parents = 1,
2353 .flags = CLK_SET_RATE_PARENT,
2354 },
2355 };
2356
2357 static struct clk_regmap meson8b_vdec_1 = {
2358 .data = &(struct clk_regmap_mux_data){
2359 .offset = HHI_VDEC3_CLK_CNTL,
2360 .mask = 0x1,
2361 .shift = 15,
2362 .flags = CLK_MUX_ROUND_CLOSEST,
2363 },
2364 .hw.init = &(struct clk_init_data){
2365 .name = "vdec_1",
2366 .ops = &clk_regmap_mux_ops,
2367 .parent_hws = (const struct clk_hw *[]) {
2368 &meson8b_vdec_1_1.hw,
2369 &meson8b_vdec_1_2.hw,
2370 },
2371 .num_parents = 2,
2372 .flags = CLK_SET_RATE_PARENT,
2373 },
2374 };
2375
2376 static struct clk_regmap meson8b_vdec_hcodec_sel = {
2377 .data = &(struct clk_regmap_mux_data){
2378 .offset = HHI_VDEC_CLK_CNTL,
2379 .mask = 0x3,
2380 .shift = 25,
2381 .flags = CLK_MUX_ROUND_CLOSEST,
2382 },
2383 .hw.init = &(struct clk_init_data){
2384 .name = "vdec_hcodec_sel",
2385 .ops = &clk_regmap_mux_ops,
2386 .parent_hws = meson8b_vdec_parent_hws,
2387 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2388 .flags = CLK_SET_RATE_PARENT,
2389 },
2390 };
2391
2392 static struct clk_regmap meson8b_vdec_hcodec_div = {
2393 .data = &(struct clk_regmap_div_data){
2394 .offset = HHI_VDEC_CLK_CNTL,
2395 .shift = 16,
2396 .width = 7,
2397 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2398 },
2399 .hw.init = &(struct clk_init_data){
2400 .name = "vdec_hcodec_div",
2401 .ops = &clk_regmap_divider_ops,
2402 .parent_hws = (const struct clk_hw *[]) {
2403 &meson8b_vdec_hcodec_sel.hw
2404 },
2405 .num_parents = 1,
2406 .flags = CLK_SET_RATE_PARENT,
2407 },
2408 };
2409
2410 static struct clk_regmap meson8b_vdec_hcodec = {
2411 .data = &(struct clk_regmap_gate_data){
2412 .offset = HHI_VDEC_CLK_CNTL,
2413 .bit_idx = 24,
2414 },
2415 .hw.init = &(struct clk_init_data) {
2416 .name = "vdec_hcodec",
2417 .ops = &clk_regmap_gate_ops,
2418 .parent_hws = (const struct clk_hw *[]) {
2419 &meson8b_vdec_hcodec_div.hw
2420 },
2421 .num_parents = 1,
2422 .flags = CLK_SET_RATE_PARENT,
2423 },
2424 };
2425
2426 static struct clk_regmap meson8b_vdec_2_sel = {
2427 .data = &(struct clk_regmap_mux_data){
2428 .offset = HHI_VDEC2_CLK_CNTL,
2429 .mask = 0x3,
2430 .shift = 9,
2431 .flags = CLK_MUX_ROUND_CLOSEST,
2432 },
2433 .hw.init = &(struct clk_init_data){
2434 .name = "vdec_2_sel",
2435 .ops = &clk_regmap_mux_ops,
2436 .parent_hws = meson8b_vdec_parent_hws,
2437 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2438 .flags = CLK_SET_RATE_PARENT,
2439 },
2440 };
2441
2442 static struct clk_regmap meson8b_vdec_2_div = {
2443 .data = &(struct clk_regmap_div_data){
2444 .offset = HHI_VDEC2_CLK_CNTL,
2445 .shift = 0,
2446 .width = 7,
2447 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2448 },
2449 .hw.init = &(struct clk_init_data){
2450 .name = "vdec_2_div",
2451 .ops = &clk_regmap_divider_ops,
2452 .parent_hws = (const struct clk_hw *[]) {
2453 &meson8b_vdec_2_sel.hw
2454 },
2455 .num_parents = 1,
2456 .flags = CLK_SET_RATE_PARENT,
2457 },
2458 };
2459
2460 static struct clk_regmap meson8b_vdec_2 = {
2461 .data = &(struct clk_regmap_gate_data){
2462 .offset = HHI_VDEC2_CLK_CNTL,
2463 .bit_idx = 8,
2464 },
2465 .hw.init = &(struct clk_init_data) {
2466 .name = "vdec_2",
2467 .ops = &clk_regmap_gate_ops,
2468 .parent_hws = (const struct clk_hw *[]) {
2469 &meson8b_vdec_2_div.hw
2470 },
2471 .num_parents = 1,
2472 .flags = CLK_SET_RATE_PARENT,
2473 },
2474 };
2475
2476 static struct clk_regmap meson8b_vdec_hevc_sel = {
2477 .data = &(struct clk_regmap_mux_data){
2478 .offset = HHI_VDEC2_CLK_CNTL,
2479 .mask = 0x3,
2480 .shift = 25,
2481 .flags = CLK_MUX_ROUND_CLOSEST,
2482 },
2483 .hw.init = &(struct clk_init_data){
2484 .name = "vdec_hevc_sel",
2485 .ops = &clk_regmap_mux_ops,
2486 .parent_hws = meson8b_vdec_parent_hws,
2487 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2488 .flags = CLK_SET_RATE_PARENT,
2489 },
2490 };
2491
2492 static struct clk_regmap meson8b_vdec_hevc_div = {
2493 .data = &(struct clk_regmap_div_data){
2494 .offset = HHI_VDEC2_CLK_CNTL,
2495 .shift = 16,
2496 .width = 7,
2497 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2498 },
2499 .hw.init = &(struct clk_init_data){
2500 .name = "vdec_hevc_div",
2501 .ops = &clk_regmap_divider_ops,
2502 .parent_hws = (const struct clk_hw *[]) {
2503 &meson8b_vdec_hevc_sel.hw
2504 },
2505 .num_parents = 1,
2506 .flags = CLK_SET_RATE_PARENT,
2507 },
2508 };
2509
2510 static struct clk_regmap meson8b_vdec_hevc_en = {
2511 .data = &(struct clk_regmap_gate_data){
2512 .offset = HHI_VDEC2_CLK_CNTL,
2513 .bit_idx = 24,
2514 },
2515 .hw.init = &(struct clk_init_data) {
2516 .name = "vdec_hevc_en",
2517 .ops = &clk_regmap_gate_ops,
2518 .parent_hws = (const struct clk_hw *[]) {
2519 &meson8b_vdec_hevc_div.hw
2520 },
2521 .num_parents = 1,
2522 .flags = CLK_SET_RATE_PARENT,
2523 },
2524 };
2525
2526 static struct clk_regmap meson8b_vdec_hevc = {
2527 .data = &(struct clk_regmap_mux_data){
2528 .offset = HHI_VDEC2_CLK_CNTL,
2529 .mask = 0x1,
2530 .shift = 31,
2531 .flags = CLK_MUX_ROUND_CLOSEST,
2532 },
2533 .hw.init = &(struct clk_init_data){
2534 .name = "vdec_hevc",
2535 .ops = &clk_regmap_mux_ops,
2536 /* TODO: The second parent is currently unknown */
2537 .parent_hws = (const struct clk_hw *[]) {
2538 &meson8b_vdec_hevc_en.hw
2539 },
2540 .num_parents = 1,
2541 .flags = CLK_SET_RATE_PARENT,
2542 },
2543 };
2544
2545 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2546 static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
2547 &meson8b_mpll0.hw,
2548 &meson8b_mpll1.hw,
2549 &meson8b_mpll2.hw
2550 };
2551
2552 static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
2553
2554 static struct clk_regmap meson8b_cts_amclk_sel = {
2555 .data = &(struct clk_regmap_mux_data){
2556 .offset = HHI_AUD_CLK_CNTL,
2557 .mask = 0x3,
2558 .shift = 9,
2559 .table = meson8b_cts_amclk_mux_table,
2560 .flags = CLK_MUX_ROUND_CLOSEST,
2561 },
2562 .hw.init = &(struct clk_init_data){
2563 .name = "cts_amclk_sel",
2564 .ops = &clk_regmap_mux_ops,
2565 .parent_hws = meson8b_cts_amclk_parent_hws,
2566 .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
2567 },
2568 };
2569
2570 static struct clk_regmap meson8b_cts_amclk_div = {
2571 .data = &(struct clk_regmap_div_data) {
2572 .offset = HHI_AUD_CLK_CNTL,
2573 .shift = 0,
2574 .width = 8,
2575 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2576 },
2577 .hw.init = &(struct clk_init_data){
2578 .name = "cts_amclk_div",
2579 .ops = &clk_regmap_divider_ops,
2580 .parent_hws = (const struct clk_hw *[]) {
2581 &meson8b_cts_amclk_sel.hw
2582 },
2583 .num_parents = 1,
2584 .flags = CLK_SET_RATE_PARENT,
2585 },
2586 };
2587
2588 static struct clk_regmap meson8b_cts_amclk = {
2589 .data = &(struct clk_regmap_gate_data){
2590 .offset = HHI_AUD_CLK_CNTL,
2591 .bit_idx = 8,
2592 },
2593 .hw.init = &(struct clk_init_data){
2594 .name = "cts_amclk",
2595 .ops = &clk_regmap_gate_ops,
2596 .parent_hws = (const struct clk_hw *[]) {
2597 &meson8b_cts_amclk_div.hw
2598 },
2599 .num_parents = 1,
2600 .flags = CLK_SET_RATE_PARENT,
2601 },
2602 };
2603
2604 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2605 static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
2606 &meson8b_mpll0.hw,
2607 &meson8b_mpll1.hw,
2608 &meson8b_mpll2.hw
2609 };
2610
2611 static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
2612
2613 static struct clk_regmap meson8b_cts_mclk_i958_sel = {
2614 .data = &(struct clk_regmap_mux_data){
2615 .offset = HHI_AUD_CLK_CNTL2,
2616 .mask = 0x3,
2617 .shift = 25,
2618 .table = meson8b_cts_mclk_i958_mux_table,
2619 .flags = CLK_MUX_ROUND_CLOSEST,
2620 },
2621 .hw.init = &(struct clk_init_data) {
2622 .name = "cts_mclk_i958_sel",
2623 .ops = &clk_regmap_mux_ops,
2624 .parent_hws = meson8b_cts_mclk_i958_parent_hws,
2625 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
2626 },
2627 };
2628
2629 static struct clk_regmap meson8b_cts_mclk_i958_div = {
2630 .data = &(struct clk_regmap_div_data){
2631 .offset = HHI_AUD_CLK_CNTL2,
2632 .shift = 16,
2633 .width = 8,
2634 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2635 },
2636 .hw.init = &(struct clk_init_data) {
2637 .name = "cts_mclk_i958_div",
2638 .ops = &clk_regmap_divider_ops,
2639 .parent_hws = (const struct clk_hw *[]) {
2640 &meson8b_cts_mclk_i958_sel.hw
2641 },
2642 .num_parents = 1,
2643 .flags = CLK_SET_RATE_PARENT,
2644 },
2645 };
2646
2647 static struct clk_regmap meson8b_cts_mclk_i958 = {
2648 .data = &(struct clk_regmap_gate_data){
2649 .offset = HHI_AUD_CLK_CNTL2,
2650 .bit_idx = 24,
2651 },
2652 .hw.init = &(struct clk_init_data){
2653 .name = "cts_mclk_i958",
2654 .ops = &clk_regmap_gate_ops,
2655 .parent_hws = (const struct clk_hw *[]) {
2656 &meson8b_cts_mclk_i958_div.hw
2657 },
2658 .num_parents = 1,
2659 .flags = CLK_SET_RATE_PARENT,
2660 },
2661 };
2662
2663 static struct clk_regmap meson8b_cts_i958 = {
2664 .data = &(struct clk_regmap_mux_data){
2665 .offset = HHI_AUD_CLK_CNTL2,
2666 .mask = 0x1,
2667 .shift = 27,
2668 },
2669 .hw.init = &(struct clk_init_data){
2670 .name = "cts_i958",
2671 .ops = &clk_regmap_mux_ops,
2672 .parent_hws = (const struct clk_hw *[]) {
2673 &meson8b_cts_amclk.hw,
2674 &meson8b_cts_mclk_i958.hw
2675 },
2676 .num_parents = 2,
2677 /*
2678 * The parent is specific to origin of the audio data. Let the
2679 * consumer choose the appropriate parent.
2680 */
2681 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2682 },
2683 };
2684
2685 #define MESON_GATE(_name, _reg, _bit) \
2686 MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
2687
2688 /* Everything Else (EE) domain gates */
2689
2690 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
2691 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
2692 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
2693 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
2694 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
2695 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
2696 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
2697 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
2698 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
2699 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
2700 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
2701 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
2702 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
2703 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
2704 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
2705 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
2706 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
2707 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
2708 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
2709
2710 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
2711 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
2712 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
2713 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
2714 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
2715 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
2716 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
2717 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
2718 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
2719 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
2720 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
2721 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
2722 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
2723 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
2724 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
2725 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
2726 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
2727
2728 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2729 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2730 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2731 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2732 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2733 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2734 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
2735 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
2736 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
2737 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
2738 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
2739 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2740 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
2741
2742 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
2743 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
2744 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2745 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2746 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
2747 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2748 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
2749 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
2750 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
2751 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
2752 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
2753 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
2754 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2755 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
2756 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
2757 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
2758
2759 /* AIU gates */
2760 #define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
2761 MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
2762
2763 static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
2764 static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
2765 static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
2766 static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
2767 static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
2768 static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
2769 static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
2770 static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
2771
2772 /* Always On (AO) domain gates */
2773
2774 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
2775 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
2776 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
2777 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
2778
2779 static struct clk_hw *meson8_hw_clks[] = {
2780 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2781 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2782 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2783 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2784 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2785 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2786 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2787 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2788 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2789 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2790 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2791 [CLKID_CLK81] = &meson8b_clk81.hw,
2792 [CLKID_DDR] = &meson8b_ddr.hw,
2793 [CLKID_DOS] = &meson8b_dos.hw,
2794 [CLKID_ISA] = &meson8b_isa.hw,
2795 [CLKID_PL301] = &meson8b_pl301.hw,
2796 [CLKID_PERIPHS] = &meson8b_periphs.hw,
2797 [CLKID_SPICC] = &meson8b_spicc.hw,
2798 [CLKID_I2C] = &meson8b_i2c.hw,
2799 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
2800 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
2801 [CLKID_RNG0] = &meson8b_rng0.hw,
2802 [CLKID_UART0] = &meson8b_uart0.hw,
2803 [CLKID_SDHC] = &meson8b_sdhc.hw,
2804 [CLKID_STREAM] = &meson8b_stream.hw,
2805 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
2806 [CLKID_SDIO] = &meson8b_sdio.hw,
2807 [CLKID_ABUF] = &meson8b_abuf.hw,
2808 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
2809 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
2810 [CLKID_SPI] = &meson8b_spi.hw,
2811 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
2812 [CLKID_ETH] = &meson8b_eth.hw,
2813 [CLKID_DEMUX] = &meson8b_demux.hw,
2814 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
2815 [CLKID_IEC958] = &meson8b_iec958.hw,
2816 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
2817 [CLKID_AMCLK] = &meson8b_amclk.hw,
2818 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
2819 [CLKID_MIXER] = &meson8b_mixer.hw,
2820 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
2821 [CLKID_ADC] = &meson8b_adc.hw,
2822 [CLKID_BLKMV] = &meson8b_blkmv.hw,
2823 [CLKID_AIU] = &meson8b_aiu.hw,
2824 [CLKID_UART1] = &meson8b_uart1.hw,
2825 [CLKID_G2D] = &meson8b_g2d.hw,
2826 [CLKID_USB0] = &meson8b_usb0.hw,
2827 [CLKID_USB1] = &meson8b_usb1.hw,
2828 [CLKID_RESET] = &meson8b_reset.hw,
2829 [CLKID_NAND] = &meson8b_nand.hw,
2830 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
2831 [CLKID_USB] = &meson8b_usb.hw,
2832 [CLKID_VDIN1] = &meson8b_vdin1.hw,
2833 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
2834 [CLKID_EFUSE] = &meson8b_efuse.hw,
2835 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
2836 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
2837 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
2838 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
2839 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
2840 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
2841 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
2842 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
2843 [CLKID_DVIN] = &meson8b_dvin.hw,
2844 [CLKID_UART2] = &meson8b_uart2.hw,
2845 [CLKID_SANA] = &meson8b_sana.hw,
2846 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
2847 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2848 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
2849 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
2850 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
2851 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
2852 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
2853 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
2854 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
2855 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
2856 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
2857 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
2858 [CLKID_ENC480P] = &meson8b_enc480p.hw,
2859 [CLKID_RNG1] = &meson8b_rng1.hw,
2860 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
2861 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
2862 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
2863 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
2864 [CLKID_EDP] = &meson8b_edp.hw,
2865 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
2866 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
2867 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
2868 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
2869 [CLKID_MPLL0] = &meson8b_mpll0.hw,
2870 [CLKID_MPLL1] = &meson8b_mpll1.hw,
2871 [CLKID_MPLL2] = &meson8b_mpll2.hw,
2872 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
2873 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
2874 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
2875 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
2876 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
2877 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
2878 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
2879 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
2880 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
2881 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
2882 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
2883 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
2884 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
2885 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
2886 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
2887 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
2888 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
2889 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
2890 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
2891 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
2892 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
2893 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
2894 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
2895 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
2896 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
2897 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
2898 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
2899 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
2900 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
2901 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
2902 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
2903 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
2904 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
2905 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
2906 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
2907 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
2908 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
2909 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
2910 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
2911 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
2912 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
2913 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
2914 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
2915 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
2916 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
2917 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
2918 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
2919 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
2920 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
2921 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
2922 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
2923 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
2924 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
2925 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
2926 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
2927 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
2928 [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
2929 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
2930 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
2931 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
2932 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
2933 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
2934 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
2935 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
2936 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
2937 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
2938 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
2939 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
2940 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
2941 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
2942 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
2943 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
2944 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
2945 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
2946 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
2947 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
2948 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
2949 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
2950 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
2951 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
2952 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
2953 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
2954 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
2955 [CLKID_MALI] = &meson8b_mali_0.hw,
2956 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
2957 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
2958 [CLKID_VPU] = &meson8b_vpu_0.hw,
2959 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
2960 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
2961 [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
2962 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
2963 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
2964 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
2965 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
2966 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
2967 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
2968 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
2969 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
2970 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
2971 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
2972 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
2973 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
2974 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
2975 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
2976 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
2977 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
2978 [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
2979 [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
2980 [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
2981 };
2982
2983 static struct clk_hw *meson8b_hw_clks[] = {
2984 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2985 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2986 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2987 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2988 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2989 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2990 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2991 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2992 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2993 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2994 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2995 [CLKID_CLK81] = &meson8b_clk81.hw,
2996 [CLKID_DDR] = &meson8b_ddr.hw,
2997 [CLKID_DOS] = &meson8b_dos.hw,
2998 [CLKID_ISA] = &meson8b_isa.hw,
2999 [CLKID_PL301] = &meson8b_pl301.hw,
3000 [CLKID_PERIPHS] = &meson8b_periphs.hw,
3001 [CLKID_SPICC] = &meson8b_spicc.hw,
3002 [CLKID_I2C] = &meson8b_i2c.hw,
3003 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
3004 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
3005 [CLKID_RNG0] = &meson8b_rng0.hw,
3006 [CLKID_UART0] = &meson8b_uart0.hw,
3007 [CLKID_SDHC] = &meson8b_sdhc.hw,
3008 [CLKID_STREAM] = &meson8b_stream.hw,
3009 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
3010 [CLKID_SDIO] = &meson8b_sdio.hw,
3011 [CLKID_ABUF] = &meson8b_abuf.hw,
3012 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
3013 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
3014 [CLKID_SPI] = &meson8b_spi.hw,
3015 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
3016 [CLKID_ETH] = &meson8b_eth.hw,
3017 [CLKID_DEMUX] = &meson8b_demux.hw,
3018 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
3019 [CLKID_IEC958] = &meson8b_iec958.hw,
3020 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
3021 [CLKID_AMCLK] = &meson8b_amclk.hw,
3022 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
3023 [CLKID_MIXER] = &meson8b_mixer.hw,
3024 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
3025 [CLKID_ADC] = &meson8b_adc.hw,
3026 [CLKID_BLKMV] = &meson8b_blkmv.hw,
3027 [CLKID_AIU] = &meson8b_aiu.hw,
3028 [CLKID_UART1] = &meson8b_uart1.hw,
3029 [CLKID_G2D] = &meson8b_g2d.hw,
3030 [CLKID_USB0] = &meson8b_usb0.hw,
3031 [CLKID_USB1] = &meson8b_usb1.hw,
3032 [CLKID_RESET] = &meson8b_reset.hw,
3033 [CLKID_NAND] = &meson8b_nand.hw,
3034 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
3035 [CLKID_USB] = &meson8b_usb.hw,
3036 [CLKID_VDIN1] = &meson8b_vdin1.hw,
3037 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
3038 [CLKID_EFUSE] = &meson8b_efuse.hw,
3039 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
3040 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
3041 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
3042 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
3043 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
3044 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
3045 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
3046 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
3047 [CLKID_DVIN] = &meson8b_dvin.hw,
3048 [CLKID_UART2] = &meson8b_uart2.hw,
3049 [CLKID_SANA] = &meson8b_sana.hw,
3050 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
3051 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
3052 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
3053 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
3054 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
3055 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
3056 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
3057 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
3058 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
3059 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
3060 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
3061 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
3062 [CLKID_ENC480P] = &meson8b_enc480p.hw,
3063 [CLKID_RNG1] = &meson8b_rng1.hw,
3064 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
3065 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
3066 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
3067 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
3068 [CLKID_EDP] = &meson8b_edp.hw,
3069 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
3070 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
3071 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
3072 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
3073 [CLKID_MPLL0] = &meson8b_mpll0.hw,
3074 [CLKID_MPLL1] = &meson8b_mpll1.hw,
3075 [CLKID_MPLL2] = &meson8b_mpll2.hw,
3076 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3077 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
3078 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
3079 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
3080 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
3081 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
3082 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
3083 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
3084 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
3085 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
3086 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
3087 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
3088 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
3089 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
3090 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
3091 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
3092 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
3093 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
3094 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
3095 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
3096 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
3097 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
3098 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
3099 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
3100 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
3101 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
3102 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
3103 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
3104 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
3105 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
3106 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
3107 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
3108 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
3109 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
3110 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
3111 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
3112 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
3113 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
3114 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
3115 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
3116 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
3117 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
3118 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
3119 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
3120 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
3121 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3122 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
3123 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3124 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
3125 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3126 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
3127 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3128 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
3129 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
3130 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
3131 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
3132 [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
3133 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3134 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
3135 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
3136 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
3137 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
3138 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
3139 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
3140 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
3141 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
3142 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
3143 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
3144 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
3145 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
3146 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
3147 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
3148 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
3149 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
3150 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
3151 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
3152 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
3153 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
3154 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
3155 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
3156 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
3157 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
3158 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
3159 [CLKID_MALI_0] = &meson8b_mali_0.hw,
3160 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
3161 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
3162 [CLKID_MALI_1] = &meson8b_mali_1.hw,
3163 [CLKID_MALI] = &meson8b_mali.hw,
3164 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
3165 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
3166 [CLKID_VPU_0] = &meson8b_vpu_0.hw,
3167 [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
3168 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
3169 [CLKID_VPU_1] = &meson8b_vpu_1.hw,
3170 [CLKID_VPU] = &meson8b_vpu.hw,
3171 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
3172 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
3173 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
3174 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
3175 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
3176 [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
3177 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
3178 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
3179 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
3180 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
3181 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
3182 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
3183 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
3184 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
3185 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
3186 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
3187 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
3188 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
3189 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
3190 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
3191 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
3192 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
3193 [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
3194 [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
3195 [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
3196 };
3197
3198 static struct clk_hw *meson8m2_hw_clks[] = {
3199 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3200 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3201 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3202 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3203 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3204 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3205 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3206 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3207 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3208 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
3209 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
3210 [CLKID_CLK81] = &meson8b_clk81.hw,
3211 [CLKID_DDR] = &meson8b_ddr.hw,
3212 [CLKID_DOS] = &meson8b_dos.hw,
3213 [CLKID_ISA] = &meson8b_isa.hw,
3214 [CLKID_PL301] = &meson8b_pl301.hw,
3215 [CLKID_PERIPHS] = &meson8b_periphs.hw,
3216 [CLKID_SPICC] = &meson8b_spicc.hw,
3217 [CLKID_I2C] = &meson8b_i2c.hw,
3218 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
3219 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
3220 [CLKID_RNG0] = &meson8b_rng0.hw,
3221 [CLKID_UART0] = &meson8b_uart0.hw,
3222 [CLKID_SDHC] = &meson8b_sdhc.hw,
3223 [CLKID_STREAM] = &meson8b_stream.hw,
3224 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
3225 [CLKID_SDIO] = &meson8b_sdio.hw,
3226 [CLKID_ABUF] = &meson8b_abuf.hw,
3227 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
3228 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
3229 [CLKID_SPI] = &meson8b_spi.hw,
3230 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
3231 [CLKID_ETH] = &meson8b_eth.hw,
3232 [CLKID_DEMUX] = &meson8b_demux.hw,
3233 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
3234 [CLKID_IEC958] = &meson8b_iec958.hw,
3235 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
3236 [CLKID_AMCLK] = &meson8b_amclk.hw,
3237 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
3238 [CLKID_MIXER] = &meson8b_mixer.hw,
3239 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
3240 [CLKID_ADC] = &meson8b_adc.hw,
3241 [CLKID_BLKMV] = &meson8b_blkmv.hw,
3242 [CLKID_AIU] = &meson8b_aiu.hw,
3243 [CLKID_UART1] = &meson8b_uart1.hw,
3244 [CLKID_G2D] = &meson8b_g2d.hw,
3245 [CLKID_USB0] = &meson8b_usb0.hw,
3246 [CLKID_USB1] = &meson8b_usb1.hw,
3247 [CLKID_RESET] = &meson8b_reset.hw,
3248 [CLKID_NAND] = &meson8b_nand.hw,
3249 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
3250 [CLKID_USB] = &meson8b_usb.hw,
3251 [CLKID_VDIN1] = &meson8b_vdin1.hw,
3252 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
3253 [CLKID_EFUSE] = &meson8b_efuse.hw,
3254 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
3255 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
3256 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
3257 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
3258 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
3259 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
3260 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
3261 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
3262 [CLKID_DVIN] = &meson8b_dvin.hw,
3263 [CLKID_UART2] = &meson8b_uart2.hw,
3264 [CLKID_SANA] = &meson8b_sana.hw,
3265 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
3266 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
3267 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
3268 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
3269 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
3270 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
3271 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
3272 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
3273 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
3274 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
3275 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
3276 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
3277 [CLKID_ENC480P] = &meson8b_enc480p.hw,
3278 [CLKID_RNG1] = &meson8b_rng1.hw,
3279 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
3280 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
3281 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
3282 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
3283 [CLKID_EDP] = &meson8b_edp.hw,
3284 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
3285 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
3286 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
3287 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
3288 [CLKID_MPLL0] = &meson8b_mpll0.hw,
3289 [CLKID_MPLL1] = &meson8b_mpll1.hw,
3290 [CLKID_MPLL2] = &meson8b_mpll2.hw,
3291 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3292 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
3293 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
3294 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
3295 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
3296 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
3297 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
3298 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
3299 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
3300 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
3301 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
3302 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
3303 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
3304 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
3305 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
3306 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
3307 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
3308 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
3309 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
3310 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
3311 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
3312 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
3313 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
3314 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
3315 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
3316 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
3317 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
3318 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
3319 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
3320 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
3321 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
3322 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
3323 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
3324 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
3325 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
3326 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
3327 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
3328 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
3329 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
3330 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
3331 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
3332 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
3333 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
3334 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
3335 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
3336 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3337 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
3338 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3339 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
3340 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3341 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
3342 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3343 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
3344 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
3345 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
3346 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
3347 [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
3348 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3349 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
3350 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
3351 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
3352 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
3353 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
3354 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
3355 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
3356 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
3357 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
3358 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
3359 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
3360 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
3361 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
3362 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
3363 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
3364 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
3365 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
3366 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
3367 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
3368 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
3369 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
3370 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
3371 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
3372 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
3373 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
3374 [CLKID_MALI_0] = &meson8b_mali_0.hw,
3375 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
3376 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
3377 [CLKID_MALI_1] = &meson8b_mali_1.hw,
3378 [CLKID_MALI] = &meson8b_mali.hw,
3379 [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
3380 [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
3381 [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
3382 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
3383 [CLKID_VPU_0] = &meson8b_vpu_0.hw,
3384 [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
3385 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
3386 [CLKID_VPU_1] = &meson8b_vpu_1.hw,
3387 [CLKID_VPU] = &meson8b_vpu.hw,
3388 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
3389 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
3390 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
3391 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
3392 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
3393 [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
3394 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
3395 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
3396 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
3397 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
3398 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
3399 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
3400 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
3401 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
3402 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
3403 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
3404 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
3405 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
3406 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
3407 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
3408 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
3409 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
3410 [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
3411 [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
3412 [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
3413 };
3414
3415 static struct clk_regmap *const meson8b_clk_regmaps[] = {
3416 &meson8b_clk81,
3417 &meson8b_ddr,
3418 &meson8b_dos,
3419 &meson8b_isa,
3420 &meson8b_pl301,
3421 &meson8b_periphs,
3422 &meson8b_spicc,
3423 &meson8b_i2c,
3424 &meson8b_sar_adc,
3425 &meson8b_smart_card,
3426 &meson8b_rng0,
3427 &meson8b_uart0,
3428 &meson8b_sdhc,
3429 &meson8b_stream,
3430 &meson8b_async_fifo,
3431 &meson8b_sdio,
3432 &meson8b_abuf,
3433 &meson8b_hiu_iface,
3434 &meson8b_assist_misc,
3435 &meson8b_spi,
3436 &meson8b_i2s_spdif,
3437 &meson8b_eth,
3438 &meson8b_demux,
3439 &meson8b_aiu_glue,
3440 &meson8b_iec958,
3441 &meson8b_i2s_out,
3442 &meson8b_amclk,
3443 &meson8b_aififo2,
3444 &meson8b_mixer,
3445 &meson8b_mixer_iface,
3446 &meson8b_adc,
3447 &meson8b_blkmv,
3448 &meson8b_aiu,
3449 &meson8b_uart1,
3450 &meson8b_g2d,
3451 &meson8b_usb0,
3452 &meson8b_usb1,
3453 &meson8b_reset,
3454 &meson8b_nand,
3455 &meson8b_dos_parser,
3456 &meson8b_usb,
3457 &meson8b_vdin1,
3458 &meson8b_ahb_arb0,
3459 &meson8b_efuse,
3460 &meson8b_boot_rom,
3461 &meson8b_ahb_data_bus,
3462 &meson8b_ahb_ctrl_bus,
3463 &meson8b_hdmi_intr_sync,
3464 &meson8b_hdmi_pclk,
3465 &meson8b_usb1_ddr_bridge,
3466 &meson8b_usb0_ddr_bridge,
3467 &meson8b_mmc_pclk,
3468 &meson8b_dvin,
3469 &meson8b_uart2,
3470 &meson8b_sana,
3471 &meson8b_vpu_intr,
3472 &meson8b_sec_ahb_ahb3_bridge,
3473 &meson8b_clk81_a9,
3474 &meson8b_vclk2_venci0,
3475 &meson8b_vclk2_venci1,
3476 &meson8b_vclk2_vencp0,
3477 &meson8b_vclk2_vencp1,
3478 &meson8b_gclk_venci_int,
3479 &meson8b_gclk_vencp_int,
3480 &meson8b_dac_clk,
3481 &meson8b_aoclk_gate,
3482 &meson8b_iec958_gate,
3483 &meson8b_enc480p,
3484 &meson8b_rng1,
3485 &meson8b_gclk_vencl_int,
3486 &meson8b_vclk2_venclmcc,
3487 &meson8b_vclk2_vencl,
3488 &meson8b_vclk2_other,
3489 &meson8b_edp,
3490 &meson8b_ao_media_cpu,
3491 &meson8b_ao_ahb_sram,
3492 &meson8b_ao_ahb_bus,
3493 &meson8b_ao_iface,
3494 &meson8b_mpeg_clk_div,
3495 &meson8b_mpeg_clk_sel,
3496 &meson8b_mpll0,
3497 &meson8b_mpll1,
3498 &meson8b_mpll2,
3499 &meson8b_mpll0_div,
3500 &meson8b_mpll1_div,
3501 &meson8b_mpll2_div,
3502 &meson8b_fixed_pll,
3503 &meson8b_sys_pll,
3504 &meson8b_cpu_in_sel,
3505 &meson8b_cpu_scale_div,
3506 &meson8b_cpu_scale_out_sel,
3507 &meson8b_cpu_clk,
3508 &meson8b_mpll_prediv,
3509 &meson8b_fclk_div2,
3510 &meson8b_fclk_div3,
3511 &meson8b_fclk_div4,
3512 &meson8b_fclk_div5,
3513 &meson8b_fclk_div7,
3514 &meson8b_nand_clk_sel,
3515 &meson8b_nand_clk_div,
3516 &meson8b_nand_clk_gate,
3517 &meson8b_fixed_pll_dco,
3518 &meson8b_hdmi_pll_dco,
3519 &meson8b_sys_pll_dco,
3520 &meson8b_apb_clk_sel,
3521 &meson8b_apb_clk_gate,
3522 &meson8b_periph_clk_sel,
3523 &meson8b_periph_clk_gate,
3524 &meson8b_axi_clk_sel,
3525 &meson8b_axi_clk_gate,
3526 &meson8b_l2_dram_clk_sel,
3527 &meson8b_l2_dram_clk_gate,
3528 &meson8b_hdmi_pll_lvds_out,
3529 &meson8b_hdmi_pll_hdmi_out,
3530 &meson8b_vid_pll_in_sel,
3531 &meson8b_vid_pll_in_en,
3532 &meson8b_vid_pll_pre_div,
3533 &meson8b_vid_pll_post_div,
3534 &meson8b_vid_pll,
3535 &meson8b_vid_pll_final_div,
3536 &meson8b_vclk_in_sel,
3537 &meson8b_vclk_in_en,
3538 &meson8b_vclk_en,
3539 &meson8b_vclk_div1_gate,
3540 &meson8b_vclk_div2_div_gate,
3541 &meson8b_vclk_div4_div_gate,
3542 &meson8b_vclk_div6_div_gate,
3543 &meson8b_vclk_div12_div_gate,
3544 &meson8b_vclk2_in_sel,
3545 &meson8b_vclk2_clk_in_en,
3546 &meson8b_vclk2_clk_en,
3547 &meson8b_vclk2_div1_gate,
3548 &meson8b_vclk2_div2_div_gate,
3549 &meson8b_vclk2_div4_div_gate,
3550 &meson8b_vclk2_div6_div_gate,
3551 &meson8b_vclk2_div12_div_gate,
3552 &meson8b_cts_enct_sel,
3553 &meson8b_cts_enct,
3554 &meson8b_cts_encp_sel,
3555 &meson8b_cts_encp,
3556 &meson8b_cts_enci_sel,
3557 &meson8b_cts_enci,
3558 &meson8b_hdmi_tx_pixel_sel,
3559 &meson8b_hdmi_tx_pixel,
3560 &meson8b_cts_encl_sel,
3561 &meson8b_cts_encl,
3562 &meson8b_cts_vdac0_sel,
3563 &meson8b_cts_vdac0,
3564 &meson8b_hdmi_sys_sel,
3565 &meson8b_hdmi_sys_div,
3566 &meson8b_hdmi_sys,
3567 &meson8b_mali_0_sel,
3568 &meson8b_mali_0_div,
3569 &meson8b_mali_0,
3570 &meson8b_mali_1_sel,
3571 &meson8b_mali_1_div,
3572 &meson8b_mali_1,
3573 &meson8b_mali,
3574 &meson8m2_gp_pll_dco,
3575 &meson8m2_gp_pll,
3576 &meson8b_vpu_0_sel,
3577 &meson8m2_vpu_0_sel,
3578 &meson8b_vpu_0_div,
3579 &meson8b_vpu_0,
3580 &meson8b_vpu_1_sel,
3581 &meson8m2_vpu_1_sel,
3582 &meson8b_vpu_1_div,
3583 &meson8b_vpu_1,
3584 &meson8b_vpu,
3585 &meson8b_vdec_1_sel,
3586 &meson8b_vdec_1_1_div,
3587 &meson8b_vdec_1_1,
3588 &meson8b_vdec_1_2_div,
3589 &meson8b_vdec_1_2,
3590 &meson8b_vdec_1,
3591 &meson8b_vdec_hcodec_sel,
3592 &meson8b_vdec_hcodec_div,
3593 &meson8b_vdec_hcodec,
3594 &meson8b_vdec_2_sel,
3595 &meson8b_vdec_2_div,
3596 &meson8b_vdec_2,
3597 &meson8b_vdec_hevc_sel,
3598 &meson8b_vdec_hevc_div,
3599 &meson8b_vdec_hevc_en,
3600 &meson8b_vdec_hevc,
3601 &meson8b_cts_amclk,
3602 &meson8b_cts_amclk_sel,
3603 &meson8b_cts_amclk_div,
3604 &meson8b_cts_mclk_i958_sel,
3605 &meson8b_cts_mclk_i958_div,
3606 &meson8b_cts_mclk_i958,
3607 &meson8b_cts_i958,
3608 &meson8b_vid_pll_lvds_en,
3609 };
3610
3611 static const struct meson8b_clk_reset_line {
3612 u32 reg;
3613 u8 bit_idx;
3614 bool active_low;
3615 } meson8b_clk_reset_bits[] = {
3616 [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
3617 .reg = HHI_SYS_CPU_CLK_CNTL0,
3618 .bit_idx = 30,
3619 .active_low = false,
3620 },
3621 [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
3622 .reg = HHI_SYS_CPU_CLK_CNTL0,
3623 .bit_idx = 29,
3624 .active_low = false,
3625 },
3626 [CLKC_RESET_SCU_SOFT_RESET] = {
3627 .reg = HHI_SYS_CPU_CLK_CNTL0,
3628 .bit_idx = 28,
3629 .active_low = false,
3630 },
3631 [CLKC_RESET_CPU3_SOFT_RESET] = {
3632 .reg = HHI_SYS_CPU_CLK_CNTL0,
3633 .bit_idx = 27,
3634 .active_low = false,
3635 },
3636 [CLKC_RESET_CPU2_SOFT_RESET] = {
3637 .reg = HHI_SYS_CPU_CLK_CNTL0,
3638 .bit_idx = 26,
3639 .active_low = false,
3640 },
3641 [CLKC_RESET_CPU1_SOFT_RESET] = {
3642 .reg = HHI_SYS_CPU_CLK_CNTL0,
3643 .bit_idx = 25,
3644 .active_low = false,
3645 },
3646 [CLKC_RESET_CPU0_SOFT_RESET] = {
3647 .reg = HHI_SYS_CPU_CLK_CNTL0,
3648 .bit_idx = 24,
3649 .active_low = false,
3650 },
3651 [CLKC_RESET_A5_GLOBAL_RESET] = {
3652 .reg = HHI_SYS_CPU_CLK_CNTL0,
3653 .bit_idx = 18,
3654 .active_low = false,
3655 },
3656 [CLKC_RESET_A5_AXI_SOFT_RESET] = {
3657 .reg = HHI_SYS_CPU_CLK_CNTL0,
3658 .bit_idx = 17,
3659 .active_low = false,
3660 },
3661 [CLKC_RESET_A5_ABP_SOFT_RESET] = {
3662 .reg = HHI_SYS_CPU_CLK_CNTL0,
3663 .bit_idx = 16,
3664 .active_low = false,
3665 },
3666 [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
3667 .reg = HHI_SYS_CPU_CLK_CNTL1,
3668 .bit_idx = 30,
3669 .active_low = false,
3670 },
3671 [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
3672 .reg = HHI_VID_CLK_CNTL,
3673 .bit_idx = 15,
3674 .active_low = false,
3675 },
3676 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
3677 .reg = HHI_VID_DIVIDER_CNTL,
3678 .bit_idx = 7,
3679 .active_low = false,
3680 },
3681 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
3682 .reg = HHI_VID_DIVIDER_CNTL,
3683 .bit_idx = 3,
3684 .active_low = false,
3685 },
3686 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
3687 .reg = HHI_VID_DIVIDER_CNTL,
3688 .bit_idx = 1,
3689 .active_low = true,
3690 },
3691 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
3692 .reg = HHI_VID_DIVIDER_CNTL,
3693 .bit_idx = 0,
3694 .active_low = true,
3695 },
3696 };
3697
meson8b_clk_reset_update(struct reset_controller_dev * rcdev,unsigned long id,bool assert)3698 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
3699 unsigned long id, bool assert)
3700 {
3701 struct meson8b_clk_reset *meson8b_clk_reset =
3702 container_of(rcdev, struct meson8b_clk_reset, reset);
3703 const struct meson8b_clk_reset_line *reset;
3704 unsigned int value = 0;
3705 unsigned long flags;
3706
3707 if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
3708 return -EINVAL;
3709
3710 reset = &meson8b_clk_reset_bits[id];
3711
3712 if (assert != reset->active_low)
3713 value = BIT(reset->bit_idx);
3714
3715 spin_lock_irqsave(&meson_clk_lock, flags);
3716
3717 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
3718 BIT(reset->bit_idx), value);
3719
3720 spin_unlock_irqrestore(&meson_clk_lock, flags);
3721
3722 return 0;
3723 }
3724
meson8b_clk_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)3725 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
3726 unsigned long id)
3727 {
3728 return meson8b_clk_reset_update(rcdev, id, true);
3729 }
3730
meson8b_clk_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)3731 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
3732 unsigned long id)
3733 {
3734 return meson8b_clk_reset_update(rcdev, id, false);
3735 }
3736
3737 static const struct reset_control_ops meson8b_clk_reset_ops = {
3738 .assert = meson8b_clk_reset_assert,
3739 .deassert = meson8b_clk_reset_deassert,
3740 };
3741
3742 struct meson8b_nb_data {
3743 struct notifier_block nb;
3744 struct clk_hw *cpu_clk;
3745 };
3746
meson8b_cpu_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)3747 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
3748 unsigned long event, void *data)
3749 {
3750 struct meson8b_nb_data *nb_data =
3751 container_of(nb, struct meson8b_nb_data, nb);
3752 struct clk_hw *parent_clk;
3753 int ret;
3754
3755 switch (event) {
3756 case PRE_RATE_CHANGE:
3757 /* xtal */
3758 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
3759 break;
3760
3761 case POST_RATE_CHANGE:
3762 /* cpu_scale_out_sel */
3763 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
3764 break;
3765
3766 default:
3767 return NOTIFY_DONE;
3768 }
3769
3770 ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
3771 if (ret)
3772 return notifier_from_errno(ret);
3773
3774 udelay(100);
3775
3776 return NOTIFY_OK;
3777 }
3778
3779 static struct meson8b_nb_data meson8b_cpu_nb_data = {
3780 .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
3781 };
3782
3783 static struct meson_clk_hw_data meson8_clks = {
3784 .hws = meson8_hw_clks,
3785 .num = ARRAY_SIZE(meson8_hw_clks),
3786 };
3787
3788 static struct meson_clk_hw_data meson8b_clks = {
3789 .hws = meson8b_hw_clks,
3790 .num = ARRAY_SIZE(meson8b_hw_clks),
3791 };
3792
3793 static struct meson_clk_hw_data meson8m2_clks = {
3794 .hws = meson8m2_hw_clks,
3795 .num = ARRAY_SIZE(meson8m2_hw_clks),
3796 };
3797
meson8b_clkc_init_common(struct device_node * np,struct meson_clk_hw_data * hw_clks)3798 static void __init meson8b_clkc_init_common(struct device_node *np,
3799 struct meson_clk_hw_data *hw_clks)
3800 {
3801 struct meson8b_clk_reset *rstc;
3802 struct device_node *parent_np;
3803 const char *notifier_clk_name;
3804 struct clk *notifier_clk;
3805 struct regmap *map;
3806 int i, ret;
3807
3808 parent_np = of_get_parent(np);
3809 map = syscon_node_to_regmap(parent_np);
3810 of_node_put(parent_np);
3811 if (IS_ERR(map)) {
3812 pr_err("failed to get HHI regmap - Trying obsolete regs\n");
3813 return;
3814 }
3815
3816 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
3817 if (!rstc)
3818 return;
3819
3820 /* Reset Controller */
3821 rstc->regmap = map;
3822 rstc->reset.ops = &meson8b_clk_reset_ops;
3823 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
3824 rstc->reset.of_node = np;
3825 ret = reset_controller_register(&rstc->reset);
3826 if (ret) {
3827 pr_err("%s: Failed to register clkc reset controller: %d\n",
3828 __func__, ret);
3829 return;
3830 }
3831
3832 /* Populate regmap for the regmap backed clocks */
3833 for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
3834 meson8b_clk_regmaps[i]->map = map;
3835
3836 /*
3837 * register all clks and start with the first used ID (which is
3838 * CLKID_PLL_FIXED)
3839 */
3840 for (i = CLKID_PLL_FIXED; i < hw_clks->num; i++) {
3841 /* array might be sparse */
3842 if (!hw_clks->hws[i])
3843 continue;
3844
3845 ret = of_clk_hw_register(np, hw_clks->hws[i]);
3846 if (ret)
3847 return;
3848 }
3849
3850 meson8b_cpu_nb_data.cpu_clk = hw_clks->hws[CLKID_CPUCLK];
3851
3852 /*
3853 * FIXME we shouldn't program the muxes in notifier handlers. The
3854 * tricky programming sequence will be handled by the forthcoming
3855 * coordinated clock rates mechanism once that feature is released.
3856 */
3857 notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw);
3858 notifier_clk = __clk_lookup(notifier_clk_name);
3859 ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb);
3860 if (ret) {
3861 pr_err("%s: failed to register the CPU clock notifier\n",
3862 __func__);
3863 return;
3864 }
3865
3866 ret = of_clk_add_hw_provider(np, meson_clk_hw_get, hw_clks);
3867 if (ret)
3868 pr_err("%s: failed to register clock provider\n", __func__);
3869 }
3870
meson8_clkc_init(struct device_node * np)3871 static void __init meson8_clkc_init(struct device_node *np)
3872 {
3873 return meson8b_clkc_init_common(np, &meson8_clks);
3874 }
3875
meson8b_clkc_init(struct device_node * np)3876 static void __init meson8b_clkc_init(struct device_node *np)
3877 {
3878 return meson8b_clkc_init_common(np, &meson8b_clks);
3879 }
3880
meson8m2_clkc_init(struct device_node * np)3881 static void __init meson8m2_clkc_init(struct device_node *np)
3882 {
3883 return meson8b_clkc_init_common(np, &meson8m2_clks);
3884 }
3885
3886 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3887 meson8_clkc_init);
3888 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3889 meson8b_clkc_init);
3890 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
3891 meson8m2_clkc_init);
3892