1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 AmLogic, Inc. 4 * Michael Turquette <mturquette@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/init.h> 10 #include <linux/of_device.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include "clkc.h" 16 #include "gxbb.h" 17 #include "clk-regmap.h" 18 19 static DEFINE_SPINLOCK(meson_clk_lock); 20 21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 22 PLL_PARAMS(32, 1), 23 PLL_PARAMS(33, 1), 24 PLL_PARAMS(34, 1), 25 PLL_PARAMS(35, 1), 26 PLL_PARAMS(36, 1), 27 PLL_PARAMS(37, 1), 28 PLL_PARAMS(38, 1), 29 PLL_PARAMS(39, 1), 30 PLL_PARAMS(40, 1), 31 PLL_PARAMS(41, 1), 32 PLL_PARAMS(42, 1), 33 PLL_PARAMS(43, 1), 34 PLL_PARAMS(44, 1), 35 PLL_PARAMS(45, 1), 36 PLL_PARAMS(46, 1), 37 PLL_PARAMS(47, 1), 38 PLL_PARAMS(48, 1), 39 PLL_PARAMS(49, 1), 40 PLL_PARAMS(50, 1), 41 PLL_PARAMS(51, 1), 42 PLL_PARAMS(52, 1), 43 PLL_PARAMS(53, 1), 44 PLL_PARAMS(54, 1), 45 PLL_PARAMS(55, 1), 46 PLL_PARAMS(56, 1), 47 PLL_PARAMS(57, 1), 48 PLL_PARAMS(58, 1), 49 PLL_PARAMS(59, 1), 50 PLL_PARAMS(60, 1), 51 PLL_PARAMS(61, 1), 52 PLL_PARAMS(62, 1), 53 { /* sentinel */ }, 54 }; 55 56 static const struct pll_params_table gxl_gp0_pll_params_table[] = { 57 PLL_PARAMS(42, 1), 58 PLL_PARAMS(43, 1), 59 PLL_PARAMS(44, 1), 60 PLL_PARAMS(45, 1), 61 PLL_PARAMS(46, 1), 62 PLL_PARAMS(47, 1), 63 PLL_PARAMS(48, 1), 64 PLL_PARAMS(49, 1), 65 PLL_PARAMS(50, 1), 66 PLL_PARAMS(51, 1), 67 PLL_PARAMS(52, 1), 68 PLL_PARAMS(53, 1), 69 PLL_PARAMS(54, 1), 70 PLL_PARAMS(55, 1), 71 PLL_PARAMS(56, 1), 72 PLL_PARAMS(57, 1), 73 PLL_PARAMS(58, 1), 74 PLL_PARAMS(59, 1), 75 PLL_PARAMS(60, 1), 76 PLL_PARAMS(61, 1), 77 PLL_PARAMS(62, 1), 78 PLL_PARAMS(63, 1), 79 PLL_PARAMS(64, 1), 80 PLL_PARAMS(65, 1), 81 PLL_PARAMS(66, 1), 82 { /* sentinel */ }, 83 }; 84 85 static struct clk_regmap gxbb_fixed_pll_dco = { 86 .data = &(struct meson_clk_pll_data){ 87 .en = { 88 .reg_off = HHI_MPLL_CNTL, 89 .shift = 30, 90 .width = 1, 91 }, 92 .m = { 93 .reg_off = HHI_MPLL_CNTL, 94 .shift = 0, 95 .width = 9, 96 }, 97 .n = { 98 .reg_off = HHI_MPLL_CNTL, 99 .shift = 9, 100 .width = 5, 101 }, 102 .frac = { 103 .reg_off = HHI_MPLL_CNTL2, 104 .shift = 0, 105 .width = 12, 106 }, 107 .l = { 108 .reg_off = HHI_MPLL_CNTL, 109 .shift = 31, 110 .width = 1, 111 }, 112 .rst = { 113 .reg_off = HHI_MPLL_CNTL, 114 .shift = 29, 115 .width = 1, 116 }, 117 }, 118 .hw.init = &(struct clk_init_data){ 119 .name = "fixed_pll_dco", 120 .ops = &meson_clk_pll_ro_ops, 121 .parent_names = (const char *[]){ "xtal" }, 122 .num_parents = 1, 123 }, 124 }; 125 126 static struct clk_regmap gxbb_fixed_pll = { 127 .data = &(struct clk_regmap_div_data){ 128 .offset = HHI_MPLL_CNTL, 129 .shift = 16, 130 .width = 2, 131 .flags = CLK_DIVIDER_POWER_OF_TWO, 132 }, 133 .hw.init = &(struct clk_init_data){ 134 .name = "fixed_pll", 135 .ops = &clk_regmap_divider_ro_ops, 136 .parent_names = (const char *[]){ "fixed_pll_dco" }, 137 .num_parents = 1, 138 /* 139 * This clock won't ever change at runtime so 140 * CLK_SET_RATE_PARENT is not required 141 */ 142 }, 143 }; 144 145 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 146 .mult = 2, 147 .div = 1, 148 .hw.init = &(struct clk_init_data){ 149 .name = "hdmi_pll_pre_mult", 150 .ops = &clk_fixed_factor_ops, 151 .parent_names = (const char *[]){ "xtal" }, 152 .num_parents = 1, 153 }, 154 }; 155 156 static struct clk_regmap gxbb_hdmi_pll_dco = { 157 .data = &(struct meson_clk_pll_data){ 158 .en = { 159 .reg_off = HHI_HDMI_PLL_CNTL, 160 .shift = 30, 161 .width = 1, 162 }, 163 .m = { 164 .reg_off = HHI_HDMI_PLL_CNTL, 165 .shift = 0, 166 .width = 9, 167 }, 168 .n = { 169 .reg_off = HHI_HDMI_PLL_CNTL, 170 .shift = 9, 171 .width = 5, 172 }, 173 .frac = { 174 .reg_off = HHI_HDMI_PLL_CNTL2, 175 .shift = 0, 176 .width = 12, 177 }, 178 .l = { 179 .reg_off = HHI_HDMI_PLL_CNTL, 180 .shift = 31, 181 .width = 1, 182 }, 183 .rst = { 184 .reg_off = HHI_HDMI_PLL_CNTL, 185 .shift = 28, 186 .width = 1, 187 }, 188 }, 189 .hw.init = &(struct clk_init_data){ 190 .name = "hdmi_pll_dco", 191 .ops = &meson_clk_pll_ro_ops, 192 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" }, 193 .num_parents = 1, 194 /* 195 * Display directly handle hdmi pll registers ATM, we need 196 * NOCACHE to keep our view of the clock as accurate as possible 197 */ 198 .flags = CLK_GET_RATE_NOCACHE, 199 }, 200 }; 201 202 static struct clk_regmap gxl_hdmi_pll_dco = { 203 .data = &(struct meson_clk_pll_data){ 204 .en = { 205 .reg_off = HHI_HDMI_PLL_CNTL, 206 .shift = 30, 207 .width = 1, 208 }, 209 .m = { 210 .reg_off = HHI_HDMI_PLL_CNTL, 211 .shift = 0, 212 .width = 9, 213 }, 214 .n = { 215 .reg_off = HHI_HDMI_PLL_CNTL, 216 .shift = 9, 217 .width = 5, 218 }, 219 /* 220 * On gxl, there is a register shift due to 221 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 222 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB 223 * instead which is defined at the same offset. 224 */ 225 .frac = { 226 .reg_off = HHI_HDMI_PLL_CNTL2, 227 .shift = 0, 228 .width = 10, 229 }, 230 .l = { 231 .reg_off = HHI_HDMI_PLL_CNTL, 232 .shift = 31, 233 .width = 1, 234 }, 235 .rst = { 236 .reg_off = HHI_HDMI_PLL_CNTL, 237 .shift = 28, 238 .width = 1, 239 }, 240 }, 241 .hw.init = &(struct clk_init_data){ 242 .name = "hdmi_pll_dco", 243 .ops = &meson_clk_pll_ro_ops, 244 .parent_names = (const char *[]){ "xtal" }, 245 .num_parents = 1, 246 /* 247 * Display directly handle hdmi pll registers ATM, we need 248 * NOCACHE to keep our view of the clock as accurate as possible 249 */ 250 .flags = CLK_GET_RATE_NOCACHE, 251 }, 252 }; 253 254 static struct clk_regmap gxbb_hdmi_pll_od = { 255 .data = &(struct clk_regmap_div_data){ 256 .offset = HHI_HDMI_PLL_CNTL2, 257 .shift = 16, 258 .width = 2, 259 .flags = CLK_DIVIDER_POWER_OF_TWO, 260 }, 261 .hw.init = &(struct clk_init_data){ 262 .name = "hdmi_pll_od", 263 .ops = &clk_regmap_divider_ro_ops, 264 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 265 .num_parents = 1, 266 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 267 }, 268 }; 269 270 static struct clk_regmap gxbb_hdmi_pll_od2 = { 271 .data = &(struct clk_regmap_div_data){ 272 .offset = HHI_HDMI_PLL_CNTL2, 273 .shift = 22, 274 .width = 2, 275 .flags = CLK_DIVIDER_POWER_OF_TWO, 276 }, 277 .hw.init = &(struct clk_init_data){ 278 .name = "hdmi_pll_od2", 279 .ops = &clk_regmap_divider_ro_ops, 280 .parent_names = (const char *[]){ "hdmi_pll_od" }, 281 .num_parents = 1, 282 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 283 }, 284 }; 285 286 static struct clk_regmap gxbb_hdmi_pll = { 287 .data = &(struct clk_regmap_div_data){ 288 .offset = HHI_HDMI_PLL_CNTL2, 289 .shift = 18, 290 .width = 2, 291 .flags = CLK_DIVIDER_POWER_OF_TWO, 292 }, 293 .hw.init = &(struct clk_init_data){ 294 .name = "hdmi_pll", 295 .ops = &clk_regmap_divider_ro_ops, 296 .parent_names = (const char *[]){ "hdmi_pll_od2" }, 297 .num_parents = 1, 298 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 299 }, 300 }; 301 302 static struct clk_regmap gxl_hdmi_pll_od = { 303 .data = &(struct clk_regmap_div_data){ 304 .offset = HHI_HDMI_PLL_CNTL + 8, 305 .shift = 21, 306 .width = 2, 307 .flags = CLK_DIVIDER_POWER_OF_TWO, 308 }, 309 .hw.init = &(struct clk_init_data){ 310 .name = "hdmi_pll_od", 311 .ops = &clk_regmap_divider_ro_ops, 312 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 313 .num_parents = 1, 314 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 315 }, 316 }; 317 318 static struct clk_regmap gxl_hdmi_pll_od2 = { 319 .data = &(struct clk_regmap_div_data){ 320 .offset = HHI_HDMI_PLL_CNTL + 8, 321 .shift = 23, 322 .width = 2, 323 .flags = CLK_DIVIDER_POWER_OF_TWO, 324 }, 325 .hw.init = &(struct clk_init_data){ 326 .name = "hdmi_pll_od2", 327 .ops = &clk_regmap_divider_ro_ops, 328 .parent_names = (const char *[]){ "hdmi_pll_od" }, 329 .num_parents = 1, 330 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 331 }, 332 }; 333 334 static struct clk_regmap gxl_hdmi_pll = { 335 .data = &(struct clk_regmap_div_data){ 336 .offset = HHI_HDMI_PLL_CNTL + 8, 337 .shift = 19, 338 .width = 2, 339 .flags = CLK_DIVIDER_POWER_OF_TWO, 340 }, 341 .hw.init = &(struct clk_init_data){ 342 .name = "hdmi_pll", 343 .ops = &clk_regmap_divider_ro_ops, 344 .parent_names = (const char *[]){ "hdmi_pll_od2" }, 345 .num_parents = 1, 346 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 347 }, 348 }; 349 350 static struct clk_regmap gxbb_sys_pll_dco = { 351 .data = &(struct meson_clk_pll_data){ 352 .en = { 353 .reg_off = HHI_SYS_PLL_CNTL, 354 .shift = 30, 355 .width = 1, 356 }, 357 .m = { 358 .reg_off = HHI_SYS_PLL_CNTL, 359 .shift = 0, 360 .width = 9, 361 }, 362 .n = { 363 .reg_off = HHI_SYS_PLL_CNTL, 364 .shift = 9, 365 .width = 5, 366 }, 367 .l = { 368 .reg_off = HHI_SYS_PLL_CNTL, 369 .shift = 31, 370 .width = 1, 371 }, 372 .rst = { 373 .reg_off = HHI_SYS_PLL_CNTL, 374 .shift = 29, 375 .width = 1, 376 }, 377 }, 378 .hw.init = &(struct clk_init_data){ 379 .name = "sys_pll_dco", 380 .ops = &meson_clk_pll_ro_ops, 381 .parent_names = (const char *[]){ "xtal" }, 382 .num_parents = 1, 383 }, 384 }; 385 386 static struct clk_regmap gxbb_sys_pll = { 387 .data = &(struct clk_regmap_div_data){ 388 .offset = HHI_SYS_PLL_CNTL, 389 .shift = 10, 390 .width = 2, 391 .flags = CLK_DIVIDER_POWER_OF_TWO, 392 }, 393 .hw.init = &(struct clk_init_data){ 394 .name = "sys_pll", 395 .ops = &clk_regmap_divider_ro_ops, 396 .parent_names = (const char *[]){ "sys_pll_dco" }, 397 .num_parents = 1, 398 .flags = CLK_SET_RATE_PARENT, 399 }, 400 }; 401 402 static const struct reg_sequence gxbb_gp0_init_regs[] = { 403 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 404 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 405 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 406 }; 407 408 static struct clk_regmap gxbb_gp0_pll_dco = { 409 .data = &(struct meson_clk_pll_data){ 410 .en = { 411 .reg_off = HHI_GP0_PLL_CNTL, 412 .shift = 30, 413 .width = 1, 414 }, 415 .m = { 416 .reg_off = HHI_GP0_PLL_CNTL, 417 .shift = 0, 418 .width = 9, 419 }, 420 .n = { 421 .reg_off = HHI_GP0_PLL_CNTL, 422 .shift = 9, 423 .width = 5, 424 }, 425 .l = { 426 .reg_off = HHI_GP0_PLL_CNTL, 427 .shift = 31, 428 .width = 1, 429 }, 430 .rst = { 431 .reg_off = HHI_GP0_PLL_CNTL, 432 .shift = 29, 433 .width = 1, 434 }, 435 .table = gxbb_gp0_pll_params_table, 436 .init_regs = gxbb_gp0_init_regs, 437 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), 438 }, 439 .hw.init = &(struct clk_init_data){ 440 .name = "gp0_pll_dco", 441 .ops = &meson_clk_pll_ops, 442 .parent_names = (const char *[]){ "xtal" }, 443 .num_parents = 1, 444 }, 445 }; 446 447 static const struct reg_sequence gxl_gp0_init_regs[] = { 448 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 449 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 450 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 451 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 452 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 453 }; 454 455 static struct clk_regmap gxl_gp0_pll_dco = { 456 .data = &(struct meson_clk_pll_data){ 457 .en = { 458 .reg_off = HHI_GP0_PLL_CNTL, 459 .shift = 30, 460 .width = 1, 461 }, 462 .m = { 463 .reg_off = HHI_GP0_PLL_CNTL, 464 .shift = 0, 465 .width = 9, 466 }, 467 .n = { 468 .reg_off = HHI_GP0_PLL_CNTL, 469 .shift = 9, 470 .width = 5, 471 }, 472 .frac = { 473 .reg_off = HHI_GP0_PLL_CNTL1, 474 .shift = 0, 475 .width = 10, 476 }, 477 .l = { 478 .reg_off = HHI_GP0_PLL_CNTL, 479 .shift = 31, 480 .width = 1, 481 }, 482 .rst = { 483 .reg_off = HHI_GP0_PLL_CNTL, 484 .shift = 29, 485 .width = 1, 486 }, 487 .table = gxl_gp0_pll_params_table, 488 .init_regs = gxl_gp0_init_regs, 489 .init_count = ARRAY_SIZE(gxl_gp0_init_regs), 490 }, 491 .hw.init = &(struct clk_init_data){ 492 .name = "gp0_pll_dco", 493 .ops = &meson_clk_pll_ops, 494 .parent_names = (const char *[]){ "xtal" }, 495 .num_parents = 1, 496 }, 497 }; 498 499 static struct clk_regmap gxbb_gp0_pll = { 500 .data = &(struct clk_regmap_div_data){ 501 .offset = HHI_GP0_PLL_CNTL, 502 .shift = 16, 503 .width = 2, 504 .flags = CLK_DIVIDER_POWER_OF_TWO, 505 }, 506 .hw.init = &(struct clk_init_data){ 507 .name = "gp0_pll", 508 .ops = &clk_regmap_divider_ops, 509 .parent_names = (const char *[]){ "gp0_pll_dco" }, 510 .num_parents = 1, 511 .flags = CLK_SET_RATE_PARENT, 512 }, 513 }; 514 515 static struct clk_fixed_factor gxbb_fclk_div2_div = { 516 .mult = 1, 517 .div = 2, 518 .hw.init = &(struct clk_init_data){ 519 .name = "fclk_div2_div", 520 .ops = &clk_fixed_factor_ops, 521 .parent_names = (const char *[]){ "fixed_pll" }, 522 .num_parents = 1, 523 }, 524 }; 525 526 static struct clk_regmap gxbb_fclk_div2 = { 527 .data = &(struct clk_regmap_gate_data){ 528 .offset = HHI_MPLL_CNTL6, 529 .bit_idx = 27, 530 }, 531 .hw.init = &(struct clk_init_data){ 532 .name = "fclk_div2", 533 .ops = &clk_regmap_gate_ops, 534 .parent_names = (const char *[]){ "fclk_div2_div" }, 535 .num_parents = 1, 536 .flags = CLK_IS_CRITICAL, 537 }, 538 }; 539 540 static struct clk_fixed_factor gxbb_fclk_div3_div = { 541 .mult = 1, 542 .div = 3, 543 .hw.init = &(struct clk_init_data){ 544 .name = "fclk_div3_div", 545 .ops = &clk_fixed_factor_ops, 546 .parent_names = (const char *[]){ "fixed_pll" }, 547 .num_parents = 1, 548 }, 549 }; 550 551 static struct clk_regmap gxbb_fclk_div3 = { 552 .data = &(struct clk_regmap_gate_data){ 553 .offset = HHI_MPLL_CNTL6, 554 .bit_idx = 28, 555 }, 556 .hw.init = &(struct clk_init_data){ 557 .name = "fclk_div3", 558 .ops = &clk_regmap_gate_ops, 559 .parent_names = (const char *[]){ "fclk_div3_div" }, 560 .num_parents = 1, 561 /* 562 * FIXME: 563 * This clock, as fdiv2, is used by the SCPI FW and is required 564 * by the platform to operate correctly. 565 * Until the following condition are met, we need this clock to 566 * be marked as critical: 567 * a) The SCPI generic driver claims and enable all the clocks 568 * it needs 569 * b) CCF has a clock hand-off mechanism to make the sure the 570 * clock stays on until the proper driver comes along 571 */ 572 .flags = CLK_IS_CRITICAL, 573 }, 574 }; 575 576 static struct clk_fixed_factor gxbb_fclk_div4_div = { 577 .mult = 1, 578 .div = 4, 579 .hw.init = &(struct clk_init_data){ 580 .name = "fclk_div4_div", 581 .ops = &clk_fixed_factor_ops, 582 .parent_names = (const char *[]){ "fixed_pll" }, 583 .num_parents = 1, 584 }, 585 }; 586 587 static struct clk_regmap gxbb_fclk_div4 = { 588 .data = &(struct clk_regmap_gate_data){ 589 .offset = HHI_MPLL_CNTL6, 590 .bit_idx = 29, 591 }, 592 .hw.init = &(struct clk_init_data){ 593 .name = "fclk_div4", 594 .ops = &clk_regmap_gate_ops, 595 .parent_names = (const char *[]){ "fclk_div4_div" }, 596 .num_parents = 1, 597 }, 598 }; 599 600 static struct clk_fixed_factor gxbb_fclk_div5_div = { 601 .mult = 1, 602 .div = 5, 603 .hw.init = &(struct clk_init_data){ 604 .name = "fclk_div5_div", 605 .ops = &clk_fixed_factor_ops, 606 .parent_names = (const char *[]){ "fixed_pll" }, 607 .num_parents = 1, 608 }, 609 }; 610 611 static struct clk_regmap gxbb_fclk_div5 = { 612 .data = &(struct clk_regmap_gate_data){ 613 .offset = HHI_MPLL_CNTL6, 614 .bit_idx = 30, 615 }, 616 .hw.init = &(struct clk_init_data){ 617 .name = "fclk_div5", 618 .ops = &clk_regmap_gate_ops, 619 .parent_names = (const char *[]){ "fclk_div5_div" }, 620 .num_parents = 1, 621 }, 622 }; 623 624 static struct clk_fixed_factor gxbb_fclk_div7_div = { 625 .mult = 1, 626 .div = 7, 627 .hw.init = &(struct clk_init_data){ 628 .name = "fclk_div7_div", 629 .ops = &clk_fixed_factor_ops, 630 .parent_names = (const char *[]){ "fixed_pll" }, 631 .num_parents = 1, 632 }, 633 }; 634 635 static struct clk_regmap gxbb_fclk_div7 = { 636 .data = &(struct clk_regmap_gate_data){ 637 .offset = HHI_MPLL_CNTL6, 638 .bit_idx = 31, 639 }, 640 .hw.init = &(struct clk_init_data){ 641 .name = "fclk_div7", 642 .ops = &clk_regmap_gate_ops, 643 .parent_names = (const char *[]){ "fclk_div7_div" }, 644 .num_parents = 1, 645 }, 646 }; 647 648 static struct clk_regmap gxbb_mpll_prediv = { 649 .data = &(struct clk_regmap_div_data){ 650 .offset = HHI_MPLL_CNTL5, 651 .shift = 12, 652 .width = 1, 653 }, 654 .hw.init = &(struct clk_init_data){ 655 .name = "mpll_prediv", 656 .ops = &clk_regmap_divider_ro_ops, 657 .parent_names = (const char *[]){ "fixed_pll" }, 658 .num_parents = 1, 659 }, 660 }; 661 662 static struct clk_regmap gxbb_mpll0_div = { 663 .data = &(struct meson_clk_mpll_data){ 664 .sdm = { 665 .reg_off = HHI_MPLL_CNTL7, 666 .shift = 0, 667 .width = 14, 668 }, 669 .sdm_en = { 670 .reg_off = HHI_MPLL_CNTL7, 671 .shift = 15, 672 .width = 1, 673 }, 674 .n2 = { 675 .reg_off = HHI_MPLL_CNTL7, 676 .shift = 16, 677 .width = 9, 678 }, 679 .ssen = { 680 .reg_off = HHI_MPLL_CNTL, 681 .shift = 25, 682 .width = 1, 683 }, 684 .lock = &meson_clk_lock, 685 }, 686 .hw.init = &(struct clk_init_data){ 687 .name = "mpll0_div", 688 .ops = &meson_clk_mpll_ops, 689 .parent_names = (const char *[]){ "mpll_prediv" }, 690 .num_parents = 1, 691 }, 692 }; 693 694 static struct clk_regmap gxbb_mpll0 = { 695 .data = &(struct clk_regmap_gate_data){ 696 .offset = HHI_MPLL_CNTL7, 697 .bit_idx = 14, 698 }, 699 .hw.init = &(struct clk_init_data){ 700 .name = "mpll0", 701 .ops = &clk_regmap_gate_ops, 702 .parent_names = (const char *[]){ "mpll0_div" }, 703 .num_parents = 1, 704 .flags = CLK_SET_RATE_PARENT, 705 }, 706 }; 707 708 static struct clk_regmap gxbb_mpll1_div = { 709 .data = &(struct meson_clk_mpll_data){ 710 .sdm = { 711 .reg_off = HHI_MPLL_CNTL8, 712 .shift = 0, 713 .width = 14, 714 }, 715 .sdm_en = { 716 .reg_off = HHI_MPLL_CNTL8, 717 .shift = 15, 718 .width = 1, 719 }, 720 .n2 = { 721 .reg_off = HHI_MPLL_CNTL8, 722 .shift = 16, 723 .width = 9, 724 }, 725 .lock = &meson_clk_lock, 726 }, 727 .hw.init = &(struct clk_init_data){ 728 .name = "mpll1_div", 729 .ops = &meson_clk_mpll_ops, 730 .parent_names = (const char *[]){ "mpll_prediv" }, 731 .num_parents = 1, 732 }, 733 }; 734 735 static struct clk_regmap gxbb_mpll1 = { 736 .data = &(struct clk_regmap_gate_data){ 737 .offset = HHI_MPLL_CNTL8, 738 .bit_idx = 14, 739 }, 740 .hw.init = &(struct clk_init_data){ 741 .name = "mpll1", 742 .ops = &clk_regmap_gate_ops, 743 .parent_names = (const char *[]){ "mpll1_div" }, 744 .num_parents = 1, 745 .flags = CLK_SET_RATE_PARENT, 746 }, 747 }; 748 749 static struct clk_regmap gxbb_mpll2_div = { 750 .data = &(struct meson_clk_mpll_data){ 751 .sdm = { 752 .reg_off = HHI_MPLL_CNTL9, 753 .shift = 0, 754 .width = 14, 755 }, 756 .sdm_en = { 757 .reg_off = HHI_MPLL_CNTL9, 758 .shift = 15, 759 .width = 1, 760 }, 761 .n2 = { 762 .reg_off = HHI_MPLL_CNTL9, 763 .shift = 16, 764 .width = 9, 765 }, 766 .lock = &meson_clk_lock, 767 }, 768 .hw.init = &(struct clk_init_data){ 769 .name = "mpll2_div", 770 .ops = &meson_clk_mpll_ops, 771 .parent_names = (const char *[]){ "mpll_prediv" }, 772 .num_parents = 1, 773 }, 774 }; 775 776 static struct clk_regmap gxbb_mpll2 = { 777 .data = &(struct clk_regmap_gate_data){ 778 .offset = HHI_MPLL_CNTL9, 779 .bit_idx = 14, 780 }, 781 .hw.init = &(struct clk_init_data){ 782 .name = "mpll2", 783 .ops = &clk_regmap_gate_ops, 784 .parent_names = (const char *[]){ "mpll2_div" }, 785 .num_parents = 1, 786 .flags = CLK_SET_RATE_PARENT, 787 }, 788 }; 789 790 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 791 static const char * const clk81_parent_names[] = { 792 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 793 "fclk_div3", "fclk_div5" 794 }; 795 796 static struct clk_regmap gxbb_mpeg_clk_sel = { 797 .data = &(struct clk_regmap_mux_data){ 798 .offset = HHI_MPEG_CLK_CNTL, 799 .mask = 0x7, 800 .shift = 12, 801 .table = mux_table_clk81, 802 }, 803 .hw.init = &(struct clk_init_data){ 804 .name = "mpeg_clk_sel", 805 .ops = &clk_regmap_mux_ro_ops, 806 /* 807 * bits 14:12 selects from 8 possible parents: 808 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 809 * fclk_div4, fclk_div3, fclk_div5 810 */ 811 .parent_names = clk81_parent_names, 812 .num_parents = ARRAY_SIZE(clk81_parent_names), 813 }, 814 }; 815 816 static struct clk_regmap gxbb_mpeg_clk_div = { 817 .data = &(struct clk_regmap_div_data){ 818 .offset = HHI_MPEG_CLK_CNTL, 819 .shift = 0, 820 .width = 7, 821 }, 822 .hw.init = &(struct clk_init_data){ 823 .name = "mpeg_clk_div", 824 .ops = &clk_regmap_divider_ro_ops, 825 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 826 .num_parents = 1, 827 }, 828 }; 829 830 /* the mother of dragons gates */ 831 static struct clk_regmap gxbb_clk81 = { 832 .data = &(struct clk_regmap_gate_data){ 833 .offset = HHI_MPEG_CLK_CNTL, 834 .bit_idx = 7, 835 }, 836 .hw.init = &(struct clk_init_data){ 837 .name = "clk81", 838 .ops = &clk_regmap_gate_ops, 839 .parent_names = (const char *[]){ "mpeg_clk_div" }, 840 .num_parents = 1, 841 .flags = CLK_IS_CRITICAL, 842 }, 843 }; 844 845 static struct clk_regmap gxbb_sar_adc_clk_sel = { 846 .data = &(struct clk_regmap_mux_data){ 847 .offset = HHI_SAR_CLK_CNTL, 848 .mask = 0x3, 849 .shift = 9, 850 }, 851 .hw.init = &(struct clk_init_data){ 852 .name = "sar_adc_clk_sel", 853 .ops = &clk_regmap_mux_ops, 854 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 855 .parent_names = (const char *[]){ "xtal", "clk81", }, 856 .num_parents = 2, 857 }, 858 }; 859 860 static struct clk_regmap gxbb_sar_adc_clk_div = { 861 .data = &(struct clk_regmap_div_data){ 862 .offset = HHI_SAR_CLK_CNTL, 863 .shift = 0, 864 .width = 8, 865 }, 866 .hw.init = &(struct clk_init_data){ 867 .name = "sar_adc_clk_div", 868 .ops = &clk_regmap_divider_ops, 869 .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 870 .num_parents = 1, 871 }, 872 }; 873 874 static struct clk_regmap gxbb_sar_adc_clk = { 875 .data = &(struct clk_regmap_gate_data){ 876 .offset = HHI_SAR_CLK_CNTL, 877 .bit_idx = 8, 878 }, 879 .hw.init = &(struct clk_init_data){ 880 .name = "sar_adc_clk", 881 .ops = &clk_regmap_gate_ops, 882 .parent_names = (const char *[]){ "sar_adc_clk_div" }, 883 .num_parents = 1, 884 .flags = CLK_SET_RATE_PARENT, 885 }, 886 }; 887 888 /* 889 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 890 * muxed by a glitch-free switch. 891 */ 892 893 static const char * const gxbb_mali_0_1_parent_names[] = { 894 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 895 "fclk_div4", "fclk_div3", "fclk_div5" 896 }; 897 898 static struct clk_regmap gxbb_mali_0_sel = { 899 .data = &(struct clk_regmap_mux_data){ 900 .offset = HHI_MALI_CLK_CNTL, 901 .mask = 0x7, 902 .shift = 9, 903 }, 904 .hw.init = &(struct clk_init_data){ 905 .name = "mali_0_sel", 906 .ops = &clk_regmap_mux_ops, 907 /* 908 * bits 10:9 selects from 8 possible parents: 909 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 910 * fclk_div4, fclk_div3, fclk_div5 911 */ 912 .parent_names = gxbb_mali_0_1_parent_names, 913 .num_parents = 8, 914 .flags = CLK_SET_RATE_NO_REPARENT, 915 }, 916 }; 917 918 static struct clk_regmap gxbb_mali_0_div = { 919 .data = &(struct clk_regmap_div_data){ 920 .offset = HHI_MALI_CLK_CNTL, 921 .shift = 0, 922 .width = 7, 923 }, 924 .hw.init = &(struct clk_init_data){ 925 .name = "mali_0_div", 926 .ops = &clk_regmap_divider_ops, 927 .parent_names = (const char *[]){ "mali_0_sel" }, 928 .num_parents = 1, 929 .flags = CLK_SET_RATE_NO_REPARENT, 930 }, 931 }; 932 933 static struct clk_regmap gxbb_mali_0 = { 934 .data = &(struct clk_regmap_gate_data){ 935 .offset = HHI_MALI_CLK_CNTL, 936 .bit_idx = 8, 937 }, 938 .hw.init = &(struct clk_init_data){ 939 .name = "mali_0", 940 .ops = &clk_regmap_gate_ops, 941 .parent_names = (const char *[]){ "mali_0_div" }, 942 .num_parents = 1, 943 .flags = CLK_SET_RATE_PARENT, 944 }, 945 }; 946 947 static struct clk_regmap gxbb_mali_1_sel = { 948 .data = &(struct clk_regmap_mux_data){ 949 .offset = HHI_MALI_CLK_CNTL, 950 .mask = 0x7, 951 .shift = 25, 952 }, 953 .hw.init = &(struct clk_init_data){ 954 .name = "mali_1_sel", 955 .ops = &clk_regmap_mux_ops, 956 /* 957 * bits 10:9 selects from 8 possible parents: 958 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 959 * fclk_div4, fclk_div3, fclk_div5 960 */ 961 .parent_names = gxbb_mali_0_1_parent_names, 962 .num_parents = 8, 963 .flags = CLK_SET_RATE_NO_REPARENT, 964 }, 965 }; 966 967 static struct clk_regmap gxbb_mali_1_div = { 968 .data = &(struct clk_regmap_div_data){ 969 .offset = HHI_MALI_CLK_CNTL, 970 .shift = 16, 971 .width = 7, 972 }, 973 .hw.init = &(struct clk_init_data){ 974 .name = "mali_1_div", 975 .ops = &clk_regmap_divider_ops, 976 .parent_names = (const char *[]){ "mali_1_sel" }, 977 .num_parents = 1, 978 .flags = CLK_SET_RATE_NO_REPARENT, 979 }, 980 }; 981 982 static struct clk_regmap gxbb_mali_1 = { 983 .data = &(struct clk_regmap_gate_data){ 984 .offset = HHI_MALI_CLK_CNTL, 985 .bit_idx = 24, 986 }, 987 .hw.init = &(struct clk_init_data){ 988 .name = "mali_1", 989 .ops = &clk_regmap_gate_ops, 990 .parent_names = (const char *[]){ "mali_1_div" }, 991 .num_parents = 1, 992 .flags = CLK_SET_RATE_PARENT, 993 }, 994 }; 995 996 static const char * const gxbb_mali_parent_names[] = { 997 "mali_0", "mali_1" 998 }; 999 1000 static struct clk_regmap gxbb_mali = { 1001 .data = &(struct clk_regmap_mux_data){ 1002 .offset = HHI_MALI_CLK_CNTL, 1003 .mask = 1, 1004 .shift = 31, 1005 }, 1006 .hw.init = &(struct clk_init_data){ 1007 .name = "mali", 1008 .ops = &clk_regmap_mux_ops, 1009 .parent_names = gxbb_mali_parent_names, 1010 .num_parents = 2, 1011 .flags = CLK_SET_RATE_NO_REPARENT, 1012 }, 1013 }; 1014 1015 static struct clk_regmap gxbb_cts_amclk_sel = { 1016 .data = &(struct clk_regmap_mux_data){ 1017 .offset = HHI_AUD_CLK_CNTL, 1018 .mask = 0x3, 1019 .shift = 9, 1020 .table = (u32[]){ 1, 2, 3 }, 1021 .flags = CLK_MUX_ROUND_CLOSEST, 1022 }, 1023 .hw.init = &(struct clk_init_data){ 1024 .name = "cts_amclk_sel", 1025 .ops = &clk_regmap_mux_ops, 1026 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 1027 .num_parents = 3, 1028 }, 1029 }; 1030 1031 static struct clk_regmap gxbb_cts_amclk_div = { 1032 .data = &(struct clk_regmap_div_data) { 1033 .offset = HHI_AUD_CLK_CNTL, 1034 .shift = 0, 1035 .width = 8, 1036 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1037 }, 1038 .hw.init = &(struct clk_init_data){ 1039 .name = "cts_amclk_div", 1040 .ops = &clk_regmap_divider_ops, 1041 .parent_names = (const char *[]){ "cts_amclk_sel" }, 1042 .num_parents = 1, 1043 .flags = CLK_SET_RATE_PARENT, 1044 }, 1045 }; 1046 1047 static struct clk_regmap gxbb_cts_amclk = { 1048 .data = &(struct clk_regmap_gate_data){ 1049 .offset = HHI_AUD_CLK_CNTL, 1050 .bit_idx = 8, 1051 }, 1052 .hw.init = &(struct clk_init_data){ 1053 .name = "cts_amclk", 1054 .ops = &clk_regmap_gate_ops, 1055 .parent_names = (const char *[]){ "cts_amclk_div" }, 1056 .num_parents = 1, 1057 .flags = CLK_SET_RATE_PARENT, 1058 }, 1059 }; 1060 1061 static struct clk_regmap gxbb_cts_mclk_i958_sel = { 1062 .data = &(struct clk_regmap_mux_data){ 1063 .offset = HHI_AUD_CLK_CNTL2, 1064 .mask = 0x3, 1065 .shift = 25, 1066 .table = (u32[]){ 1, 2, 3 }, 1067 .flags = CLK_MUX_ROUND_CLOSEST, 1068 }, 1069 .hw.init = &(struct clk_init_data) { 1070 .name = "cts_mclk_i958_sel", 1071 .ops = &clk_regmap_mux_ops, 1072 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 1073 .num_parents = 3, 1074 }, 1075 }; 1076 1077 static struct clk_regmap gxbb_cts_mclk_i958_div = { 1078 .data = &(struct clk_regmap_div_data){ 1079 .offset = HHI_AUD_CLK_CNTL2, 1080 .shift = 16, 1081 .width = 8, 1082 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1083 }, 1084 .hw.init = &(struct clk_init_data) { 1085 .name = "cts_mclk_i958_div", 1086 .ops = &clk_regmap_divider_ops, 1087 .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 1088 .num_parents = 1, 1089 .flags = CLK_SET_RATE_PARENT, 1090 }, 1091 }; 1092 1093 static struct clk_regmap gxbb_cts_mclk_i958 = { 1094 .data = &(struct clk_regmap_gate_data){ 1095 .offset = HHI_AUD_CLK_CNTL2, 1096 .bit_idx = 24, 1097 }, 1098 .hw.init = &(struct clk_init_data){ 1099 .name = "cts_mclk_i958", 1100 .ops = &clk_regmap_gate_ops, 1101 .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 1102 .num_parents = 1, 1103 .flags = CLK_SET_RATE_PARENT, 1104 }, 1105 }; 1106 1107 static struct clk_regmap gxbb_cts_i958 = { 1108 .data = &(struct clk_regmap_mux_data){ 1109 .offset = HHI_AUD_CLK_CNTL2, 1110 .mask = 0x1, 1111 .shift = 27, 1112 }, 1113 .hw.init = &(struct clk_init_data){ 1114 .name = "cts_i958", 1115 .ops = &clk_regmap_mux_ops, 1116 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 1117 .num_parents = 2, 1118 /* 1119 *The parent is specific to origin of the audio data. Let the 1120 * consumer choose the appropriate parent 1121 */ 1122 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1123 }, 1124 }; 1125 1126 static struct clk_regmap gxbb_32k_clk_div = { 1127 .data = &(struct clk_regmap_div_data){ 1128 .offset = HHI_32K_CLK_CNTL, 1129 .shift = 0, 1130 .width = 14, 1131 }, 1132 .hw.init = &(struct clk_init_data){ 1133 .name = "32k_clk_div", 1134 .ops = &clk_regmap_divider_ops, 1135 .parent_names = (const char *[]){ "32k_clk_sel" }, 1136 .num_parents = 1, 1137 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 1138 }, 1139 }; 1140 1141 static struct clk_regmap gxbb_32k_clk = { 1142 .data = &(struct clk_regmap_gate_data){ 1143 .offset = HHI_32K_CLK_CNTL, 1144 .bit_idx = 15, 1145 }, 1146 .hw.init = &(struct clk_init_data){ 1147 .name = "32k_clk", 1148 .ops = &clk_regmap_gate_ops, 1149 .parent_names = (const char *[]){ "32k_clk_div" }, 1150 .num_parents = 1, 1151 .flags = CLK_SET_RATE_PARENT, 1152 }, 1153 }; 1154 1155 static const char * const gxbb_32k_clk_parent_names[] = { 1156 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" 1157 }; 1158 1159 static struct clk_regmap gxbb_32k_clk_sel = { 1160 .data = &(struct clk_regmap_mux_data){ 1161 .offset = HHI_32K_CLK_CNTL, 1162 .mask = 0x3, 1163 .shift = 16, 1164 }, 1165 .hw.init = &(struct clk_init_data){ 1166 .name = "32k_clk_sel", 1167 .ops = &clk_regmap_mux_ops, 1168 .parent_names = gxbb_32k_clk_parent_names, 1169 .num_parents = 4, 1170 .flags = CLK_SET_RATE_PARENT, 1171 }, 1172 }; 1173 1174 static const char * const gxbb_sd_emmc_clk0_parent_names[] = { 1175 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 1176 1177 /* 1178 * Following these parent clocks, we should also have had mpll2, mpll3 1179 * and gp0_pll but these clocks are too precious to be used here. All 1180 * the necessary rates for MMC and NAND operation can be acheived using 1181 * xtal or fclk_div clocks 1182 */ 1183 }; 1184 1185 /* SDIO clock */ 1186 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 1187 .data = &(struct clk_regmap_mux_data){ 1188 .offset = HHI_SD_EMMC_CLK_CNTL, 1189 .mask = 0x7, 1190 .shift = 9, 1191 }, 1192 .hw.init = &(struct clk_init_data) { 1193 .name = "sd_emmc_a_clk0_sel", 1194 .ops = &clk_regmap_mux_ops, 1195 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1196 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1197 .flags = CLK_SET_RATE_PARENT, 1198 }, 1199 }; 1200 1201 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1202 .data = &(struct clk_regmap_div_data){ 1203 .offset = HHI_SD_EMMC_CLK_CNTL, 1204 .shift = 0, 1205 .width = 7, 1206 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1207 }, 1208 .hw.init = &(struct clk_init_data) { 1209 .name = "sd_emmc_a_clk0_div", 1210 .ops = &clk_regmap_divider_ops, 1211 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, 1212 .num_parents = 1, 1213 .flags = CLK_SET_RATE_PARENT, 1214 }, 1215 }; 1216 1217 static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 1218 .data = &(struct clk_regmap_gate_data){ 1219 .offset = HHI_SD_EMMC_CLK_CNTL, 1220 .bit_idx = 7, 1221 }, 1222 .hw.init = &(struct clk_init_data){ 1223 .name = "sd_emmc_a_clk0", 1224 .ops = &clk_regmap_gate_ops, 1225 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, 1226 .num_parents = 1, 1227 .flags = CLK_SET_RATE_PARENT, 1228 }, 1229 }; 1230 1231 /* SDcard clock */ 1232 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 1233 .data = &(struct clk_regmap_mux_data){ 1234 .offset = HHI_SD_EMMC_CLK_CNTL, 1235 .mask = 0x7, 1236 .shift = 25, 1237 }, 1238 .hw.init = &(struct clk_init_data) { 1239 .name = "sd_emmc_b_clk0_sel", 1240 .ops = &clk_regmap_mux_ops, 1241 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1242 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1243 .flags = CLK_SET_RATE_PARENT, 1244 }, 1245 }; 1246 1247 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1248 .data = &(struct clk_regmap_div_data){ 1249 .offset = HHI_SD_EMMC_CLK_CNTL, 1250 .shift = 16, 1251 .width = 7, 1252 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1253 }, 1254 .hw.init = &(struct clk_init_data) { 1255 .name = "sd_emmc_b_clk0_div", 1256 .ops = &clk_regmap_divider_ops, 1257 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 1258 .num_parents = 1, 1259 .flags = CLK_SET_RATE_PARENT, 1260 }, 1261 }; 1262 1263 static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 1264 .data = &(struct clk_regmap_gate_data){ 1265 .offset = HHI_SD_EMMC_CLK_CNTL, 1266 .bit_idx = 23, 1267 }, 1268 .hw.init = &(struct clk_init_data){ 1269 .name = "sd_emmc_b_clk0", 1270 .ops = &clk_regmap_gate_ops, 1271 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 1272 .num_parents = 1, 1273 .flags = CLK_SET_RATE_PARENT, 1274 }, 1275 }; 1276 1277 /* EMMC/NAND clock */ 1278 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 1279 .data = &(struct clk_regmap_mux_data){ 1280 .offset = HHI_NAND_CLK_CNTL, 1281 .mask = 0x7, 1282 .shift = 9, 1283 }, 1284 .hw.init = &(struct clk_init_data) { 1285 .name = "sd_emmc_c_clk0_sel", 1286 .ops = &clk_regmap_mux_ops, 1287 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1288 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1289 .flags = CLK_SET_RATE_PARENT, 1290 }, 1291 }; 1292 1293 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1294 .data = &(struct clk_regmap_div_data){ 1295 .offset = HHI_NAND_CLK_CNTL, 1296 .shift = 0, 1297 .width = 7, 1298 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1299 }, 1300 .hw.init = &(struct clk_init_data) { 1301 .name = "sd_emmc_c_clk0_div", 1302 .ops = &clk_regmap_divider_ops, 1303 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 1304 .num_parents = 1, 1305 .flags = CLK_SET_RATE_PARENT, 1306 }, 1307 }; 1308 1309 static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 1310 .data = &(struct clk_regmap_gate_data){ 1311 .offset = HHI_NAND_CLK_CNTL, 1312 .bit_idx = 7, 1313 }, 1314 .hw.init = &(struct clk_init_data){ 1315 .name = "sd_emmc_c_clk0", 1316 .ops = &clk_regmap_gate_ops, 1317 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 1318 .num_parents = 1, 1319 .flags = CLK_SET_RATE_PARENT, 1320 }, 1321 }; 1322 1323 /* VPU Clock */ 1324 1325 static const char * const gxbb_vpu_parent_names[] = { 1326 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1327 }; 1328 1329 static struct clk_regmap gxbb_vpu_0_sel = { 1330 .data = &(struct clk_regmap_mux_data){ 1331 .offset = HHI_VPU_CLK_CNTL, 1332 .mask = 0x3, 1333 .shift = 9, 1334 }, 1335 .hw.init = &(struct clk_init_data){ 1336 .name = "vpu_0_sel", 1337 .ops = &clk_regmap_mux_ops, 1338 /* 1339 * bits 9:10 selects from 4 possible parents: 1340 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1341 */ 1342 .parent_names = gxbb_vpu_parent_names, 1343 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1344 .flags = CLK_SET_RATE_NO_REPARENT, 1345 }, 1346 }; 1347 1348 static struct clk_regmap gxbb_vpu_0_div = { 1349 .data = &(struct clk_regmap_div_data){ 1350 .offset = HHI_VPU_CLK_CNTL, 1351 .shift = 0, 1352 .width = 7, 1353 }, 1354 .hw.init = &(struct clk_init_data){ 1355 .name = "vpu_0_div", 1356 .ops = &clk_regmap_divider_ops, 1357 .parent_names = (const char *[]){ "vpu_0_sel" }, 1358 .num_parents = 1, 1359 .flags = CLK_SET_RATE_PARENT, 1360 }, 1361 }; 1362 1363 static struct clk_regmap gxbb_vpu_0 = { 1364 .data = &(struct clk_regmap_gate_data){ 1365 .offset = HHI_VPU_CLK_CNTL, 1366 .bit_idx = 8, 1367 }, 1368 .hw.init = &(struct clk_init_data) { 1369 .name = "vpu_0", 1370 .ops = &clk_regmap_gate_ops, 1371 .parent_names = (const char *[]){ "vpu_0_div" }, 1372 .num_parents = 1, 1373 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1374 }, 1375 }; 1376 1377 static struct clk_regmap gxbb_vpu_1_sel = { 1378 .data = &(struct clk_regmap_mux_data){ 1379 .offset = HHI_VPU_CLK_CNTL, 1380 .mask = 0x3, 1381 .shift = 25, 1382 }, 1383 .hw.init = &(struct clk_init_data){ 1384 .name = "vpu_1_sel", 1385 .ops = &clk_regmap_mux_ops, 1386 /* 1387 * bits 25:26 selects from 4 possible parents: 1388 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1389 */ 1390 .parent_names = gxbb_vpu_parent_names, 1391 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1392 .flags = CLK_SET_RATE_NO_REPARENT, 1393 }, 1394 }; 1395 1396 static struct clk_regmap gxbb_vpu_1_div = { 1397 .data = &(struct clk_regmap_div_data){ 1398 .offset = HHI_VPU_CLK_CNTL, 1399 .shift = 16, 1400 .width = 7, 1401 }, 1402 .hw.init = &(struct clk_init_data){ 1403 .name = "vpu_1_div", 1404 .ops = &clk_regmap_divider_ops, 1405 .parent_names = (const char *[]){ "vpu_1_sel" }, 1406 .num_parents = 1, 1407 .flags = CLK_SET_RATE_PARENT, 1408 }, 1409 }; 1410 1411 static struct clk_regmap gxbb_vpu_1 = { 1412 .data = &(struct clk_regmap_gate_data){ 1413 .offset = HHI_VPU_CLK_CNTL, 1414 .bit_idx = 24, 1415 }, 1416 .hw.init = &(struct clk_init_data) { 1417 .name = "vpu_1", 1418 .ops = &clk_regmap_gate_ops, 1419 .parent_names = (const char *[]){ "vpu_1_div" }, 1420 .num_parents = 1, 1421 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1422 }, 1423 }; 1424 1425 static struct clk_regmap gxbb_vpu = { 1426 .data = &(struct clk_regmap_mux_data){ 1427 .offset = HHI_VPU_CLK_CNTL, 1428 .mask = 1, 1429 .shift = 31, 1430 }, 1431 .hw.init = &(struct clk_init_data){ 1432 .name = "vpu", 1433 .ops = &clk_regmap_mux_ops, 1434 /* 1435 * bit 31 selects from 2 possible parents: 1436 * vpu_0 or vpu_1 1437 */ 1438 .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, 1439 .num_parents = 2, 1440 .flags = CLK_SET_RATE_NO_REPARENT, 1441 }, 1442 }; 1443 1444 /* VAPB Clock */ 1445 1446 static const char * const gxbb_vapb_parent_names[] = { 1447 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1448 }; 1449 1450 static struct clk_regmap gxbb_vapb_0_sel = { 1451 .data = &(struct clk_regmap_mux_data){ 1452 .offset = HHI_VAPBCLK_CNTL, 1453 .mask = 0x3, 1454 .shift = 9, 1455 }, 1456 .hw.init = &(struct clk_init_data){ 1457 .name = "vapb_0_sel", 1458 .ops = &clk_regmap_mux_ops, 1459 /* 1460 * bits 9:10 selects from 4 possible parents: 1461 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1462 */ 1463 .parent_names = gxbb_vapb_parent_names, 1464 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1465 .flags = CLK_SET_RATE_NO_REPARENT, 1466 }, 1467 }; 1468 1469 static struct clk_regmap gxbb_vapb_0_div = { 1470 .data = &(struct clk_regmap_div_data){ 1471 .offset = HHI_VAPBCLK_CNTL, 1472 .shift = 0, 1473 .width = 7, 1474 }, 1475 .hw.init = &(struct clk_init_data){ 1476 .name = "vapb_0_div", 1477 .ops = &clk_regmap_divider_ops, 1478 .parent_names = (const char *[]){ "vapb_0_sel" }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT, 1481 }, 1482 }; 1483 1484 static struct clk_regmap gxbb_vapb_0 = { 1485 .data = &(struct clk_regmap_gate_data){ 1486 .offset = HHI_VAPBCLK_CNTL, 1487 .bit_idx = 8, 1488 }, 1489 .hw.init = &(struct clk_init_data) { 1490 .name = "vapb_0", 1491 .ops = &clk_regmap_gate_ops, 1492 .parent_names = (const char *[]){ "vapb_0_div" }, 1493 .num_parents = 1, 1494 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1495 }, 1496 }; 1497 1498 static struct clk_regmap gxbb_vapb_1_sel = { 1499 .data = &(struct clk_regmap_mux_data){ 1500 .offset = HHI_VAPBCLK_CNTL, 1501 .mask = 0x3, 1502 .shift = 25, 1503 }, 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "vapb_1_sel", 1506 .ops = &clk_regmap_mux_ops, 1507 /* 1508 * bits 25:26 selects from 4 possible parents: 1509 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1510 */ 1511 .parent_names = gxbb_vapb_parent_names, 1512 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1513 .flags = CLK_SET_RATE_NO_REPARENT, 1514 }, 1515 }; 1516 1517 static struct clk_regmap gxbb_vapb_1_div = { 1518 .data = &(struct clk_regmap_div_data){ 1519 .offset = HHI_VAPBCLK_CNTL, 1520 .shift = 16, 1521 .width = 7, 1522 }, 1523 .hw.init = &(struct clk_init_data){ 1524 .name = "vapb_1_div", 1525 .ops = &clk_regmap_divider_ops, 1526 .parent_names = (const char *[]){ "vapb_1_sel" }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 }, 1530 }; 1531 1532 static struct clk_regmap gxbb_vapb_1 = { 1533 .data = &(struct clk_regmap_gate_data){ 1534 .offset = HHI_VAPBCLK_CNTL, 1535 .bit_idx = 24, 1536 }, 1537 .hw.init = &(struct clk_init_data) { 1538 .name = "vapb_1", 1539 .ops = &clk_regmap_gate_ops, 1540 .parent_names = (const char *[]){ "vapb_1_div" }, 1541 .num_parents = 1, 1542 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1543 }, 1544 }; 1545 1546 static struct clk_regmap gxbb_vapb_sel = { 1547 .data = &(struct clk_regmap_mux_data){ 1548 .offset = HHI_VAPBCLK_CNTL, 1549 .mask = 1, 1550 .shift = 31, 1551 }, 1552 .hw.init = &(struct clk_init_data){ 1553 .name = "vapb_sel", 1554 .ops = &clk_regmap_mux_ops, 1555 /* 1556 * bit 31 selects from 2 possible parents: 1557 * vapb_0 or vapb_1 1558 */ 1559 .parent_names = (const char *[]){ "vapb_0", "vapb_1" }, 1560 .num_parents = 2, 1561 .flags = CLK_SET_RATE_NO_REPARENT, 1562 }, 1563 }; 1564 1565 static struct clk_regmap gxbb_vapb = { 1566 .data = &(struct clk_regmap_gate_data){ 1567 .offset = HHI_VAPBCLK_CNTL, 1568 .bit_idx = 30, 1569 }, 1570 .hw.init = &(struct clk_init_data) { 1571 .name = "vapb", 1572 .ops = &clk_regmap_gate_ops, 1573 .parent_names = (const char *[]){ "vapb_sel" }, 1574 .num_parents = 1, 1575 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1576 }, 1577 }; 1578 1579 /* Video Clocks */ 1580 1581 static struct clk_regmap gxbb_vid_pll_div = { 1582 .data = &(struct meson_vid_pll_div_data){ 1583 .val = { 1584 .reg_off = HHI_VID_PLL_CLK_DIV, 1585 .shift = 0, 1586 .width = 15, 1587 }, 1588 .sel = { 1589 .reg_off = HHI_VID_PLL_CLK_DIV, 1590 .shift = 16, 1591 .width = 2, 1592 }, 1593 }, 1594 .hw.init = &(struct clk_init_data) { 1595 .name = "vid_pll_div", 1596 .ops = &meson_vid_pll_div_ro_ops, 1597 .parent_names = (const char *[]){ "hdmi_pll" }, 1598 .num_parents = 1, 1599 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1600 }, 1601 }; 1602 1603 static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" }; 1604 1605 static struct clk_regmap gxbb_vid_pll_sel = { 1606 .data = &(struct clk_regmap_mux_data){ 1607 .offset = HHI_VID_PLL_CLK_DIV, 1608 .mask = 0x1, 1609 .shift = 18, 1610 }, 1611 .hw.init = &(struct clk_init_data){ 1612 .name = "vid_pll_sel", 1613 .ops = &clk_regmap_mux_ops, 1614 /* 1615 * bit 18 selects from 2 possible parents: 1616 * vid_pll_div or hdmi_pll 1617 */ 1618 .parent_names = gxbb_vid_pll_parent_names, 1619 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_names), 1620 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1621 }, 1622 }; 1623 1624 static struct clk_regmap gxbb_vid_pll = { 1625 .data = &(struct clk_regmap_gate_data){ 1626 .offset = HHI_VID_PLL_CLK_DIV, 1627 .bit_idx = 19, 1628 }, 1629 .hw.init = &(struct clk_init_data) { 1630 .name = "vid_pll", 1631 .ops = &clk_regmap_gate_ops, 1632 .parent_names = (const char *[]){ "vid_pll_sel" }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1635 }, 1636 }; 1637 1638 static const char * const gxbb_vclk_parent_names[] = { 1639 "vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll", 1640 "fclk_div7", "mpll1", 1641 }; 1642 1643 static struct clk_regmap gxbb_vclk_sel = { 1644 .data = &(struct clk_regmap_mux_data){ 1645 .offset = HHI_VID_CLK_CNTL, 1646 .mask = 0x7, 1647 .shift = 16, 1648 }, 1649 .hw.init = &(struct clk_init_data){ 1650 .name = "vclk_sel", 1651 .ops = &clk_regmap_mux_ops, 1652 /* 1653 * bits 16:18 selects from 8 possible parents: 1654 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1655 * vid_pll, fclk_div7, mp1 1656 */ 1657 .parent_names = gxbb_vclk_parent_names, 1658 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_names), 1659 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1660 }, 1661 }; 1662 1663 static struct clk_regmap gxbb_vclk2_sel = { 1664 .data = &(struct clk_regmap_mux_data){ 1665 .offset = HHI_VIID_CLK_CNTL, 1666 .mask = 0x7, 1667 .shift = 16, 1668 }, 1669 .hw.init = &(struct clk_init_data){ 1670 .name = "vclk2_sel", 1671 .ops = &clk_regmap_mux_ops, 1672 /* 1673 * bits 16:18 selects from 8 possible parents: 1674 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1675 * vid_pll, fclk_div7, mp1 1676 */ 1677 .parent_names = gxbb_vclk_parent_names, 1678 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_names), 1679 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1680 }, 1681 }; 1682 1683 static struct clk_regmap gxbb_vclk_input = { 1684 .data = &(struct clk_regmap_gate_data){ 1685 .offset = HHI_VID_CLK_DIV, 1686 .bit_idx = 16, 1687 }, 1688 .hw.init = &(struct clk_init_data) { 1689 .name = "vclk_input", 1690 .ops = &clk_regmap_gate_ops, 1691 .parent_names = (const char *[]){ "vclk_sel" }, 1692 .num_parents = 1, 1693 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1694 }, 1695 }; 1696 1697 static struct clk_regmap gxbb_vclk2_input = { 1698 .data = &(struct clk_regmap_gate_data){ 1699 .offset = HHI_VIID_CLK_DIV, 1700 .bit_idx = 16, 1701 }, 1702 .hw.init = &(struct clk_init_data) { 1703 .name = "vclk2_input", 1704 .ops = &clk_regmap_gate_ops, 1705 .parent_names = (const char *[]){ "vclk2_sel" }, 1706 .num_parents = 1, 1707 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1708 }, 1709 }; 1710 1711 static struct clk_regmap gxbb_vclk_div = { 1712 .data = &(struct clk_regmap_div_data){ 1713 .offset = HHI_VID_CLK_DIV, 1714 .shift = 0, 1715 .width = 8, 1716 }, 1717 .hw.init = &(struct clk_init_data){ 1718 .name = "vclk_div", 1719 .ops = &clk_regmap_divider_ops, 1720 .parent_names = (const char *[]){ "vclk_input" }, 1721 .num_parents = 1, 1722 .flags = CLK_GET_RATE_NOCACHE, 1723 }, 1724 }; 1725 1726 static struct clk_regmap gxbb_vclk2_div = { 1727 .data = &(struct clk_regmap_div_data){ 1728 .offset = HHI_VIID_CLK_DIV, 1729 .shift = 0, 1730 .width = 8, 1731 }, 1732 .hw.init = &(struct clk_init_data){ 1733 .name = "vclk2_div", 1734 .ops = &clk_regmap_divider_ops, 1735 .parent_names = (const char *[]){ "vclk2_input" }, 1736 .num_parents = 1, 1737 .flags = CLK_GET_RATE_NOCACHE, 1738 }, 1739 }; 1740 1741 static struct clk_regmap gxbb_vclk = { 1742 .data = &(struct clk_regmap_gate_data){ 1743 .offset = HHI_VID_CLK_CNTL, 1744 .bit_idx = 19, 1745 }, 1746 .hw.init = &(struct clk_init_data) { 1747 .name = "vclk", 1748 .ops = &clk_regmap_gate_ops, 1749 .parent_names = (const char *[]){ "vclk_div" }, 1750 .num_parents = 1, 1751 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1752 }, 1753 }; 1754 1755 static struct clk_regmap gxbb_vclk2 = { 1756 .data = &(struct clk_regmap_gate_data){ 1757 .offset = HHI_VIID_CLK_CNTL, 1758 .bit_idx = 19, 1759 }, 1760 .hw.init = &(struct clk_init_data) { 1761 .name = "vclk2", 1762 .ops = &clk_regmap_gate_ops, 1763 .parent_names = (const char *[]){ "vclk2_div" }, 1764 .num_parents = 1, 1765 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1766 }, 1767 }; 1768 1769 static struct clk_regmap gxbb_vclk_div1 = { 1770 .data = &(struct clk_regmap_gate_data){ 1771 .offset = HHI_VID_CLK_CNTL, 1772 .bit_idx = 0, 1773 }, 1774 .hw.init = &(struct clk_init_data) { 1775 .name = "vclk_div1", 1776 .ops = &clk_regmap_gate_ops, 1777 .parent_names = (const char *[]){ "vclk" }, 1778 .num_parents = 1, 1779 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1780 }, 1781 }; 1782 1783 static struct clk_regmap gxbb_vclk_div2_en = { 1784 .data = &(struct clk_regmap_gate_data){ 1785 .offset = HHI_VID_CLK_CNTL, 1786 .bit_idx = 1, 1787 }, 1788 .hw.init = &(struct clk_init_data) { 1789 .name = "vclk_div2_en", 1790 .ops = &clk_regmap_gate_ops, 1791 .parent_names = (const char *[]){ "vclk" }, 1792 .num_parents = 1, 1793 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1794 }, 1795 }; 1796 1797 static struct clk_regmap gxbb_vclk_div4_en = { 1798 .data = &(struct clk_regmap_gate_data){ 1799 .offset = HHI_VID_CLK_CNTL, 1800 .bit_idx = 2, 1801 }, 1802 .hw.init = &(struct clk_init_data) { 1803 .name = "vclk_div4_en", 1804 .ops = &clk_regmap_gate_ops, 1805 .parent_names = (const char *[]){ "vclk" }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1808 }, 1809 }; 1810 1811 static struct clk_regmap gxbb_vclk_div6_en = { 1812 .data = &(struct clk_regmap_gate_data){ 1813 .offset = HHI_VID_CLK_CNTL, 1814 .bit_idx = 3, 1815 }, 1816 .hw.init = &(struct clk_init_data) { 1817 .name = "vclk_div6_en", 1818 .ops = &clk_regmap_gate_ops, 1819 .parent_names = (const char *[]){ "vclk" }, 1820 .num_parents = 1, 1821 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1822 }, 1823 }; 1824 1825 static struct clk_regmap gxbb_vclk_div12_en = { 1826 .data = &(struct clk_regmap_gate_data){ 1827 .offset = HHI_VID_CLK_CNTL, 1828 .bit_idx = 4, 1829 }, 1830 .hw.init = &(struct clk_init_data) { 1831 .name = "vclk_div12_en", 1832 .ops = &clk_regmap_gate_ops, 1833 .parent_names = (const char *[]){ "vclk" }, 1834 .num_parents = 1, 1835 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1836 }, 1837 }; 1838 1839 static struct clk_regmap gxbb_vclk2_div1 = { 1840 .data = &(struct clk_regmap_gate_data){ 1841 .offset = HHI_VIID_CLK_CNTL, 1842 .bit_idx = 0, 1843 }, 1844 .hw.init = &(struct clk_init_data) { 1845 .name = "vclk2_div1", 1846 .ops = &clk_regmap_gate_ops, 1847 .parent_names = (const char *[]){ "vclk2" }, 1848 .num_parents = 1, 1849 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1850 }, 1851 }; 1852 1853 static struct clk_regmap gxbb_vclk2_div2_en = { 1854 .data = &(struct clk_regmap_gate_data){ 1855 .offset = HHI_VIID_CLK_CNTL, 1856 .bit_idx = 1, 1857 }, 1858 .hw.init = &(struct clk_init_data) { 1859 .name = "vclk2_div2_en", 1860 .ops = &clk_regmap_gate_ops, 1861 .parent_names = (const char *[]){ "vclk2" }, 1862 .num_parents = 1, 1863 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1864 }, 1865 }; 1866 1867 static struct clk_regmap gxbb_vclk2_div4_en = { 1868 .data = &(struct clk_regmap_gate_data){ 1869 .offset = HHI_VIID_CLK_CNTL, 1870 .bit_idx = 2, 1871 }, 1872 .hw.init = &(struct clk_init_data) { 1873 .name = "vclk2_div4_en", 1874 .ops = &clk_regmap_gate_ops, 1875 .parent_names = (const char *[]){ "vclk2" }, 1876 .num_parents = 1, 1877 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1878 }, 1879 }; 1880 1881 static struct clk_regmap gxbb_vclk2_div6_en = { 1882 .data = &(struct clk_regmap_gate_data){ 1883 .offset = HHI_VIID_CLK_CNTL, 1884 .bit_idx = 3, 1885 }, 1886 .hw.init = &(struct clk_init_data) { 1887 .name = "vclk2_div6_en", 1888 .ops = &clk_regmap_gate_ops, 1889 .parent_names = (const char *[]){ "vclk2" }, 1890 .num_parents = 1, 1891 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1892 }, 1893 }; 1894 1895 static struct clk_regmap gxbb_vclk2_div12_en = { 1896 .data = &(struct clk_regmap_gate_data){ 1897 .offset = HHI_VIID_CLK_CNTL, 1898 .bit_idx = 4, 1899 }, 1900 .hw.init = &(struct clk_init_data) { 1901 .name = "vclk2_div12_en", 1902 .ops = &clk_regmap_gate_ops, 1903 .parent_names = (const char *[]){ "vclk2" }, 1904 .num_parents = 1, 1905 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1906 }, 1907 }; 1908 1909 static struct clk_fixed_factor gxbb_vclk_div2 = { 1910 .mult = 1, 1911 .div = 2, 1912 .hw.init = &(struct clk_init_data){ 1913 .name = "vclk_div2", 1914 .ops = &clk_fixed_factor_ops, 1915 .parent_names = (const char *[]){ "vclk_div2_en" }, 1916 .num_parents = 1, 1917 }, 1918 }; 1919 1920 static struct clk_fixed_factor gxbb_vclk_div4 = { 1921 .mult = 1, 1922 .div = 4, 1923 .hw.init = &(struct clk_init_data){ 1924 .name = "vclk_div4", 1925 .ops = &clk_fixed_factor_ops, 1926 .parent_names = (const char *[]){ "vclk_div4_en" }, 1927 .num_parents = 1, 1928 }, 1929 }; 1930 1931 static struct clk_fixed_factor gxbb_vclk_div6 = { 1932 .mult = 1, 1933 .div = 6, 1934 .hw.init = &(struct clk_init_data){ 1935 .name = "vclk_div6", 1936 .ops = &clk_fixed_factor_ops, 1937 .parent_names = (const char *[]){ "vclk_div6_en" }, 1938 .num_parents = 1, 1939 }, 1940 }; 1941 1942 static struct clk_fixed_factor gxbb_vclk_div12 = { 1943 .mult = 1, 1944 .div = 12, 1945 .hw.init = &(struct clk_init_data){ 1946 .name = "vclk_div12", 1947 .ops = &clk_fixed_factor_ops, 1948 .parent_names = (const char *[]){ "vclk_div12_en" }, 1949 .num_parents = 1, 1950 }, 1951 }; 1952 1953 static struct clk_fixed_factor gxbb_vclk2_div2 = { 1954 .mult = 1, 1955 .div = 2, 1956 .hw.init = &(struct clk_init_data){ 1957 .name = "vclk2_div2", 1958 .ops = &clk_fixed_factor_ops, 1959 .parent_names = (const char *[]){ "vclk2_div2_en" }, 1960 .num_parents = 1, 1961 }, 1962 }; 1963 1964 static struct clk_fixed_factor gxbb_vclk2_div4 = { 1965 .mult = 1, 1966 .div = 4, 1967 .hw.init = &(struct clk_init_data){ 1968 .name = "vclk2_div4", 1969 .ops = &clk_fixed_factor_ops, 1970 .parent_names = (const char *[]){ "vclk2_div4_en" }, 1971 .num_parents = 1, 1972 }, 1973 }; 1974 1975 static struct clk_fixed_factor gxbb_vclk2_div6 = { 1976 .mult = 1, 1977 .div = 6, 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "vclk2_div6", 1980 .ops = &clk_fixed_factor_ops, 1981 .parent_names = (const char *[]){ "vclk2_div6_en" }, 1982 .num_parents = 1, 1983 }, 1984 }; 1985 1986 static struct clk_fixed_factor gxbb_vclk2_div12 = { 1987 .mult = 1, 1988 .div = 12, 1989 .hw.init = &(struct clk_init_data){ 1990 .name = "vclk2_div12", 1991 .ops = &clk_fixed_factor_ops, 1992 .parent_names = (const char *[]){ "vclk2_div12_en" }, 1993 .num_parents = 1, 1994 }, 1995 }; 1996 1997 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1998 static const char * const gxbb_cts_parent_names[] = { 1999 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", 2000 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", 2001 "vclk2_div6", "vclk2_div12" 2002 }; 2003 2004 static struct clk_regmap gxbb_cts_enci_sel = { 2005 .data = &(struct clk_regmap_mux_data){ 2006 .offset = HHI_VID_CLK_DIV, 2007 .mask = 0xf, 2008 .shift = 28, 2009 .table = mux_table_cts_sel, 2010 }, 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "cts_enci_sel", 2013 .ops = &clk_regmap_mux_ops, 2014 .parent_names = gxbb_cts_parent_names, 2015 .num_parents = ARRAY_SIZE(gxbb_cts_parent_names), 2016 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2017 }, 2018 }; 2019 2020 static struct clk_regmap gxbb_cts_encp_sel = { 2021 .data = &(struct clk_regmap_mux_data){ 2022 .offset = HHI_VID_CLK_DIV, 2023 .mask = 0xf, 2024 .shift = 20, 2025 .table = mux_table_cts_sel, 2026 }, 2027 .hw.init = &(struct clk_init_data){ 2028 .name = "cts_encp_sel", 2029 .ops = &clk_regmap_mux_ops, 2030 .parent_names = gxbb_cts_parent_names, 2031 .num_parents = ARRAY_SIZE(gxbb_cts_parent_names), 2032 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2033 }, 2034 }; 2035 2036 static struct clk_regmap gxbb_cts_vdac_sel = { 2037 .data = &(struct clk_regmap_mux_data){ 2038 .offset = HHI_VIID_CLK_DIV, 2039 .mask = 0xf, 2040 .shift = 28, 2041 .table = mux_table_cts_sel, 2042 }, 2043 .hw.init = &(struct clk_init_data){ 2044 .name = "cts_vdac_sel", 2045 .ops = &clk_regmap_mux_ops, 2046 .parent_names = gxbb_cts_parent_names, 2047 .num_parents = ARRAY_SIZE(gxbb_cts_parent_names), 2048 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2049 }, 2050 }; 2051 2052 /* TOFIX: add support for cts_tcon */ 2053 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2054 static const char * const gxbb_cts_hdmi_tx_parent_names[] = { 2055 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", 2056 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", 2057 "vclk2_div6", "vclk2_div12" 2058 }; 2059 2060 static struct clk_regmap gxbb_hdmi_tx_sel = { 2061 .data = &(struct clk_regmap_mux_data){ 2062 .offset = HHI_HDMI_CLK_CNTL, 2063 .mask = 0xf, 2064 .shift = 16, 2065 .table = mux_table_hdmi_tx_sel, 2066 }, 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "hdmi_tx_sel", 2069 .ops = &clk_regmap_mux_ops, 2070 /* 2071 * bits 31:28 selects from 12 possible parents: 2072 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 2073 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, 2074 * cts_tcon 2075 */ 2076 .parent_names = gxbb_cts_hdmi_tx_parent_names, 2077 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_names), 2078 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2079 }, 2080 }; 2081 2082 static struct clk_regmap gxbb_cts_enci = { 2083 .data = &(struct clk_regmap_gate_data){ 2084 .offset = HHI_VID_CLK_CNTL2, 2085 .bit_idx = 0, 2086 }, 2087 .hw.init = &(struct clk_init_data) { 2088 .name = "cts_enci", 2089 .ops = &clk_regmap_gate_ops, 2090 .parent_names = (const char *[]){ "cts_enci_sel" }, 2091 .num_parents = 1, 2092 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2093 }, 2094 }; 2095 2096 static struct clk_regmap gxbb_cts_encp = { 2097 .data = &(struct clk_regmap_gate_data){ 2098 .offset = HHI_VID_CLK_CNTL2, 2099 .bit_idx = 2, 2100 }, 2101 .hw.init = &(struct clk_init_data) { 2102 .name = "cts_encp", 2103 .ops = &clk_regmap_gate_ops, 2104 .parent_names = (const char *[]){ "cts_encp_sel" }, 2105 .num_parents = 1, 2106 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2107 }, 2108 }; 2109 2110 static struct clk_regmap gxbb_cts_vdac = { 2111 .data = &(struct clk_regmap_gate_data){ 2112 .offset = HHI_VID_CLK_CNTL2, 2113 .bit_idx = 4, 2114 }, 2115 .hw.init = &(struct clk_init_data) { 2116 .name = "cts_vdac", 2117 .ops = &clk_regmap_gate_ops, 2118 .parent_names = (const char *[]){ "cts_vdac_sel" }, 2119 .num_parents = 1, 2120 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2121 }, 2122 }; 2123 2124 static struct clk_regmap gxbb_hdmi_tx = { 2125 .data = &(struct clk_regmap_gate_data){ 2126 .offset = HHI_VID_CLK_CNTL2, 2127 .bit_idx = 5, 2128 }, 2129 .hw.init = &(struct clk_init_data) { 2130 .name = "hdmi_tx", 2131 .ops = &clk_regmap_gate_ops, 2132 .parent_names = (const char *[]){ "hdmi_tx_sel" }, 2133 .num_parents = 1, 2134 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2135 }, 2136 }; 2137 2138 /* HDMI Clocks */ 2139 2140 static const char * const gxbb_hdmi_parent_names[] = { 2141 "xtal", "fclk_div4", "fclk_div3", "fclk_div5" 2142 }; 2143 2144 static struct clk_regmap gxbb_hdmi_sel = { 2145 .data = &(struct clk_regmap_mux_data){ 2146 .offset = HHI_HDMI_CLK_CNTL, 2147 .mask = 0x3, 2148 .shift = 9, 2149 .flags = CLK_MUX_ROUND_CLOSEST, 2150 }, 2151 .hw.init = &(struct clk_init_data){ 2152 .name = "hdmi_sel", 2153 .ops = &clk_regmap_mux_ops, 2154 .parent_names = gxbb_hdmi_parent_names, 2155 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_names), 2156 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2157 }, 2158 }; 2159 2160 static struct clk_regmap gxbb_hdmi_div = { 2161 .data = &(struct clk_regmap_div_data){ 2162 .offset = HHI_HDMI_CLK_CNTL, 2163 .shift = 0, 2164 .width = 7, 2165 }, 2166 .hw.init = &(struct clk_init_data){ 2167 .name = "hdmi_div", 2168 .ops = &clk_regmap_divider_ops, 2169 .parent_names = (const char *[]){ "hdmi_sel" }, 2170 .num_parents = 1, 2171 .flags = CLK_GET_RATE_NOCACHE, 2172 }, 2173 }; 2174 2175 static struct clk_regmap gxbb_hdmi = { 2176 .data = &(struct clk_regmap_gate_data){ 2177 .offset = HHI_HDMI_CLK_CNTL, 2178 .bit_idx = 8, 2179 }, 2180 .hw.init = &(struct clk_init_data) { 2181 .name = "hdmi", 2182 .ops = &clk_regmap_gate_ops, 2183 .parent_names = (const char *[]){ "hdmi_div" }, 2184 .num_parents = 1, 2185 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2186 }, 2187 }; 2188 2189 /* VDEC clocks */ 2190 2191 static const char * const gxbb_vdec_parent_names[] = { 2192 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 2193 }; 2194 2195 static struct clk_regmap gxbb_vdec_1_sel = { 2196 .data = &(struct clk_regmap_mux_data){ 2197 .offset = HHI_VDEC_CLK_CNTL, 2198 .mask = 0x3, 2199 .shift = 9, 2200 .flags = CLK_MUX_ROUND_CLOSEST, 2201 }, 2202 .hw.init = &(struct clk_init_data){ 2203 .name = "vdec_1_sel", 2204 .ops = &clk_regmap_mux_ops, 2205 .parent_names = gxbb_vdec_parent_names, 2206 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 2207 .flags = CLK_SET_RATE_PARENT, 2208 }, 2209 }; 2210 2211 static struct clk_regmap gxbb_vdec_1_div = { 2212 .data = &(struct clk_regmap_div_data){ 2213 .offset = HHI_VDEC_CLK_CNTL, 2214 .shift = 0, 2215 .width = 7, 2216 }, 2217 .hw.init = &(struct clk_init_data){ 2218 .name = "vdec_1_div", 2219 .ops = &clk_regmap_divider_ops, 2220 .parent_names = (const char *[]){ "vdec_1_sel" }, 2221 .num_parents = 1, 2222 .flags = CLK_SET_RATE_PARENT, 2223 }, 2224 }; 2225 2226 static struct clk_regmap gxbb_vdec_1 = { 2227 .data = &(struct clk_regmap_gate_data){ 2228 .offset = HHI_VDEC_CLK_CNTL, 2229 .bit_idx = 8, 2230 }, 2231 .hw.init = &(struct clk_init_data) { 2232 .name = "vdec_1", 2233 .ops = &clk_regmap_gate_ops, 2234 .parent_names = (const char *[]){ "vdec_1_div" }, 2235 .num_parents = 1, 2236 .flags = CLK_SET_RATE_PARENT, 2237 }, 2238 }; 2239 2240 static struct clk_regmap gxbb_vdec_hevc_sel = { 2241 .data = &(struct clk_regmap_mux_data){ 2242 .offset = HHI_VDEC2_CLK_CNTL, 2243 .mask = 0x3, 2244 .shift = 25, 2245 .flags = CLK_MUX_ROUND_CLOSEST, 2246 }, 2247 .hw.init = &(struct clk_init_data){ 2248 .name = "vdec_hevc_sel", 2249 .ops = &clk_regmap_mux_ops, 2250 .parent_names = gxbb_vdec_parent_names, 2251 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 2252 .flags = CLK_SET_RATE_PARENT, 2253 }, 2254 }; 2255 2256 static struct clk_regmap gxbb_vdec_hevc_div = { 2257 .data = &(struct clk_regmap_div_data){ 2258 .offset = HHI_VDEC2_CLK_CNTL, 2259 .shift = 16, 2260 .width = 7, 2261 }, 2262 .hw.init = &(struct clk_init_data){ 2263 .name = "vdec_hevc_div", 2264 .ops = &clk_regmap_divider_ops, 2265 .parent_names = (const char *[]){ "vdec_hevc_sel" }, 2266 .num_parents = 1, 2267 .flags = CLK_SET_RATE_PARENT, 2268 }, 2269 }; 2270 2271 static struct clk_regmap gxbb_vdec_hevc = { 2272 .data = &(struct clk_regmap_gate_data){ 2273 .offset = HHI_VDEC2_CLK_CNTL, 2274 .bit_idx = 24, 2275 }, 2276 .hw.init = &(struct clk_init_data) { 2277 .name = "vdec_hevc", 2278 .ops = &clk_regmap_gate_ops, 2279 .parent_names = (const char *[]){ "vdec_hevc_div" }, 2280 .num_parents = 1, 2281 .flags = CLK_SET_RATE_PARENT, 2282 }, 2283 }; 2284 2285 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 2286 9, 10, 11, 13, 14, }; 2287 static const char * const gen_clk_parent_names[] = { 2288 "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2", 2289 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", 2290 }; 2291 2292 static struct clk_regmap gxbb_gen_clk_sel = { 2293 .data = &(struct clk_regmap_mux_data){ 2294 .offset = HHI_GEN_CLK_CNTL, 2295 .mask = 0xf, 2296 .shift = 12, 2297 .table = mux_table_gen_clk, 2298 }, 2299 .hw.init = &(struct clk_init_data){ 2300 .name = "gen_clk_sel", 2301 .ops = &clk_regmap_mux_ops, 2302 /* 2303 * bits 15:12 selects from 14 possible parents: 2304 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 2305 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 2306 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 2307 */ 2308 .parent_names = gen_clk_parent_names, 2309 .num_parents = ARRAY_SIZE(gen_clk_parent_names), 2310 }, 2311 }; 2312 2313 static struct clk_regmap gxbb_gen_clk_div = { 2314 .data = &(struct clk_regmap_div_data){ 2315 .offset = HHI_GEN_CLK_CNTL, 2316 .shift = 0, 2317 .width = 11, 2318 }, 2319 .hw.init = &(struct clk_init_data){ 2320 .name = "gen_clk_div", 2321 .ops = &clk_regmap_divider_ops, 2322 .parent_names = (const char *[]){ "gen_clk_sel" }, 2323 .num_parents = 1, 2324 .flags = CLK_SET_RATE_PARENT, 2325 }, 2326 }; 2327 2328 static struct clk_regmap gxbb_gen_clk = { 2329 .data = &(struct clk_regmap_gate_data){ 2330 .offset = HHI_GEN_CLK_CNTL, 2331 .bit_idx = 7, 2332 }, 2333 .hw.init = &(struct clk_init_data){ 2334 .name = "gen_clk", 2335 .ops = &clk_regmap_gate_ops, 2336 .parent_names = (const char *[]){ "gen_clk_div" }, 2337 .num_parents = 1, 2338 .flags = CLK_SET_RATE_PARENT, 2339 }, 2340 }; 2341 2342 /* Everything Else (EE) domain gates */ 2343 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 2344 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 2345 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 2346 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 2347 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 2348 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 2349 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 2350 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); 2351 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 2352 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 2353 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 2354 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 2355 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 2356 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 2357 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 2358 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 2359 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 2360 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 2361 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 2362 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 2363 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 2364 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 2365 2366 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 2367 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 2368 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 2369 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6); 2370 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7); 2371 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8); 2372 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9); 2373 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10); 2374 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11); 2375 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12); 2376 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13); 2377 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 2378 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 2379 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 2380 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 2381 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 2382 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 2383 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 2384 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 2385 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 2386 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 2387 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 2388 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 2389 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 2390 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 2391 2392 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 2393 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 2394 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 2395 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 2396 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 2397 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 2398 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 2399 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 2400 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 2401 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); 2402 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 2403 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 2404 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 2405 2406 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 2407 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 2408 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 2409 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 2410 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 2411 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 2412 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 2413 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 2414 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 2415 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 2416 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 2417 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 2418 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 2419 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 2420 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 2421 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 2422 2423 /* Always On (AO) domain gates */ 2424 2425 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 2426 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 2427 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 2428 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 2429 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 2430 2431 /* Array of all clocks provided by this provider */ 2432 2433 static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 2434 .hws = { 2435 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2436 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2437 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2438 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2439 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2440 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2441 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2442 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2443 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2444 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2445 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2446 [CLKID_CLK81] = &gxbb_clk81.hw, 2447 [CLKID_MPLL0] = &gxbb_mpll0.hw, 2448 [CLKID_MPLL1] = &gxbb_mpll1.hw, 2449 [CLKID_MPLL2] = &gxbb_mpll2.hw, 2450 [CLKID_DDR] = &gxbb_ddr.hw, 2451 [CLKID_DOS] = &gxbb_dos.hw, 2452 [CLKID_ISA] = &gxbb_isa.hw, 2453 [CLKID_PL301] = &gxbb_pl301.hw, 2454 [CLKID_PERIPHS] = &gxbb_periphs.hw, 2455 [CLKID_SPICC] = &gxbb_spicc.hw, 2456 [CLKID_I2C] = &gxbb_i2c.hw, 2457 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2458 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2459 [CLKID_RNG0] = &gxbb_rng0.hw, 2460 [CLKID_UART0] = &gxbb_uart0.hw, 2461 [CLKID_SDHC] = &gxbb_sdhc.hw, 2462 [CLKID_STREAM] = &gxbb_stream.hw, 2463 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2464 [CLKID_SDIO] = &gxbb_sdio.hw, 2465 [CLKID_ABUF] = &gxbb_abuf.hw, 2466 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2467 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2468 [CLKID_SPI] = &gxbb_spi.hw, 2469 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2470 [CLKID_ETH] = &gxbb_eth.hw, 2471 [CLKID_DEMUX] = &gxbb_demux.hw, 2472 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2473 [CLKID_IEC958] = &gxbb_iec958.hw, 2474 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2475 [CLKID_AMCLK] = &gxbb_amclk.hw, 2476 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2477 [CLKID_MIXER] = &gxbb_mixer.hw, 2478 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2479 [CLKID_ADC] = &gxbb_adc.hw, 2480 [CLKID_BLKMV] = &gxbb_blkmv.hw, 2481 [CLKID_AIU] = &gxbb_aiu.hw, 2482 [CLKID_UART1] = &gxbb_uart1.hw, 2483 [CLKID_G2D] = &gxbb_g2d.hw, 2484 [CLKID_USB0] = &gxbb_usb0.hw, 2485 [CLKID_USB1] = &gxbb_usb1.hw, 2486 [CLKID_RESET] = &gxbb_reset.hw, 2487 [CLKID_NAND] = &gxbb_nand.hw, 2488 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2489 [CLKID_USB] = &gxbb_usb.hw, 2490 [CLKID_VDIN1] = &gxbb_vdin1.hw, 2491 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2492 [CLKID_EFUSE] = &gxbb_efuse.hw, 2493 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2494 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2495 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2496 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2497 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2498 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2499 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2500 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2501 [CLKID_DVIN] = &gxbb_dvin.hw, 2502 [CLKID_UART2] = &gxbb_uart2.hw, 2503 [CLKID_SANA] = &gxbb_sana.hw, 2504 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2505 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2506 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2507 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2508 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2509 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2510 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2511 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2512 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2513 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2514 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2515 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2516 [CLKID_ENC480P] = &gxbb_enc480p.hw, 2517 [CLKID_RNG1] = &gxbb_rng1.hw, 2518 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2519 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2520 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2521 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2522 [CLKID_EDP] = &gxbb_edp.hw, 2523 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2524 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2525 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2526 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2527 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2528 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2529 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2530 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2531 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2532 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2533 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2534 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2535 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2536 [CLKID_MALI_0] = &gxbb_mali_0.hw, 2537 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2538 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2539 [CLKID_MALI_1] = &gxbb_mali_1.hw, 2540 [CLKID_MALI] = &gxbb_mali.hw, 2541 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2542 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2543 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2544 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2545 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2546 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2547 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2548 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2549 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2550 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2551 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2552 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2553 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2554 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2555 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2556 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2557 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2558 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2559 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2560 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2561 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2562 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2563 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2564 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2565 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2566 [CLKID_VPU] = &gxbb_vpu.hw, 2567 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2568 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2569 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2570 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2571 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2572 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2573 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2574 [CLKID_VAPB] = &gxbb_vapb.hw, 2575 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2576 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2577 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2578 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2579 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2580 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2581 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2582 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2583 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2584 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2585 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2586 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2587 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2588 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2589 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2590 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 2591 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 2592 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 2593 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 2594 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 2595 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 2596 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 2597 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 2598 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 2599 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 2600 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 2601 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 2602 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 2603 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 2604 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 2605 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 2606 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 2607 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 2608 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 2609 [CLKID_VCLK] = &gxbb_vclk.hw, 2610 [CLKID_VCLK2] = &gxbb_vclk2.hw, 2611 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 2612 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 2613 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 2614 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 2615 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 2616 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 2617 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 2618 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 2619 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 2620 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 2621 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 2622 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 2623 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 2624 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 2625 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 2626 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 2627 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 2628 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 2629 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 2630 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 2631 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 2632 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 2633 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 2634 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 2635 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 2636 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 2637 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 2638 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 2639 [CLKID_HDMI] = &gxbb_hdmi.hw, 2640 [NR_CLKS] = NULL, 2641 }, 2642 .num = NR_CLKS, 2643 }; 2644 2645 static struct clk_hw_onecell_data gxl_hw_onecell_data = { 2646 .hws = { 2647 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2648 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 2649 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2650 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2651 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2652 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2653 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2654 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2655 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2656 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2657 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2658 [CLKID_CLK81] = &gxbb_clk81.hw, 2659 [CLKID_MPLL0] = &gxbb_mpll0.hw, 2660 [CLKID_MPLL1] = &gxbb_mpll1.hw, 2661 [CLKID_MPLL2] = &gxbb_mpll2.hw, 2662 [CLKID_DDR] = &gxbb_ddr.hw, 2663 [CLKID_DOS] = &gxbb_dos.hw, 2664 [CLKID_ISA] = &gxbb_isa.hw, 2665 [CLKID_PL301] = &gxbb_pl301.hw, 2666 [CLKID_PERIPHS] = &gxbb_periphs.hw, 2667 [CLKID_SPICC] = &gxbb_spicc.hw, 2668 [CLKID_I2C] = &gxbb_i2c.hw, 2669 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2670 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2671 [CLKID_RNG0] = &gxbb_rng0.hw, 2672 [CLKID_UART0] = &gxbb_uart0.hw, 2673 [CLKID_SDHC] = &gxbb_sdhc.hw, 2674 [CLKID_STREAM] = &gxbb_stream.hw, 2675 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2676 [CLKID_SDIO] = &gxbb_sdio.hw, 2677 [CLKID_ABUF] = &gxbb_abuf.hw, 2678 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2679 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2680 [CLKID_SPI] = &gxbb_spi.hw, 2681 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2682 [CLKID_ETH] = &gxbb_eth.hw, 2683 [CLKID_DEMUX] = &gxbb_demux.hw, 2684 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2685 [CLKID_IEC958] = &gxbb_iec958.hw, 2686 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2687 [CLKID_AMCLK] = &gxbb_amclk.hw, 2688 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2689 [CLKID_MIXER] = &gxbb_mixer.hw, 2690 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2691 [CLKID_ADC] = &gxbb_adc.hw, 2692 [CLKID_BLKMV] = &gxbb_blkmv.hw, 2693 [CLKID_AIU] = &gxbb_aiu.hw, 2694 [CLKID_UART1] = &gxbb_uart1.hw, 2695 [CLKID_G2D] = &gxbb_g2d.hw, 2696 [CLKID_USB0] = &gxbb_usb0.hw, 2697 [CLKID_USB1] = &gxbb_usb1.hw, 2698 [CLKID_RESET] = &gxbb_reset.hw, 2699 [CLKID_NAND] = &gxbb_nand.hw, 2700 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2701 [CLKID_USB] = &gxbb_usb.hw, 2702 [CLKID_VDIN1] = &gxbb_vdin1.hw, 2703 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2704 [CLKID_EFUSE] = &gxbb_efuse.hw, 2705 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2706 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2707 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2708 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2709 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2710 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2711 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2712 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2713 [CLKID_DVIN] = &gxbb_dvin.hw, 2714 [CLKID_UART2] = &gxbb_uart2.hw, 2715 [CLKID_SANA] = &gxbb_sana.hw, 2716 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2717 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2718 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2719 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2720 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2721 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2722 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2723 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2724 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2725 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2726 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2727 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2728 [CLKID_ENC480P] = &gxbb_enc480p.hw, 2729 [CLKID_RNG1] = &gxbb_rng1.hw, 2730 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2731 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2732 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2733 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2734 [CLKID_EDP] = &gxbb_edp.hw, 2735 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2736 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2737 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2738 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2739 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2740 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2741 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2742 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2743 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2744 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2745 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2746 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2747 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2748 [CLKID_MALI_0] = &gxbb_mali_0.hw, 2749 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2750 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2751 [CLKID_MALI_1] = &gxbb_mali_1.hw, 2752 [CLKID_MALI] = &gxbb_mali.hw, 2753 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2754 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2755 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2756 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2757 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2758 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2759 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2760 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2761 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2762 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2763 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2764 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2765 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2766 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2767 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2768 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2769 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2770 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2771 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2772 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2773 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2774 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2775 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2776 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2777 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2778 [CLKID_VPU] = &gxbb_vpu.hw, 2779 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2780 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2781 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2782 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2783 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2784 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2785 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2786 [CLKID_VAPB] = &gxbb_vapb.hw, 2787 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2788 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2789 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2790 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2791 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2792 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2793 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2794 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2795 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2796 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2797 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2798 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2799 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2800 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2801 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 2802 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 2803 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 2804 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 2805 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 2806 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 2807 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 2808 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 2809 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 2810 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 2811 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 2812 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 2813 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 2814 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 2815 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 2816 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 2817 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 2818 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 2819 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 2820 [CLKID_VCLK] = &gxbb_vclk.hw, 2821 [CLKID_VCLK2] = &gxbb_vclk2.hw, 2822 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 2823 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 2824 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 2825 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 2826 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 2827 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 2828 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 2829 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 2830 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 2831 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 2832 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 2833 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 2834 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 2835 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 2836 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 2837 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 2838 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 2839 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 2840 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 2841 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 2842 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 2843 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 2844 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 2845 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 2846 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 2847 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 2848 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 2849 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 2850 [CLKID_HDMI] = &gxbb_hdmi.hw, 2851 [NR_CLKS] = NULL, 2852 }, 2853 .num = NR_CLKS, 2854 }; 2855 2856 static struct clk_regmap *const gxbb_clk_regmaps[] = { 2857 &gxbb_gp0_pll_dco, 2858 &gxbb_hdmi_pll, 2859 &gxbb_hdmi_pll_od, 2860 &gxbb_hdmi_pll_od2, 2861 &gxbb_hdmi_pll_dco, 2862 }; 2863 2864 static struct clk_regmap *const gxl_clk_regmaps[] = { 2865 &gxl_gp0_pll_dco, 2866 &gxl_hdmi_pll, 2867 &gxl_hdmi_pll_od, 2868 &gxl_hdmi_pll_od2, 2869 &gxl_hdmi_pll_dco, 2870 }; 2871 2872 static struct clk_regmap *const gx_clk_regmaps[] = { 2873 &gxbb_clk81, 2874 &gxbb_ddr, 2875 &gxbb_dos, 2876 &gxbb_isa, 2877 &gxbb_pl301, 2878 &gxbb_periphs, 2879 &gxbb_spicc, 2880 &gxbb_i2c, 2881 &gxbb_sar_adc, 2882 &gxbb_smart_card, 2883 &gxbb_rng0, 2884 &gxbb_uart0, 2885 &gxbb_sdhc, 2886 &gxbb_stream, 2887 &gxbb_async_fifo, 2888 &gxbb_sdio, 2889 &gxbb_abuf, 2890 &gxbb_hiu_iface, 2891 &gxbb_assist_misc, 2892 &gxbb_spi, 2893 &gxbb_i2s_spdif, 2894 &gxbb_eth, 2895 &gxbb_demux, 2896 &gxbb_aiu_glue, 2897 &gxbb_iec958, 2898 &gxbb_i2s_out, 2899 &gxbb_amclk, 2900 &gxbb_aififo2, 2901 &gxbb_mixer, 2902 &gxbb_mixer_iface, 2903 &gxbb_adc, 2904 &gxbb_blkmv, 2905 &gxbb_aiu, 2906 &gxbb_uart1, 2907 &gxbb_g2d, 2908 &gxbb_usb0, 2909 &gxbb_usb1, 2910 &gxbb_reset, 2911 &gxbb_nand, 2912 &gxbb_dos_parser, 2913 &gxbb_usb, 2914 &gxbb_vdin1, 2915 &gxbb_ahb_arb0, 2916 &gxbb_efuse, 2917 &gxbb_boot_rom, 2918 &gxbb_ahb_data_bus, 2919 &gxbb_ahb_ctrl_bus, 2920 &gxbb_hdmi_intr_sync, 2921 &gxbb_hdmi_pclk, 2922 &gxbb_usb1_ddr_bridge, 2923 &gxbb_usb0_ddr_bridge, 2924 &gxbb_mmc_pclk, 2925 &gxbb_dvin, 2926 &gxbb_uart2, 2927 &gxbb_sana, 2928 &gxbb_vpu_intr, 2929 &gxbb_sec_ahb_ahb3_bridge, 2930 &gxbb_clk81_a53, 2931 &gxbb_vclk2_venci0, 2932 &gxbb_vclk2_venci1, 2933 &gxbb_vclk2_vencp0, 2934 &gxbb_vclk2_vencp1, 2935 &gxbb_gclk_venci_int0, 2936 &gxbb_gclk_vencp_int, 2937 &gxbb_dac_clk, 2938 &gxbb_aoclk_gate, 2939 &gxbb_iec958_gate, 2940 &gxbb_enc480p, 2941 &gxbb_rng1, 2942 &gxbb_gclk_venci_int1, 2943 &gxbb_vclk2_venclmcc, 2944 &gxbb_vclk2_vencl, 2945 &gxbb_vclk_other, 2946 &gxbb_edp, 2947 &gxbb_ao_media_cpu, 2948 &gxbb_ao_ahb_sram, 2949 &gxbb_ao_ahb_bus, 2950 &gxbb_ao_iface, 2951 &gxbb_ao_i2c, 2952 &gxbb_emmc_a, 2953 &gxbb_emmc_b, 2954 &gxbb_emmc_c, 2955 &gxbb_sar_adc_clk, 2956 &gxbb_mali_0, 2957 &gxbb_mali_1, 2958 &gxbb_cts_amclk, 2959 &gxbb_cts_mclk_i958, 2960 &gxbb_32k_clk, 2961 &gxbb_sd_emmc_a_clk0, 2962 &gxbb_sd_emmc_b_clk0, 2963 &gxbb_sd_emmc_c_clk0, 2964 &gxbb_vpu_0, 2965 &gxbb_vpu_1, 2966 &gxbb_vapb_0, 2967 &gxbb_vapb_1, 2968 &gxbb_vapb, 2969 &gxbb_mpeg_clk_div, 2970 &gxbb_sar_adc_clk_div, 2971 &gxbb_mali_0_div, 2972 &gxbb_mali_1_div, 2973 &gxbb_cts_mclk_i958_div, 2974 &gxbb_32k_clk_div, 2975 &gxbb_sd_emmc_a_clk0_div, 2976 &gxbb_sd_emmc_b_clk0_div, 2977 &gxbb_sd_emmc_c_clk0_div, 2978 &gxbb_vpu_0_div, 2979 &gxbb_vpu_1_div, 2980 &gxbb_vapb_0_div, 2981 &gxbb_vapb_1_div, 2982 &gxbb_mpeg_clk_sel, 2983 &gxbb_sar_adc_clk_sel, 2984 &gxbb_mali_0_sel, 2985 &gxbb_mali_1_sel, 2986 &gxbb_mali, 2987 &gxbb_cts_amclk_sel, 2988 &gxbb_cts_mclk_i958_sel, 2989 &gxbb_cts_i958, 2990 &gxbb_32k_clk_sel, 2991 &gxbb_sd_emmc_a_clk0_sel, 2992 &gxbb_sd_emmc_b_clk0_sel, 2993 &gxbb_sd_emmc_c_clk0_sel, 2994 &gxbb_vpu_0_sel, 2995 &gxbb_vpu_1_sel, 2996 &gxbb_vpu, 2997 &gxbb_vapb_0_sel, 2998 &gxbb_vapb_1_sel, 2999 &gxbb_vapb_sel, 3000 &gxbb_mpll0, 3001 &gxbb_mpll1, 3002 &gxbb_mpll2, 3003 &gxbb_mpll0_div, 3004 &gxbb_mpll1_div, 3005 &gxbb_mpll2_div, 3006 &gxbb_cts_amclk_div, 3007 &gxbb_fixed_pll, 3008 &gxbb_sys_pll, 3009 &gxbb_mpll_prediv, 3010 &gxbb_fclk_div2, 3011 &gxbb_fclk_div3, 3012 &gxbb_fclk_div4, 3013 &gxbb_fclk_div5, 3014 &gxbb_fclk_div7, 3015 &gxbb_vdec_1_sel, 3016 &gxbb_vdec_1_div, 3017 &gxbb_vdec_1, 3018 &gxbb_vdec_hevc_sel, 3019 &gxbb_vdec_hevc_div, 3020 &gxbb_vdec_hevc, 3021 &gxbb_gen_clk_sel, 3022 &gxbb_gen_clk_div, 3023 &gxbb_gen_clk, 3024 &gxbb_fixed_pll_dco, 3025 &gxbb_sys_pll_dco, 3026 &gxbb_gp0_pll, 3027 &gxbb_vid_pll, 3028 &gxbb_vid_pll_sel, 3029 &gxbb_vid_pll_div, 3030 &gxbb_vclk, 3031 &gxbb_vclk_sel, 3032 &gxbb_vclk_div, 3033 &gxbb_vclk_input, 3034 &gxbb_vclk_div1, 3035 &gxbb_vclk_div2_en, 3036 &gxbb_vclk_div4_en, 3037 &gxbb_vclk_div6_en, 3038 &gxbb_vclk_div12_en, 3039 &gxbb_vclk2, 3040 &gxbb_vclk2_sel, 3041 &gxbb_vclk2_div, 3042 &gxbb_vclk2_input, 3043 &gxbb_vclk2_div1, 3044 &gxbb_vclk2_div2_en, 3045 &gxbb_vclk2_div4_en, 3046 &gxbb_vclk2_div6_en, 3047 &gxbb_vclk2_div12_en, 3048 &gxbb_cts_enci, 3049 &gxbb_cts_enci_sel, 3050 &gxbb_cts_encp, 3051 &gxbb_cts_encp_sel, 3052 &gxbb_cts_vdac, 3053 &gxbb_cts_vdac_sel, 3054 &gxbb_hdmi_tx, 3055 &gxbb_hdmi_tx_sel, 3056 &gxbb_hdmi_sel, 3057 &gxbb_hdmi_div, 3058 &gxbb_hdmi, 3059 }; 3060 3061 struct clkc_data { 3062 struct clk_regmap *const *regmap_clks; 3063 unsigned int regmap_clks_count; 3064 struct clk_hw_onecell_data *hw_onecell_data; 3065 }; 3066 3067 static const struct clkc_data gxbb_clkc_data = { 3068 .regmap_clks = gxbb_clk_regmaps, 3069 .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps), 3070 .hw_onecell_data = &gxbb_hw_onecell_data, 3071 }; 3072 3073 static const struct clkc_data gxl_clkc_data = { 3074 .regmap_clks = gxl_clk_regmaps, 3075 .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps), 3076 .hw_onecell_data = &gxl_hw_onecell_data, 3077 }; 3078 3079 static const struct of_device_id clkc_match_table[] = { 3080 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 3081 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 3082 {}, 3083 }; 3084 3085 static int gxbb_clkc_probe(struct platform_device *pdev) 3086 { 3087 const struct clkc_data *clkc_data; 3088 struct regmap *map; 3089 int ret, i; 3090 struct device *dev = &pdev->dev; 3091 3092 clkc_data = of_device_get_match_data(dev); 3093 if (!clkc_data) 3094 return -EINVAL; 3095 3096 /* Get the hhi system controller node if available */ 3097 map = syscon_node_to_regmap(of_get_parent(dev->of_node)); 3098 if (IS_ERR(map)) { 3099 dev_err(dev, "failed to get HHI regmap\n"); 3100 return PTR_ERR(map); 3101 } 3102 3103 /* Populate regmap for the common regmap backed clocks */ 3104 for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++) 3105 gx_clk_regmaps[i]->map = map; 3106 3107 /* Populate regmap for soc specific clocks */ 3108 for (i = 0; i < clkc_data->regmap_clks_count; i++) 3109 clkc_data->regmap_clks[i]->map = map; 3110 3111 /* Register all clks */ 3112 for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { 3113 /* array might be sparse */ 3114 if (!clkc_data->hw_onecell_data->hws[i]) 3115 continue; 3116 3117 ret = devm_clk_hw_register(dev, 3118 clkc_data->hw_onecell_data->hws[i]); 3119 if (ret) { 3120 dev_err(dev, "Clock registration failed\n"); 3121 return ret; 3122 } 3123 } 3124 3125 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 3126 clkc_data->hw_onecell_data); 3127 } 3128 3129 static struct platform_driver gxbb_driver = { 3130 .probe = gxbb_clkc_probe, 3131 .driver = { 3132 .name = "gxbb-clkc", 3133 .of_match_table = clkc_match_table, 3134 }, 3135 }; 3136 3137 builtin_platform_driver(gxbb_driver); 3138