1 /* 2 * AmLogic S905 / GXBB Clock Controller Driver 3 * 4 * Copyright (c) 2016 AmLogic, Inc. 5 * Michael Turquette <mturquette@baylibre.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/clk.h> 21 #include <linux/clk-provider.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/init.h> 26 27 #include "clkc.h" 28 #include "gxbb.h" 29 30 static DEFINE_SPINLOCK(clk_lock); 31 32 static const struct pll_rate_table sys_pll_rate_table[] = { 33 PLL_RATE(24000000, 56, 1, 2), 34 PLL_RATE(48000000, 64, 1, 2), 35 PLL_RATE(72000000, 72, 1, 2), 36 PLL_RATE(96000000, 64, 1, 2), 37 PLL_RATE(120000000, 80, 1, 2), 38 PLL_RATE(144000000, 96, 1, 2), 39 PLL_RATE(168000000, 56, 1, 1), 40 PLL_RATE(192000000, 64, 1, 1), 41 PLL_RATE(216000000, 72, 1, 1), 42 PLL_RATE(240000000, 80, 1, 1), 43 PLL_RATE(264000000, 88, 1, 1), 44 PLL_RATE(288000000, 96, 1, 1), 45 PLL_RATE(312000000, 52, 1, 2), 46 PLL_RATE(336000000, 56, 1, 2), 47 PLL_RATE(360000000, 60, 1, 2), 48 PLL_RATE(384000000, 64, 1, 2), 49 PLL_RATE(408000000, 68, 1, 2), 50 PLL_RATE(432000000, 72, 1, 2), 51 PLL_RATE(456000000, 76, 1, 2), 52 PLL_RATE(480000000, 80, 1, 2), 53 PLL_RATE(504000000, 84, 1, 2), 54 PLL_RATE(528000000, 88, 1, 2), 55 PLL_RATE(552000000, 92, 1, 2), 56 PLL_RATE(576000000, 96, 1, 2), 57 PLL_RATE(600000000, 50, 1, 1), 58 PLL_RATE(624000000, 52, 1, 1), 59 PLL_RATE(648000000, 54, 1, 1), 60 PLL_RATE(672000000, 56, 1, 1), 61 PLL_RATE(696000000, 58, 1, 1), 62 PLL_RATE(720000000, 60, 1, 1), 63 PLL_RATE(744000000, 62, 1, 1), 64 PLL_RATE(768000000, 64, 1, 1), 65 PLL_RATE(792000000, 66, 1, 1), 66 PLL_RATE(816000000, 68, 1, 1), 67 PLL_RATE(840000000, 70, 1, 1), 68 PLL_RATE(864000000, 72, 1, 1), 69 PLL_RATE(888000000, 74, 1, 1), 70 PLL_RATE(912000000, 76, 1, 1), 71 PLL_RATE(936000000, 78, 1, 1), 72 PLL_RATE(960000000, 80, 1, 1), 73 PLL_RATE(984000000, 82, 1, 1), 74 PLL_RATE(1008000000, 84, 1, 1), 75 PLL_RATE(1032000000, 86, 1, 1), 76 PLL_RATE(1056000000, 88, 1, 1), 77 PLL_RATE(1080000000, 90, 1, 1), 78 PLL_RATE(1104000000, 92, 1, 1), 79 PLL_RATE(1128000000, 94, 1, 1), 80 PLL_RATE(1152000000, 96, 1, 1), 81 PLL_RATE(1176000000, 98, 1, 1), 82 PLL_RATE(1200000000, 50, 1, 0), 83 PLL_RATE(1224000000, 51, 1, 0), 84 PLL_RATE(1248000000, 52, 1, 0), 85 PLL_RATE(1272000000, 53, 1, 0), 86 PLL_RATE(1296000000, 54, 1, 0), 87 PLL_RATE(1320000000, 55, 1, 0), 88 PLL_RATE(1344000000, 56, 1, 0), 89 PLL_RATE(1368000000, 57, 1, 0), 90 PLL_RATE(1392000000, 58, 1, 0), 91 PLL_RATE(1416000000, 59, 1, 0), 92 PLL_RATE(1440000000, 60, 1, 0), 93 PLL_RATE(1464000000, 61, 1, 0), 94 PLL_RATE(1488000000, 62, 1, 0), 95 PLL_RATE(1512000000, 63, 1, 0), 96 PLL_RATE(1536000000, 64, 1, 0), 97 PLL_RATE(1560000000, 65, 1, 0), 98 PLL_RATE(1584000000, 66, 1, 0), 99 PLL_RATE(1608000000, 67, 1, 0), 100 PLL_RATE(1632000000, 68, 1, 0), 101 PLL_RATE(1656000000, 68, 1, 0), 102 PLL_RATE(1680000000, 68, 1, 0), 103 PLL_RATE(1704000000, 68, 1, 0), 104 PLL_RATE(1728000000, 69, 1, 0), 105 PLL_RATE(1752000000, 69, 1, 0), 106 PLL_RATE(1776000000, 69, 1, 0), 107 PLL_RATE(1800000000, 69, 1, 0), 108 PLL_RATE(1824000000, 70, 1, 0), 109 PLL_RATE(1848000000, 70, 1, 0), 110 PLL_RATE(1872000000, 70, 1, 0), 111 PLL_RATE(1896000000, 70, 1, 0), 112 PLL_RATE(1920000000, 71, 1, 0), 113 PLL_RATE(1944000000, 71, 1, 0), 114 PLL_RATE(1968000000, 71, 1, 0), 115 PLL_RATE(1992000000, 71, 1, 0), 116 PLL_RATE(2016000000, 72, 1, 0), 117 PLL_RATE(2040000000, 72, 1, 0), 118 PLL_RATE(2064000000, 72, 1, 0), 119 PLL_RATE(2088000000, 72, 1, 0), 120 PLL_RATE(2112000000, 73, 1, 0), 121 { /* sentinel */ }, 122 }; 123 124 static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = { 125 PLL_RATE(96000000, 32, 1, 3), 126 PLL_RATE(99000000, 33, 1, 3), 127 PLL_RATE(102000000, 34, 1, 3), 128 PLL_RATE(105000000, 35, 1, 3), 129 PLL_RATE(108000000, 36, 1, 3), 130 PLL_RATE(111000000, 37, 1, 3), 131 PLL_RATE(114000000, 38, 1, 3), 132 PLL_RATE(117000000, 39, 1, 3), 133 PLL_RATE(120000000, 40, 1, 3), 134 PLL_RATE(123000000, 41, 1, 3), 135 PLL_RATE(126000000, 42, 1, 3), 136 PLL_RATE(129000000, 43, 1, 3), 137 PLL_RATE(132000000, 44, 1, 3), 138 PLL_RATE(135000000, 45, 1, 3), 139 PLL_RATE(138000000, 46, 1, 3), 140 PLL_RATE(141000000, 47, 1, 3), 141 PLL_RATE(144000000, 48, 1, 3), 142 PLL_RATE(147000000, 49, 1, 3), 143 PLL_RATE(150000000, 50, 1, 3), 144 PLL_RATE(153000000, 51, 1, 3), 145 PLL_RATE(156000000, 52, 1, 3), 146 PLL_RATE(159000000, 53, 1, 3), 147 PLL_RATE(162000000, 54, 1, 3), 148 PLL_RATE(165000000, 55, 1, 3), 149 PLL_RATE(168000000, 56, 1, 3), 150 PLL_RATE(171000000, 57, 1, 3), 151 PLL_RATE(174000000, 58, 1, 3), 152 PLL_RATE(177000000, 59, 1, 3), 153 PLL_RATE(180000000, 60, 1, 3), 154 PLL_RATE(183000000, 61, 1, 3), 155 PLL_RATE(186000000, 62, 1, 3), 156 PLL_RATE(192000000, 32, 1, 2), 157 PLL_RATE(198000000, 33, 1, 2), 158 PLL_RATE(204000000, 34, 1, 2), 159 PLL_RATE(210000000, 35, 1, 2), 160 PLL_RATE(216000000, 36, 1, 2), 161 PLL_RATE(222000000, 37, 1, 2), 162 PLL_RATE(228000000, 38, 1, 2), 163 PLL_RATE(234000000, 39, 1, 2), 164 PLL_RATE(240000000, 40, 1, 2), 165 PLL_RATE(246000000, 41, 1, 2), 166 PLL_RATE(252000000, 42, 1, 2), 167 PLL_RATE(258000000, 43, 1, 2), 168 PLL_RATE(264000000, 44, 1, 2), 169 PLL_RATE(270000000, 45, 1, 2), 170 PLL_RATE(276000000, 46, 1, 2), 171 PLL_RATE(282000000, 47, 1, 2), 172 PLL_RATE(288000000, 48, 1, 2), 173 PLL_RATE(294000000, 49, 1, 2), 174 PLL_RATE(300000000, 50, 1, 2), 175 PLL_RATE(306000000, 51, 1, 2), 176 PLL_RATE(312000000, 52, 1, 2), 177 PLL_RATE(318000000, 53, 1, 2), 178 PLL_RATE(324000000, 54, 1, 2), 179 PLL_RATE(330000000, 55, 1, 2), 180 PLL_RATE(336000000, 56, 1, 2), 181 PLL_RATE(342000000, 57, 1, 2), 182 PLL_RATE(348000000, 58, 1, 2), 183 PLL_RATE(354000000, 59, 1, 2), 184 PLL_RATE(360000000, 60, 1, 2), 185 PLL_RATE(366000000, 61, 1, 2), 186 PLL_RATE(372000000, 62, 1, 2), 187 PLL_RATE(384000000, 32, 1, 1), 188 PLL_RATE(396000000, 33, 1, 1), 189 PLL_RATE(408000000, 34, 1, 1), 190 PLL_RATE(420000000, 35, 1, 1), 191 PLL_RATE(432000000, 36, 1, 1), 192 PLL_RATE(444000000, 37, 1, 1), 193 PLL_RATE(456000000, 38, 1, 1), 194 PLL_RATE(468000000, 39, 1, 1), 195 PLL_RATE(480000000, 40, 1, 1), 196 PLL_RATE(492000000, 41, 1, 1), 197 PLL_RATE(504000000, 42, 1, 1), 198 PLL_RATE(516000000, 43, 1, 1), 199 PLL_RATE(528000000, 44, 1, 1), 200 PLL_RATE(540000000, 45, 1, 1), 201 PLL_RATE(552000000, 46, 1, 1), 202 PLL_RATE(564000000, 47, 1, 1), 203 PLL_RATE(576000000, 48, 1, 1), 204 PLL_RATE(588000000, 49, 1, 1), 205 PLL_RATE(600000000, 50, 1, 1), 206 PLL_RATE(612000000, 51, 1, 1), 207 PLL_RATE(624000000, 52, 1, 1), 208 PLL_RATE(636000000, 53, 1, 1), 209 PLL_RATE(648000000, 54, 1, 1), 210 PLL_RATE(660000000, 55, 1, 1), 211 PLL_RATE(672000000, 56, 1, 1), 212 PLL_RATE(684000000, 57, 1, 1), 213 PLL_RATE(696000000, 58, 1, 1), 214 PLL_RATE(708000000, 59, 1, 1), 215 PLL_RATE(720000000, 60, 1, 1), 216 PLL_RATE(732000000, 61, 1, 1), 217 PLL_RATE(744000000, 62, 1, 1), 218 PLL_RATE(768000000, 32, 1, 0), 219 PLL_RATE(792000000, 33, 1, 0), 220 PLL_RATE(816000000, 34, 1, 0), 221 PLL_RATE(840000000, 35, 1, 0), 222 PLL_RATE(864000000, 36, 1, 0), 223 PLL_RATE(888000000, 37, 1, 0), 224 PLL_RATE(912000000, 38, 1, 0), 225 PLL_RATE(936000000, 39, 1, 0), 226 PLL_RATE(960000000, 40, 1, 0), 227 PLL_RATE(984000000, 41, 1, 0), 228 PLL_RATE(1008000000, 42, 1, 0), 229 PLL_RATE(1032000000, 43, 1, 0), 230 PLL_RATE(1056000000, 44, 1, 0), 231 PLL_RATE(1080000000, 45, 1, 0), 232 PLL_RATE(1104000000, 46, 1, 0), 233 PLL_RATE(1128000000, 47, 1, 0), 234 PLL_RATE(1152000000, 48, 1, 0), 235 PLL_RATE(1176000000, 49, 1, 0), 236 PLL_RATE(1200000000, 50, 1, 0), 237 PLL_RATE(1224000000, 51, 1, 0), 238 PLL_RATE(1248000000, 52, 1, 0), 239 PLL_RATE(1272000000, 53, 1, 0), 240 PLL_RATE(1296000000, 54, 1, 0), 241 PLL_RATE(1320000000, 55, 1, 0), 242 PLL_RATE(1344000000, 56, 1, 0), 243 PLL_RATE(1368000000, 57, 1, 0), 244 PLL_RATE(1392000000, 58, 1, 0), 245 PLL_RATE(1416000000, 59, 1, 0), 246 PLL_RATE(1440000000, 60, 1, 0), 247 PLL_RATE(1464000000, 61, 1, 0), 248 PLL_RATE(1488000000, 62, 1, 0), 249 { /* sentinel */ }, 250 }; 251 252 static const struct pll_rate_table gxl_gp0_pll_rate_table[] = { 253 PLL_RATE(504000000, 42, 1, 1), 254 PLL_RATE(516000000, 43, 1, 1), 255 PLL_RATE(528000000, 44, 1, 1), 256 PLL_RATE(540000000, 45, 1, 1), 257 PLL_RATE(552000000, 46, 1, 1), 258 PLL_RATE(564000000, 47, 1, 1), 259 PLL_RATE(576000000, 48, 1, 1), 260 PLL_RATE(588000000, 49, 1, 1), 261 PLL_RATE(600000000, 50, 1, 1), 262 PLL_RATE(612000000, 51, 1, 1), 263 PLL_RATE(624000000, 52, 1, 1), 264 PLL_RATE(636000000, 53, 1, 1), 265 PLL_RATE(648000000, 54, 1, 1), 266 PLL_RATE(660000000, 55, 1, 1), 267 PLL_RATE(672000000, 56, 1, 1), 268 PLL_RATE(684000000, 57, 1, 1), 269 PLL_RATE(696000000, 58, 1, 1), 270 PLL_RATE(708000000, 59, 1, 1), 271 PLL_RATE(720000000, 60, 1, 1), 272 PLL_RATE(732000000, 61, 1, 1), 273 PLL_RATE(744000000, 62, 1, 1), 274 PLL_RATE(756000000, 63, 1, 1), 275 PLL_RATE(768000000, 64, 1, 1), 276 PLL_RATE(780000000, 65, 1, 1), 277 PLL_RATE(792000000, 66, 1, 1), 278 { /* sentinel */ }, 279 }; 280 281 static const struct clk_div_table cpu_div_table[] = { 282 { .val = 1, .div = 1 }, 283 { .val = 2, .div = 2 }, 284 { .val = 3, .div = 3 }, 285 { .val = 2, .div = 4 }, 286 { .val = 3, .div = 6 }, 287 { .val = 4, .div = 8 }, 288 { .val = 5, .div = 10 }, 289 { .val = 6, .div = 12 }, 290 { .val = 7, .div = 14 }, 291 { .val = 8, .div = 16 }, 292 { /* sentinel */ }, 293 }; 294 295 static struct meson_clk_pll gxbb_fixed_pll = { 296 .m = { 297 .reg_off = HHI_MPLL_CNTL, 298 .shift = 0, 299 .width = 9, 300 }, 301 .n = { 302 .reg_off = HHI_MPLL_CNTL, 303 .shift = 9, 304 .width = 5, 305 }, 306 .od = { 307 .reg_off = HHI_MPLL_CNTL, 308 .shift = 16, 309 .width = 2, 310 }, 311 .lock = &clk_lock, 312 .hw.init = &(struct clk_init_data){ 313 .name = "fixed_pll", 314 .ops = &meson_clk_pll_ro_ops, 315 .parent_names = (const char *[]){ "xtal" }, 316 .num_parents = 1, 317 .flags = CLK_GET_RATE_NOCACHE, 318 }, 319 }; 320 321 static struct meson_clk_pll gxbb_hdmi_pll = { 322 .m = { 323 .reg_off = HHI_HDMI_PLL_CNTL, 324 .shift = 0, 325 .width = 9, 326 }, 327 .n = { 328 .reg_off = HHI_HDMI_PLL_CNTL, 329 .shift = 9, 330 .width = 5, 331 }, 332 .frac = { 333 .reg_off = HHI_HDMI_PLL_CNTL2, 334 .shift = 0, 335 .width = 12, 336 }, 337 .od = { 338 .reg_off = HHI_HDMI_PLL_CNTL2, 339 .shift = 16, 340 .width = 2, 341 }, 342 .od2 = { 343 .reg_off = HHI_HDMI_PLL_CNTL2, 344 .shift = 22, 345 .width = 2, 346 }, 347 .lock = &clk_lock, 348 .hw.init = &(struct clk_init_data){ 349 .name = "hdmi_pll", 350 .ops = &meson_clk_pll_ro_ops, 351 .parent_names = (const char *[]){ "xtal" }, 352 .num_parents = 1, 353 .flags = CLK_GET_RATE_NOCACHE, 354 }, 355 }; 356 357 static struct meson_clk_pll gxbb_sys_pll = { 358 .m = { 359 .reg_off = HHI_SYS_PLL_CNTL, 360 .shift = 0, 361 .width = 9, 362 }, 363 .n = { 364 .reg_off = HHI_SYS_PLL_CNTL, 365 .shift = 9, 366 .width = 5, 367 }, 368 .od = { 369 .reg_off = HHI_SYS_PLL_CNTL, 370 .shift = 10, 371 .width = 2, 372 }, 373 .rate_table = sys_pll_rate_table, 374 .rate_count = ARRAY_SIZE(sys_pll_rate_table), 375 .lock = &clk_lock, 376 .hw.init = &(struct clk_init_data){ 377 .name = "sys_pll", 378 .ops = &meson_clk_pll_ro_ops, 379 .parent_names = (const char *[]){ "xtal" }, 380 .num_parents = 1, 381 .flags = CLK_GET_RATE_NOCACHE, 382 }, 383 }; 384 385 struct pll_params_table gxbb_gp0_params_table[] = { 386 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228), 387 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000), 388 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4), 389 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d), 390 }; 391 392 static struct meson_clk_pll gxbb_gp0_pll = { 393 .m = { 394 .reg_off = HHI_GP0_PLL_CNTL, 395 .shift = 0, 396 .width = 9, 397 }, 398 .n = { 399 .reg_off = HHI_GP0_PLL_CNTL, 400 .shift = 9, 401 .width = 5, 402 }, 403 .od = { 404 .reg_off = HHI_GP0_PLL_CNTL, 405 .shift = 16, 406 .width = 2, 407 }, 408 .params = { 409 .params_table = gxbb_gp0_params_table, 410 .params_count = ARRAY_SIZE(gxbb_gp0_params_table), 411 .no_init_reset = true, 412 .clear_reset_for_lock = true, 413 }, 414 .rate_table = gxbb_gp0_pll_rate_table, 415 .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table), 416 .lock = &clk_lock, 417 .hw.init = &(struct clk_init_data){ 418 .name = "gp0_pll", 419 .ops = &meson_clk_pll_ops, 420 .parent_names = (const char *[]){ "xtal" }, 421 .num_parents = 1, 422 .flags = CLK_GET_RATE_NOCACHE, 423 }, 424 }; 425 426 struct pll_params_table gxl_gp0_params_table[] = { 427 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250), 428 PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000), 429 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be), 430 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288), 431 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d), 432 PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000), 433 }; 434 435 static struct meson_clk_pll gxl_gp0_pll = { 436 .m = { 437 .reg_off = HHI_GP0_PLL_CNTL, 438 .shift = 0, 439 .width = 9, 440 }, 441 .n = { 442 .reg_off = HHI_GP0_PLL_CNTL, 443 .shift = 9, 444 .width = 5, 445 }, 446 .od = { 447 .reg_off = HHI_GP0_PLL_CNTL, 448 .shift = 16, 449 .width = 2, 450 }, 451 .params = { 452 .params_table = gxl_gp0_params_table, 453 .params_count = ARRAY_SIZE(gxl_gp0_params_table), 454 .no_init_reset = true, 455 .reset_lock_loop = true, 456 }, 457 .rate_table = gxl_gp0_pll_rate_table, 458 .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table), 459 .lock = &clk_lock, 460 .hw.init = &(struct clk_init_data){ 461 .name = "gp0_pll", 462 .ops = &meson_clk_pll_ops, 463 .parent_names = (const char *[]){ "xtal" }, 464 .num_parents = 1, 465 .flags = CLK_GET_RATE_NOCACHE, 466 }, 467 }; 468 469 static struct clk_fixed_factor gxbb_fclk_div2 = { 470 .mult = 1, 471 .div = 2, 472 .hw.init = &(struct clk_init_data){ 473 .name = "fclk_div2", 474 .ops = &clk_fixed_factor_ops, 475 .parent_names = (const char *[]){ "fixed_pll" }, 476 .num_parents = 1, 477 }, 478 }; 479 480 static struct clk_fixed_factor gxbb_fclk_div3 = { 481 .mult = 1, 482 .div = 3, 483 .hw.init = &(struct clk_init_data){ 484 .name = "fclk_div3", 485 .ops = &clk_fixed_factor_ops, 486 .parent_names = (const char *[]){ "fixed_pll" }, 487 .num_parents = 1, 488 }, 489 }; 490 491 static struct clk_fixed_factor gxbb_fclk_div4 = { 492 .mult = 1, 493 .div = 4, 494 .hw.init = &(struct clk_init_data){ 495 .name = "fclk_div4", 496 .ops = &clk_fixed_factor_ops, 497 .parent_names = (const char *[]){ "fixed_pll" }, 498 .num_parents = 1, 499 }, 500 }; 501 502 static struct clk_fixed_factor gxbb_fclk_div5 = { 503 .mult = 1, 504 .div = 5, 505 .hw.init = &(struct clk_init_data){ 506 .name = "fclk_div5", 507 .ops = &clk_fixed_factor_ops, 508 .parent_names = (const char *[]){ "fixed_pll" }, 509 .num_parents = 1, 510 }, 511 }; 512 513 static struct clk_fixed_factor gxbb_fclk_div7 = { 514 .mult = 1, 515 .div = 7, 516 .hw.init = &(struct clk_init_data){ 517 .name = "fclk_div7", 518 .ops = &clk_fixed_factor_ops, 519 .parent_names = (const char *[]){ "fixed_pll" }, 520 .num_parents = 1, 521 }, 522 }; 523 524 static struct meson_clk_mpll gxbb_mpll0 = { 525 .sdm = { 526 .reg_off = HHI_MPLL_CNTL7, 527 .shift = 0, 528 .width = 14, 529 }, 530 .sdm_en = { 531 .reg_off = HHI_MPLL_CNTL7, 532 .shift = 15, 533 .width = 1, 534 }, 535 .n2 = { 536 .reg_off = HHI_MPLL_CNTL7, 537 .shift = 16, 538 .width = 9, 539 }, 540 .en = { 541 .reg_off = HHI_MPLL_CNTL7, 542 .shift = 14, 543 .width = 1, 544 }, 545 .lock = &clk_lock, 546 .hw.init = &(struct clk_init_data){ 547 .name = "mpll0", 548 .ops = &meson_clk_mpll_ops, 549 .parent_names = (const char *[]){ "fixed_pll" }, 550 .num_parents = 1, 551 }, 552 }; 553 554 static struct meson_clk_mpll gxbb_mpll1 = { 555 .sdm = { 556 .reg_off = HHI_MPLL_CNTL8, 557 .shift = 0, 558 .width = 14, 559 }, 560 .sdm_en = { 561 .reg_off = HHI_MPLL_CNTL8, 562 .shift = 15, 563 .width = 1, 564 }, 565 .n2 = { 566 .reg_off = HHI_MPLL_CNTL8, 567 .shift = 16, 568 .width = 9, 569 }, 570 .en = { 571 .reg_off = HHI_MPLL_CNTL8, 572 .shift = 14, 573 .width = 1, 574 }, 575 .lock = &clk_lock, 576 .hw.init = &(struct clk_init_data){ 577 .name = "mpll1", 578 .ops = &meson_clk_mpll_ops, 579 .parent_names = (const char *[]){ "fixed_pll" }, 580 .num_parents = 1, 581 }, 582 }; 583 584 static struct meson_clk_mpll gxbb_mpll2 = { 585 .sdm = { 586 .reg_off = HHI_MPLL_CNTL9, 587 .shift = 0, 588 .width = 14, 589 }, 590 .sdm_en = { 591 .reg_off = HHI_MPLL_CNTL9, 592 .shift = 15, 593 .width = 1, 594 }, 595 .n2 = { 596 .reg_off = HHI_MPLL_CNTL9, 597 .shift = 16, 598 .width = 9, 599 }, 600 .en = { 601 .reg_off = HHI_MPLL_CNTL9, 602 .shift = 14, 603 .width = 1, 604 }, 605 .lock = &clk_lock, 606 .hw.init = &(struct clk_init_data){ 607 .name = "mpll2", 608 .ops = &meson_clk_mpll_ops, 609 .parent_names = (const char *[]){ "fixed_pll" }, 610 .num_parents = 1, 611 }, 612 }; 613 614 /* 615 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL 616 * post-dividers and should be modeled with their respective PLLs via the 617 * forthcoming coordinated clock rates feature 618 */ 619 static struct meson_clk_cpu gxbb_cpu_clk = { 620 .reg_off = HHI_SYS_CPU_CLK_CNTL1, 621 .div_table = cpu_div_table, 622 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb, 623 .hw.init = &(struct clk_init_data){ 624 .name = "cpu_clk", 625 .ops = &meson_clk_cpu_ops, 626 .parent_names = (const char *[]){ "sys_pll" }, 627 .num_parents = 1, 628 }, 629 }; 630 631 static u32 mux_table_clk81[] = { 6, 5, 7 }; 632 633 static struct clk_mux gxbb_mpeg_clk_sel = { 634 .reg = (void *)HHI_MPEG_CLK_CNTL, 635 .mask = 0x7, 636 .shift = 12, 637 .flags = CLK_MUX_READ_ONLY, 638 .table = mux_table_clk81, 639 .lock = &clk_lock, 640 .hw.init = &(struct clk_init_data){ 641 .name = "mpeg_clk_sel", 642 .ops = &clk_mux_ro_ops, 643 /* 644 * FIXME bits 14:12 selects from 8 possible parents: 645 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 646 * fclk_div4, fclk_div3, fclk_div5 647 */ 648 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", 649 "fclk_div5" }, 650 .num_parents = 3, 651 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), 652 }, 653 }; 654 655 static struct clk_divider gxbb_mpeg_clk_div = { 656 .reg = (void *)HHI_MPEG_CLK_CNTL, 657 .shift = 0, 658 .width = 7, 659 .lock = &clk_lock, 660 .hw.init = &(struct clk_init_data){ 661 .name = "mpeg_clk_div", 662 .ops = &clk_divider_ops, 663 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 664 .num_parents = 1, 665 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), 666 }, 667 }; 668 669 /* the mother of dragons^W gates */ 670 static struct clk_gate gxbb_clk81 = { 671 .reg = (void *)HHI_MPEG_CLK_CNTL, 672 .bit_idx = 7, 673 .lock = &clk_lock, 674 .hw.init = &(struct clk_init_data){ 675 .name = "clk81", 676 .ops = &clk_gate_ops, 677 .parent_names = (const char *[]){ "mpeg_clk_div" }, 678 .num_parents = 1, 679 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL), 680 }, 681 }; 682 683 static struct clk_mux gxbb_sar_adc_clk_sel = { 684 .reg = (void *)HHI_SAR_CLK_CNTL, 685 .mask = 0x3, 686 .shift = 9, 687 .lock = &clk_lock, 688 .hw.init = &(struct clk_init_data){ 689 .name = "sar_adc_clk_sel", 690 .ops = &clk_mux_ops, 691 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 692 .parent_names = (const char *[]){ "xtal", "clk81", }, 693 .num_parents = 2, 694 }, 695 }; 696 697 static struct clk_divider gxbb_sar_adc_clk_div = { 698 .reg = (void *)HHI_SAR_CLK_CNTL, 699 .shift = 0, 700 .width = 8, 701 .lock = &clk_lock, 702 .hw.init = &(struct clk_init_data){ 703 .name = "sar_adc_clk_div", 704 .ops = &clk_divider_ops, 705 .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 706 .num_parents = 1, 707 }, 708 }; 709 710 static struct clk_gate gxbb_sar_adc_clk = { 711 .reg = (void *)HHI_SAR_CLK_CNTL, 712 .bit_idx = 8, 713 .lock = &clk_lock, 714 .hw.init = &(struct clk_init_data){ 715 .name = "sar_adc_clk", 716 .ops = &clk_gate_ops, 717 .parent_names = (const char *[]){ "sar_adc_clk_div" }, 718 .num_parents = 1, 719 .flags = CLK_SET_RATE_PARENT, 720 }, 721 }; 722 723 /* 724 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 725 * muxed by a glitch-free switch. 726 */ 727 728 static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7}; 729 static const char *gxbb_mali_0_1_parent_names[] = { 730 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 731 "fclk_div4", "fclk_div3", "fclk_div5" 732 }; 733 734 static struct clk_mux gxbb_mali_0_sel = { 735 .reg = (void *)HHI_MALI_CLK_CNTL, 736 .mask = 0x7, 737 .shift = 9, 738 .table = mux_table_mali_0_1, 739 .lock = &clk_lock, 740 .hw.init = &(struct clk_init_data){ 741 .name = "mali_0_sel", 742 .ops = &clk_mux_ops, 743 /* 744 * bits 10:9 selects from 8 possible parents: 745 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 746 * fclk_div4, fclk_div3, fclk_div5 747 */ 748 .parent_names = gxbb_mali_0_1_parent_names, 749 .num_parents = 8, 750 .flags = CLK_SET_RATE_NO_REPARENT, 751 }, 752 }; 753 754 static struct clk_divider gxbb_mali_0_div = { 755 .reg = (void *)HHI_MALI_CLK_CNTL, 756 .shift = 0, 757 .width = 7, 758 .lock = &clk_lock, 759 .hw.init = &(struct clk_init_data){ 760 .name = "mali_0_div", 761 .ops = &clk_divider_ops, 762 .parent_names = (const char *[]){ "mali_0_sel" }, 763 .num_parents = 1, 764 .flags = CLK_SET_RATE_NO_REPARENT, 765 }, 766 }; 767 768 static struct clk_gate gxbb_mali_0 = { 769 .reg = (void *)HHI_MALI_CLK_CNTL, 770 .bit_idx = 8, 771 .lock = &clk_lock, 772 .hw.init = &(struct clk_init_data){ 773 .name = "mali_0", 774 .ops = &clk_gate_ops, 775 .parent_names = (const char *[]){ "mali_0_div" }, 776 .num_parents = 1, 777 .flags = CLK_SET_RATE_PARENT, 778 }, 779 }; 780 781 static struct clk_mux gxbb_mali_1_sel = { 782 .reg = (void *)HHI_MALI_CLK_CNTL, 783 .mask = 0x7, 784 .shift = 25, 785 .table = mux_table_mali_0_1, 786 .lock = &clk_lock, 787 .hw.init = &(struct clk_init_data){ 788 .name = "mali_1_sel", 789 .ops = &clk_mux_ops, 790 /* 791 * bits 10:9 selects from 8 possible parents: 792 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 793 * fclk_div4, fclk_div3, fclk_div5 794 */ 795 .parent_names = gxbb_mali_0_1_parent_names, 796 .num_parents = 8, 797 .flags = CLK_SET_RATE_NO_REPARENT, 798 }, 799 }; 800 801 static struct clk_divider gxbb_mali_1_div = { 802 .reg = (void *)HHI_MALI_CLK_CNTL, 803 .shift = 16, 804 .width = 7, 805 .lock = &clk_lock, 806 .hw.init = &(struct clk_init_data){ 807 .name = "mali_1_div", 808 .ops = &clk_divider_ops, 809 .parent_names = (const char *[]){ "mali_1_sel" }, 810 .num_parents = 1, 811 .flags = CLK_SET_RATE_NO_REPARENT, 812 }, 813 }; 814 815 static struct clk_gate gxbb_mali_1 = { 816 .reg = (void *)HHI_MALI_CLK_CNTL, 817 .bit_idx = 24, 818 .lock = &clk_lock, 819 .hw.init = &(struct clk_init_data){ 820 .name = "mali_1", 821 .ops = &clk_gate_ops, 822 .parent_names = (const char *[]){ "mali_1_div" }, 823 .num_parents = 1, 824 .flags = CLK_SET_RATE_PARENT, 825 }, 826 }; 827 828 static u32 mux_table_mali[] = {0, 1}; 829 static const char *gxbb_mali_parent_names[] = { 830 "mali_0", "mali_1" 831 }; 832 833 static struct clk_mux gxbb_mali = { 834 .reg = (void *)HHI_MALI_CLK_CNTL, 835 .mask = 1, 836 .shift = 31, 837 .table = mux_table_mali, 838 .lock = &clk_lock, 839 .hw.init = &(struct clk_init_data){ 840 .name = "mali", 841 .ops = &clk_mux_ops, 842 .parent_names = gxbb_mali_parent_names, 843 .num_parents = 2, 844 .flags = CLK_SET_RATE_NO_REPARENT, 845 }, 846 }; 847 848 static struct clk_mux gxbb_cts_amclk_sel = { 849 .reg = (void *) HHI_AUD_CLK_CNTL, 850 .mask = 0x3, 851 .shift = 9, 852 /* Default parent unknown (register reset value: 0) */ 853 .table = (u32[]){ 1, 2, 3 }, 854 .lock = &clk_lock, 855 .hw.init = &(struct clk_init_data){ 856 .name = "cts_amclk_sel", 857 .ops = &clk_mux_ops, 858 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 859 .num_parents = 3, 860 .flags = CLK_SET_RATE_PARENT, 861 }, 862 }; 863 864 static struct meson_clk_audio_divider gxbb_cts_amclk_div = { 865 .div = { 866 .reg_off = HHI_AUD_CLK_CNTL, 867 .shift = 0, 868 .width = 8, 869 }, 870 .lock = &clk_lock, 871 .hw.init = &(struct clk_init_data){ 872 .name = "cts_amclk_div", 873 .ops = &meson_clk_audio_divider_ops, 874 .parent_names = (const char *[]){ "cts_amclk_sel" }, 875 .num_parents = 1, 876 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 877 }, 878 }; 879 880 static struct clk_gate gxbb_cts_amclk = { 881 .reg = (void *) HHI_AUD_CLK_CNTL, 882 .bit_idx = 8, 883 .lock = &clk_lock, 884 .hw.init = &(struct clk_init_data){ 885 .name = "cts_amclk", 886 .ops = &clk_gate_ops, 887 .parent_names = (const char *[]){ "cts_amclk_div" }, 888 .num_parents = 1, 889 .flags = CLK_SET_RATE_PARENT, 890 }, 891 }; 892 893 static struct clk_mux gxbb_cts_mclk_i958_sel = { 894 .reg = (void *)HHI_AUD_CLK_CNTL2, 895 .mask = 0x3, 896 .shift = 25, 897 /* Default parent unknown (register reset value: 0) */ 898 .table = (u32[]){ 1, 2, 3 }, 899 .lock = &clk_lock, 900 .hw.init = &(struct clk_init_data){ 901 .name = "cts_mclk_i958_sel", 902 .ops = &clk_mux_ops, 903 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 904 .num_parents = 3, 905 .flags = CLK_SET_RATE_PARENT, 906 }, 907 }; 908 909 static struct clk_divider gxbb_cts_mclk_i958_div = { 910 .reg = (void *)HHI_AUD_CLK_CNTL2, 911 .shift = 16, 912 .width = 8, 913 .lock = &clk_lock, 914 .hw.init = &(struct clk_init_data){ 915 .name = "cts_mclk_i958_div", 916 .ops = &clk_divider_ops, 917 .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 918 .num_parents = 1, 919 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 920 }, 921 }; 922 923 static struct clk_gate gxbb_cts_mclk_i958 = { 924 .reg = (void *)HHI_AUD_CLK_CNTL2, 925 .bit_idx = 24, 926 .lock = &clk_lock, 927 .hw.init = &(struct clk_init_data){ 928 .name = "cts_mclk_i958", 929 .ops = &clk_gate_ops, 930 .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 931 .num_parents = 1, 932 .flags = CLK_SET_RATE_PARENT, 933 }, 934 }; 935 936 static struct clk_mux gxbb_cts_i958 = { 937 .reg = (void *)HHI_AUD_CLK_CNTL2, 938 .mask = 0x1, 939 .shift = 27, 940 .lock = &clk_lock, 941 .hw.init = &(struct clk_init_data){ 942 .name = "cts_i958", 943 .ops = &clk_mux_ops, 944 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 945 .num_parents = 2, 946 /* 947 *The parent is specific to origin of the audio data. Let the 948 * consumer choose the appropriate parent 949 */ 950 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 951 }, 952 }; 953 954 /* Everything Else (EE) domain gates */ 955 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 956 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 957 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 958 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 959 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 960 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 961 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 962 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10); 963 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 964 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 965 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 966 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 967 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 968 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 969 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 970 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 971 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 972 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 973 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 974 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 975 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 976 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 977 978 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 979 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 980 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 981 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6); 982 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7); 983 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8); 984 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9); 985 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10); 986 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11); 987 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12); 988 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13); 989 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 990 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 991 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 992 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 993 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 994 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 995 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 996 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 997 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 998 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 999 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 1000 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 1001 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 1002 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 1003 1004 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1005 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1006 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 1007 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 1008 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 1009 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 1010 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 1011 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 1012 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 1013 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22); 1014 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 1015 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1016 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 1017 1018 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 1019 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 1020 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 1021 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 1022 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 1023 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 1024 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 1025 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 1026 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 1027 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 1028 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 1029 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 1030 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 1031 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 1032 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 1033 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 1034 1035 /* Always On (AO) domain gates */ 1036 1037 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 1038 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 1039 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 1040 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 1041 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 1042 1043 /* Array of all clocks provided by this provider */ 1044 1045 static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 1046 .hws = { 1047 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1048 [CLKID_CPUCLK] = &gxbb_cpu_clk.hw, 1049 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1050 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1051 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1052 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1053 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1054 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1055 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1056 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 1057 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1058 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1059 [CLKID_CLK81] = &gxbb_clk81.hw, 1060 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1061 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1062 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1063 [CLKID_DDR] = &gxbb_ddr.hw, 1064 [CLKID_DOS] = &gxbb_dos.hw, 1065 [CLKID_ISA] = &gxbb_isa.hw, 1066 [CLKID_PL301] = &gxbb_pl301.hw, 1067 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1068 [CLKID_SPICC] = &gxbb_spicc.hw, 1069 [CLKID_I2C] = &gxbb_i2c.hw, 1070 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1071 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1072 [CLKID_RNG0] = &gxbb_rng0.hw, 1073 [CLKID_UART0] = &gxbb_uart0.hw, 1074 [CLKID_SDHC] = &gxbb_sdhc.hw, 1075 [CLKID_STREAM] = &gxbb_stream.hw, 1076 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1077 [CLKID_SDIO] = &gxbb_sdio.hw, 1078 [CLKID_ABUF] = &gxbb_abuf.hw, 1079 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1080 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1081 [CLKID_SPI] = &gxbb_spi.hw, 1082 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1083 [CLKID_ETH] = &gxbb_eth.hw, 1084 [CLKID_DEMUX] = &gxbb_demux.hw, 1085 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1086 [CLKID_IEC958] = &gxbb_iec958.hw, 1087 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1088 [CLKID_AMCLK] = &gxbb_amclk.hw, 1089 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1090 [CLKID_MIXER] = &gxbb_mixer.hw, 1091 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1092 [CLKID_ADC] = &gxbb_adc.hw, 1093 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1094 [CLKID_AIU] = &gxbb_aiu.hw, 1095 [CLKID_UART1] = &gxbb_uart1.hw, 1096 [CLKID_G2D] = &gxbb_g2d.hw, 1097 [CLKID_USB0] = &gxbb_usb0.hw, 1098 [CLKID_USB1] = &gxbb_usb1.hw, 1099 [CLKID_RESET] = &gxbb_reset.hw, 1100 [CLKID_NAND] = &gxbb_nand.hw, 1101 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1102 [CLKID_USB] = &gxbb_usb.hw, 1103 [CLKID_VDIN1] = &gxbb_vdin1.hw, 1104 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1105 [CLKID_EFUSE] = &gxbb_efuse.hw, 1106 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1107 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1108 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1109 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1110 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1111 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1112 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1113 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1114 [CLKID_DVIN] = &gxbb_dvin.hw, 1115 [CLKID_UART2] = &gxbb_uart2.hw, 1116 [CLKID_SANA] = &gxbb_sana.hw, 1117 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1118 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1119 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1120 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1121 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1122 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1123 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1124 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1125 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1126 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1127 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1128 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1129 [CLKID_ENC480P] = &gxbb_enc480p.hw, 1130 [CLKID_RNG1] = &gxbb_rng1.hw, 1131 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1132 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1133 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1134 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1135 [CLKID_EDP] = &gxbb_edp.hw, 1136 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1137 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1138 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1139 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1140 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 1141 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 1142 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 1143 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 1144 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 1145 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 1146 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1147 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1148 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1149 [CLKID_MALI_0] = &gxbb_mali_0.hw, 1150 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1151 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1152 [CLKID_MALI_1] = &gxbb_mali_1.hw, 1153 [CLKID_MALI] = &gxbb_mali.hw, 1154 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 1155 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 1156 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 1157 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 1158 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 1159 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 1160 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 1161 }, 1162 .num = NR_CLKS, 1163 }; 1164 1165 static struct clk_hw_onecell_data gxl_hw_onecell_data = { 1166 .hws = { 1167 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1168 [CLKID_CPUCLK] = &gxbb_cpu_clk.hw, 1169 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1170 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1171 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1172 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1173 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1174 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1175 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1176 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw, 1177 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1178 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1179 [CLKID_CLK81] = &gxbb_clk81.hw, 1180 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1181 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1182 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1183 [CLKID_DDR] = &gxbb_ddr.hw, 1184 [CLKID_DOS] = &gxbb_dos.hw, 1185 [CLKID_ISA] = &gxbb_isa.hw, 1186 [CLKID_PL301] = &gxbb_pl301.hw, 1187 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1188 [CLKID_SPICC] = &gxbb_spicc.hw, 1189 [CLKID_I2C] = &gxbb_i2c.hw, 1190 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1191 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1192 [CLKID_RNG0] = &gxbb_rng0.hw, 1193 [CLKID_UART0] = &gxbb_uart0.hw, 1194 [CLKID_SDHC] = &gxbb_sdhc.hw, 1195 [CLKID_STREAM] = &gxbb_stream.hw, 1196 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1197 [CLKID_SDIO] = &gxbb_sdio.hw, 1198 [CLKID_ABUF] = &gxbb_abuf.hw, 1199 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1200 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1201 [CLKID_SPI] = &gxbb_spi.hw, 1202 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1203 [CLKID_ETH] = &gxbb_eth.hw, 1204 [CLKID_DEMUX] = &gxbb_demux.hw, 1205 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1206 [CLKID_IEC958] = &gxbb_iec958.hw, 1207 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1208 [CLKID_AMCLK] = &gxbb_amclk.hw, 1209 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1210 [CLKID_MIXER] = &gxbb_mixer.hw, 1211 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1212 [CLKID_ADC] = &gxbb_adc.hw, 1213 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1214 [CLKID_AIU] = &gxbb_aiu.hw, 1215 [CLKID_UART1] = &gxbb_uart1.hw, 1216 [CLKID_G2D] = &gxbb_g2d.hw, 1217 [CLKID_USB0] = &gxbb_usb0.hw, 1218 [CLKID_USB1] = &gxbb_usb1.hw, 1219 [CLKID_RESET] = &gxbb_reset.hw, 1220 [CLKID_NAND] = &gxbb_nand.hw, 1221 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1222 [CLKID_USB] = &gxbb_usb.hw, 1223 [CLKID_VDIN1] = &gxbb_vdin1.hw, 1224 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1225 [CLKID_EFUSE] = &gxbb_efuse.hw, 1226 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1227 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1228 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1229 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1230 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1231 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1232 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1233 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1234 [CLKID_DVIN] = &gxbb_dvin.hw, 1235 [CLKID_UART2] = &gxbb_uart2.hw, 1236 [CLKID_SANA] = &gxbb_sana.hw, 1237 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1238 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1239 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1240 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1241 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1242 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1243 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1244 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1245 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1246 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1247 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1248 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1249 [CLKID_ENC480P] = &gxbb_enc480p.hw, 1250 [CLKID_RNG1] = &gxbb_rng1.hw, 1251 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1252 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1253 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1254 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1255 [CLKID_EDP] = &gxbb_edp.hw, 1256 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1257 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1258 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1259 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1260 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 1261 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 1262 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 1263 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 1264 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 1265 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 1266 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1267 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1268 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1269 [CLKID_MALI_0] = &gxbb_mali_0.hw, 1270 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1271 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1272 [CLKID_MALI_1] = &gxbb_mali_1.hw, 1273 [CLKID_MALI] = &gxbb_mali.hw, 1274 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 1275 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 1276 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 1277 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 1278 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 1279 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 1280 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 1281 }, 1282 .num = NR_CLKS, 1283 }; 1284 1285 /* Convenience tables to populate base addresses in .probe */ 1286 1287 static struct meson_clk_pll *const gxbb_clk_plls[] = { 1288 &gxbb_fixed_pll, 1289 &gxbb_hdmi_pll, 1290 &gxbb_sys_pll, 1291 &gxbb_gp0_pll, 1292 }; 1293 1294 static struct meson_clk_pll *const gxl_clk_plls[] = { 1295 &gxbb_fixed_pll, 1296 &gxbb_hdmi_pll, 1297 &gxbb_sys_pll, 1298 &gxl_gp0_pll, 1299 }; 1300 1301 static struct meson_clk_mpll *const gxbb_clk_mplls[] = { 1302 &gxbb_mpll0, 1303 &gxbb_mpll1, 1304 &gxbb_mpll2, 1305 }; 1306 1307 static struct clk_gate *const gxbb_clk_gates[] = { 1308 &gxbb_clk81, 1309 &gxbb_ddr, 1310 &gxbb_dos, 1311 &gxbb_isa, 1312 &gxbb_pl301, 1313 &gxbb_periphs, 1314 &gxbb_spicc, 1315 &gxbb_i2c, 1316 &gxbb_sar_adc, 1317 &gxbb_smart_card, 1318 &gxbb_rng0, 1319 &gxbb_uart0, 1320 &gxbb_sdhc, 1321 &gxbb_stream, 1322 &gxbb_async_fifo, 1323 &gxbb_sdio, 1324 &gxbb_abuf, 1325 &gxbb_hiu_iface, 1326 &gxbb_assist_misc, 1327 &gxbb_spi, 1328 &gxbb_i2s_spdif, 1329 &gxbb_eth, 1330 &gxbb_demux, 1331 &gxbb_aiu_glue, 1332 &gxbb_iec958, 1333 &gxbb_i2s_out, 1334 &gxbb_amclk, 1335 &gxbb_aififo2, 1336 &gxbb_mixer, 1337 &gxbb_mixer_iface, 1338 &gxbb_adc, 1339 &gxbb_blkmv, 1340 &gxbb_aiu, 1341 &gxbb_uart1, 1342 &gxbb_g2d, 1343 &gxbb_usb0, 1344 &gxbb_usb1, 1345 &gxbb_reset, 1346 &gxbb_nand, 1347 &gxbb_dos_parser, 1348 &gxbb_usb, 1349 &gxbb_vdin1, 1350 &gxbb_ahb_arb0, 1351 &gxbb_efuse, 1352 &gxbb_boot_rom, 1353 &gxbb_ahb_data_bus, 1354 &gxbb_ahb_ctrl_bus, 1355 &gxbb_hdmi_intr_sync, 1356 &gxbb_hdmi_pclk, 1357 &gxbb_usb1_ddr_bridge, 1358 &gxbb_usb0_ddr_bridge, 1359 &gxbb_mmc_pclk, 1360 &gxbb_dvin, 1361 &gxbb_uart2, 1362 &gxbb_sana, 1363 &gxbb_vpu_intr, 1364 &gxbb_sec_ahb_ahb3_bridge, 1365 &gxbb_clk81_a53, 1366 &gxbb_vclk2_venci0, 1367 &gxbb_vclk2_venci1, 1368 &gxbb_vclk2_vencp0, 1369 &gxbb_vclk2_vencp1, 1370 &gxbb_gclk_venci_int0, 1371 &gxbb_gclk_vencp_int, 1372 &gxbb_dac_clk, 1373 &gxbb_aoclk_gate, 1374 &gxbb_iec958_gate, 1375 &gxbb_enc480p, 1376 &gxbb_rng1, 1377 &gxbb_gclk_venci_int1, 1378 &gxbb_vclk2_venclmcc, 1379 &gxbb_vclk2_vencl, 1380 &gxbb_vclk_other, 1381 &gxbb_edp, 1382 &gxbb_ao_media_cpu, 1383 &gxbb_ao_ahb_sram, 1384 &gxbb_ao_ahb_bus, 1385 &gxbb_ao_iface, 1386 &gxbb_ao_i2c, 1387 &gxbb_emmc_a, 1388 &gxbb_emmc_b, 1389 &gxbb_emmc_c, 1390 &gxbb_sar_adc_clk, 1391 &gxbb_mali_0, 1392 &gxbb_mali_1, 1393 &gxbb_cts_amclk, 1394 &gxbb_cts_mclk_i958, 1395 }; 1396 1397 static struct clk_mux *const gxbb_clk_muxes[] = { 1398 &gxbb_mpeg_clk_sel, 1399 &gxbb_sar_adc_clk_sel, 1400 &gxbb_mali_0_sel, 1401 &gxbb_mali_1_sel, 1402 &gxbb_mali, 1403 &gxbb_cts_amclk_sel, 1404 &gxbb_cts_mclk_i958_sel, 1405 &gxbb_cts_i958, 1406 }; 1407 1408 static struct clk_divider *const gxbb_clk_dividers[] = { 1409 &gxbb_mpeg_clk_div, 1410 &gxbb_sar_adc_clk_div, 1411 &gxbb_mali_0_div, 1412 &gxbb_mali_1_div, 1413 &gxbb_cts_mclk_i958_div, 1414 }; 1415 1416 static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { 1417 &gxbb_cts_amclk_div, 1418 }; 1419 1420 struct clkc_data { 1421 struct clk_gate *const *clk_gates; 1422 unsigned int clk_gates_count; 1423 struct meson_clk_mpll *const *clk_mplls; 1424 unsigned int clk_mplls_count; 1425 struct meson_clk_pll *const *clk_plls; 1426 unsigned int clk_plls_count; 1427 struct clk_mux *const *clk_muxes; 1428 unsigned int clk_muxes_count; 1429 struct clk_divider *const *clk_dividers; 1430 unsigned int clk_dividers_count; 1431 struct meson_clk_audio_divider *const *clk_audio_dividers; 1432 unsigned int clk_audio_dividers_count; 1433 struct meson_clk_cpu *cpu_clk; 1434 struct clk_hw_onecell_data *hw_onecell_data; 1435 }; 1436 1437 static const struct clkc_data gxbb_clkc_data = { 1438 .clk_gates = gxbb_clk_gates, 1439 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 1440 .clk_mplls = gxbb_clk_mplls, 1441 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), 1442 .clk_plls = gxbb_clk_plls, 1443 .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), 1444 .clk_muxes = gxbb_clk_muxes, 1445 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), 1446 .clk_dividers = gxbb_clk_dividers, 1447 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), 1448 .clk_audio_dividers = gxbb_audio_dividers, 1449 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), 1450 .cpu_clk = &gxbb_cpu_clk, 1451 .hw_onecell_data = &gxbb_hw_onecell_data, 1452 }; 1453 1454 static const struct clkc_data gxl_clkc_data = { 1455 .clk_gates = gxbb_clk_gates, 1456 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 1457 .clk_mplls = gxbb_clk_mplls, 1458 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), 1459 .clk_plls = gxl_clk_plls, 1460 .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), 1461 .clk_muxes = gxbb_clk_muxes, 1462 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), 1463 .clk_dividers = gxbb_clk_dividers, 1464 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), 1465 .clk_audio_dividers = gxbb_audio_dividers, 1466 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), 1467 .cpu_clk = &gxbb_cpu_clk, 1468 .hw_onecell_data = &gxl_hw_onecell_data, 1469 }; 1470 1471 static const struct of_device_id clkc_match_table[] = { 1472 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 1473 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 1474 {}, 1475 }; 1476 1477 static int gxbb_clkc_probe(struct platform_device *pdev) 1478 { 1479 const struct clkc_data *clkc_data; 1480 void __iomem *clk_base; 1481 int ret, clkid, i; 1482 struct clk_hw *parent_hw; 1483 struct clk *parent_clk; 1484 struct device *dev = &pdev->dev; 1485 1486 clkc_data = of_device_get_match_data(&pdev->dev); 1487 if (!clkc_data) 1488 return -EINVAL; 1489 1490 /* Generic clocks and PLLs */ 1491 clk_base = of_iomap(dev->of_node, 0); 1492 if (!clk_base) { 1493 pr_err("%s: Unable to map clk base\n", __func__); 1494 return -ENXIO; 1495 } 1496 1497 /* Populate base address for PLLs */ 1498 for (i = 0; i < clkc_data->clk_plls_count; i++) 1499 clkc_data->clk_plls[i]->base = clk_base; 1500 1501 /* Populate base address for MPLLs */ 1502 for (i = 0; i < clkc_data->clk_mplls_count; i++) 1503 clkc_data->clk_mplls[i]->base = clk_base; 1504 1505 /* Populate the base address for CPU clk */ 1506 clkc_data->cpu_clk->base = clk_base; 1507 1508 /* Populate base address for gates */ 1509 for (i = 0; i < clkc_data->clk_gates_count; i++) 1510 clkc_data->clk_gates[i]->reg = clk_base + 1511 (u64)clkc_data->clk_gates[i]->reg; 1512 1513 /* Populate base address for muxes */ 1514 for (i = 0; i < clkc_data->clk_muxes_count; i++) 1515 clkc_data->clk_muxes[i]->reg = clk_base + 1516 (u64)clkc_data->clk_muxes[i]->reg; 1517 1518 /* Populate base address for dividers */ 1519 for (i = 0; i < clkc_data->clk_dividers_count; i++) 1520 clkc_data->clk_dividers[i]->reg = clk_base + 1521 (u64)clkc_data->clk_dividers[i]->reg; 1522 1523 /* Populate base address for the audio dividers */ 1524 for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) 1525 clkc_data->clk_audio_dividers[i]->base = clk_base; 1526 1527 /* 1528 * register all clks 1529 */ 1530 for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) { 1531 /* array might be sparse */ 1532 if (!clkc_data->hw_onecell_data->hws[clkid]) 1533 continue; 1534 1535 ret = devm_clk_hw_register(dev, 1536 clkc_data->hw_onecell_data->hws[clkid]); 1537 if (ret) 1538 goto iounmap; 1539 } 1540 1541 /* 1542 * Register CPU clk notifier 1543 * 1544 * FIXME this is wrong for a lot of reasons. First, the muxes should be 1545 * struct clk_hw objects. Second, we shouldn't program the muxes in 1546 * notifier handlers. The tricky programming sequence will be handled 1547 * by the forthcoming coordinated clock rates mechanism once that 1548 * feature is released. 1549 * 1550 * Furthermore, looking up the parent this way is terrible. At some 1551 * point we will stop allocating a default struct clk when registering 1552 * a new clk_hw, and this hack will no longer work. Releasing the ccr 1553 * feature before that time solves the problem :-) 1554 */ 1555 parent_hw = clk_hw_get_parent(&clkc_data->cpu_clk->hw); 1556 parent_clk = parent_hw->clk; 1557 ret = clk_notifier_register(parent_clk, &clkc_data->cpu_clk->clk_nb); 1558 if (ret) { 1559 pr_err("%s: failed to register clock notifier for cpu_clk\n", 1560 __func__); 1561 goto iounmap; 1562 } 1563 1564 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 1565 clkc_data->hw_onecell_data); 1566 1567 iounmap: 1568 iounmap(clk_base); 1569 return ret; 1570 } 1571 1572 static struct platform_driver gxbb_driver = { 1573 .probe = gxbb_clkc_probe, 1574 .driver = { 1575 .name = "gxbb-clkc", 1576 .of_match_table = clkc_match_table, 1577 }, 1578 }; 1579 1580 builtin_platform_driver(gxbb_driver); 1581