xref: /openbmc/linux/drivers/clk/meson/gxbb.c (revision 8795a739)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2016 AmLogic, Inc.
4  * Michael Turquette <mturquette@baylibre.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 
12 #include "gxbb.h"
13 #include "clk-regmap.h"
14 #include "clk-pll.h"
15 #include "clk-mpll.h"
16 #include "meson-eeclk.h"
17 #include "vid-pll-div.h"
18 
19 static DEFINE_SPINLOCK(meson_clk_lock);
20 
21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
22 	PLL_PARAMS(32, 1),
23 	PLL_PARAMS(33, 1),
24 	PLL_PARAMS(34, 1),
25 	PLL_PARAMS(35, 1),
26 	PLL_PARAMS(36, 1),
27 	PLL_PARAMS(37, 1),
28 	PLL_PARAMS(38, 1),
29 	PLL_PARAMS(39, 1),
30 	PLL_PARAMS(40, 1),
31 	PLL_PARAMS(41, 1),
32 	PLL_PARAMS(42, 1),
33 	PLL_PARAMS(43, 1),
34 	PLL_PARAMS(44, 1),
35 	PLL_PARAMS(45, 1),
36 	PLL_PARAMS(46, 1),
37 	PLL_PARAMS(47, 1),
38 	PLL_PARAMS(48, 1),
39 	PLL_PARAMS(49, 1),
40 	PLL_PARAMS(50, 1),
41 	PLL_PARAMS(51, 1),
42 	PLL_PARAMS(52, 1),
43 	PLL_PARAMS(53, 1),
44 	PLL_PARAMS(54, 1),
45 	PLL_PARAMS(55, 1),
46 	PLL_PARAMS(56, 1),
47 	PLL_PARAMS(57, 1),
48 	PLL_PARAMS(58, 1),
49 	PLL_PARAMS(59, 1),
50 	PLL_PARAMS(60, 1),
51 	PLL_PARAMS(61, 1),
52 	PLL_PARAMS(62, 1),
53 	{ /* sentinel */ },
54 };
55 
56 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
57 	PLL_PARAMS(42, 1),
58 	PLL_PARAMS(43, 1),
59 	PLL_PARAMS(44, 1),
60 	PLL_PARAMS(45, 1),
61 	PLL_PARAMS(46, 1),
62 	PLL_PARAMS(47, 1),
63 	PLL_PARAMS(48, 1),
64 	PLL_PARAMS(49, 1),
65 	PLL_PARAMS(50, 1),
66 	PLL_PARAMS(51, 1),
67 	PLL_PARAMS(52, 1),
68 	PLL_PARAMS(53, 1),
69 	PLL_PARAMS(54, 1),
70 	PLL_PARAMS(55, 1),
71 	PLL_PARAMS(56, 1),
72 	PLL_PARAMS(57, 1),
73 	PLL_PARAMS(58, 1),
74 	PLL_PARAMS(59, 1),
75 	PLL_PARAMS(60, 1),
76 	PLL_PARAMS(61, 1),
77 	PLL_PARAMS(62, 1),
78 	PLL_PARAMS(63, 1),
79 	PLL_PARAMS(64, 1),
80 	PLL_PARAMS(65, 1),
81 	PLL_PARAMS(66, 1),
82 	{ /* sentinel */ },
83 };
84 
85 static struct clk_regmap gxbb_fixed_pll_dco = {
86 	.data = &(struct meson_clk_pll_data){
87 		.en = {
88 			.reg_off = HHI_MPLL_CNTL,
89 			.shift   = 30,
90 			.width   = 1,
91 		},
92 		.m = {
93 			.reg_off = HHI_MPLL_CNTL,
94 			.shift   = 0,
95 			.width   = 9,
96 		},
97 		.n = {
98 			.reg_off = HHI_MPLL_CNTL,
99 			.shift   = 9,
100 			.width   = 5,
101 		},
102 		.frac = {
103 			.reg_off = HHI_MPLL_CNTL2,
104 			.shift   = 0,
105 			.width   = 12,
106 		},
107 		.l = {
108 			.reg_off = HHI_MPLL_CNTL,
109 			.shift   = 31,
110 			.width   = 1,
111 		},
112 		.rst = {
113 			.reg_off = HHI_MPLL_CNTL,
114 			.shift   = 29,
115 			.width   = 1,
116 		},
117 	},
118 	.hw.init = &(struct clk_init_data){
119 		.name = "fixed_pll_dco",
120 		.ops = &meson_clk_pll_ro_ops,
121 		.parent_data = &(const struct clk_parent_data) {
122 			.fw_name = "xtal",
123 		},
124 		.num_parents = 1,
125 	},
126 };
127 
128 static struct clk_regmap gxbb_fixed_pll = {
129 	.data = &(struct clk_regmap_div_data){
130 		.offset = HHI_MPLL_CNTL,
131 		.shift = 16,
132 		.width = 2,
133 		.flags = CLK_DIVIDER_POWER_OF_TWO,
134 	},
135 	.hw.init = &(struct clk_init_data){
136 		.name = "fixed_pll",
137 		.ops = &clk_regmap_divider_ro_ops,
138 		.parent_hws = (const struct clk_hw *[]) {
139 			&gxbb_fixed_pll_dco.hw
140 		},
141 		.num_parents = 1,
142 		/*
143 		 * This clock won't ever change at runtime so
144 		 * CLK_SET_RATE_PARENT is not required
145 		 */
146 	},
147 };
148 
149 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
150 	.mult = 2,
151 	.div = 1,
152 	.hw.init = &(struct clk_init_data){
153 		.name = "hdmi_pll_pre_mult",
154 		.ops = &clk_fixed_factor_ops,
155 		.parent_data = &(const struct clk_parent_data) {
156 			.fw_name = "xtal",
157 		},
158 		.num_parents = 1,
159 	},
160 };
161 
162 static struct clk_regmap gxbb_hdmi_pll_dco = {
163 	.data = &(struct meson_clk_pll_data){
164 		.en = {
165 			.reg_off = HHI_HDMI_PLL_CNTL,
166 			.shift   = 30,
167 			.width   = 1,
168 		},
169 		.m = {
170 			.reg_off = HHI_HDMI_PLL_CNTL,
171 			.shift   = 0,
172 			.width   = 9,
173 		},
174 		.n = {
175 			.reg_off = HHI_HDMI_PLL_CNTL,
176 			.shift   = 9,
177 			.width   = 5,
178 		},
179 		.frac = {
180 			.reg_off = HHI_HDMI_PLL_CNTL2,
181 			.shift   = 0,
182 			.width   = 12,
183 		},
184 		.l = {
185 			.reg_off = HHI_HDMI_PLL_CNTL,
186 			.shift   = 31,
187 			.width   = 1,
188 		},
189 		.rst = {
190 			.reg_off = HHI_HDMI_PLL_CNTL,
191 			.shift   = 28,
192 			.width   = 1,
193 		},
194 	},
195 	.hw.init = &(struct clk_init_data){
196 		.name = "hdmi_pll_dco",
197 		.ops = &meson_clk_pll_ro_ops,
198 		.parent_hws = (const struct clk_hw *[]) {
199 			&gxbb_hdmi_pll_pre_mult.hw
200 		},
201 		.num_parents = 1,
202 		/*
203 		 * Display directly handle hdmi pll registers ATM, we need
204 		 * NOCACHE to keep our view of the clock as accurate as possible
205 		 */
206 		.flags = CLK_GET_RATE_NOCACHE,
207 	},
208 };
209 
210 static struct clk_regmap gxl_hdmi_pll_dco = {
211 	.data = &(struct meson_clk_pll_data){
212 		.en = {
213 			.reg_off = HHI_HDMI_PLL_CNTL,
214 			.shift   = 30,
215 			.width   = 1,
216 		},
217 		.m = {
218 			.reg_off = HHI_HDMI_PLL_CNTL,
219 			.shift   = 0,
220 			.width   = 9,
221 		},
222 		.n = {
223 			.reg_off = HHI_HDMI_PLL_CNTL,
224 			.shift   = 9,
225 			.width   = 5,
226 		},
227 		/*
228 		 * On gxl, there is a register shift due to
229 		 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
230 		 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
231 		 * instead which is defined at the same offset.
232 		 */
233 		.frac = {
234 			.reg_off = HHI_HDMI_PLL_CNTL2,
235 			.shift   = 0,
236 			.width   = 10,
237 		},
238 		.l = {
239 			.reg_off = HHI_HDMI_PLL_CNTL,
240 			.shift   = 31,
241 			.width   = 1,
242 		},
243 		.rst = {
244 			.reg_off = HHI_HDMI_PLL_CNTL,
245 			.shift   = 28,
246 			.width   = 1,
247 		},
248 	},
249 	.hw.init = &(struct clk_init_data){
250 		.name = "hdmi_pll_dco",
251 		.ops = &meson_clk_pll_ro_ops,
252 		.parent_data = &(const struct clk_parent_data) {
253 			.fw_name = "xtal",
254 		},
255 		.num_parents = 1,
256 		/*
257 		 * Display directly handle hdmi pll registers ATM, we need
258 		 * NOCACHE to keep our view of the clock as accurate as possible
259 		 */
260 		.flags = CLK_GET_RATE_NOCACHE,
261 	},
262 };
263 
264 static struct clk_regmap gxbb_hdmi_pll_od = {
265 	.data = &(struct clk_regmap_div_data){
266 		.offset = HHI_HDMI_PLL_CNTL2,
267 		.shift = 16,
268 		.width = 2,
269 		.flags = CLK_DIVIDER_POWER_OF_TWO,
270 	},
271 	.hw.init = &(struct clk_init_data){
272 		.name = "hdmi_pll_od",
273 		.ops = &clk_regmap_divider_ro_ops,
274 		.parent_hws = (const struct clk_hw *[]) {
275 			&gxbb_hdmi_pll_dco.hw
276 		},
277 		.num_parents = 1,
278 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
279 	},
280 };
281 
282 static struct clk_regmap gxbb_hdmi_pll_od2 = {
283 	.data = &(struct clk_regmap_div_data){
284 		.offset = HHI_HDMI_PLL_CNTL2,
285 		.shift = 22,
286 		.width = 2,
287 		.flags = CLK_DIVIDER_POWER_OF_TWO,
288 	},
289 	.hw.init = &(struct clk_init_data){
290 		.name = "hdmi_pll_od2",
291 		.ops = &clk_regmap_divider_ro_ops,
292 		.parent_hws = (const struct clk_hw *[]) {
293 			&gxbb_hdmi_pll_od.hw
294 		},
295 		.num_parents = 1,
296 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
297 	},
298 };
299 
300 static struct clk_regmap gxbb_hdmi_pll = {
301 	.data = &(struct clk_regmap_div_data){
302 		.offset = HHI_HDMI_PLL_CNTL2,
303 		.shift = 18,
304 		.width = 2,
305 		.flags = CLK_DIVIDER_POWER_OF_TWO,
306 	},
307 	.hw.init = &(struct clk_init_data){
308 		.name = "hdmi_pll",
309 		.ops = &clk_regmap_divider_ro_ops,
310 		.parent_hws = (const struct clk_hw *[]) {
311 			&gxbb_hdmi_pll_od2.hw
312 		},
313 		.num_parents = 1,
314 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
315 	},
316 };
317 
318 static struct clk_regmap gxl_hdmi_pll_od = {
319 	.data = &(struct clk_regmap_div_data){
320 		.offset = HHI_HDMI_PLL_CNTL + 8,
321 		.shift = 21,
322 		.width = 2,
323 		.flags = CLK_DIVIDER_POWER_OF_TWO,
324 	},
325 	.hw.init = &(struct clk_init_data){
326 		.name = "hdmi_pll_od",
327 		.ops = &clk_regmap_divider_ro_ops,
328 		.parent_hws = (const struct clk_hw *[]) {
329 			&gxl_hdmi_pll_dco.hw
330 		},
331 		.num_parents = 1,
332 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
333 	},
334 };
335 
336 static struct clk_regmap gxl_hdmi_pll_od2 = {
337 	.data = &(struct clk_regmap_div_data){
338 		.offset = HHI_HDMI_PLL_CNTL + 8,
339 		.shift = 23,
340 		.width = 2,
341 		.flags = CLK_DIVIDER_POWER_OF_TWO,
342 	},
343 	.hw.init = &(struct clk_init_data){
344 		.name = "hdmi_pll_od2",
345 		.ops = &clk_regmap_divider_ro_ops,
346 		.parent_hws = (const struct clk_hw *[]) {
347 			&gxl_hdmi_pll_od.hw
348 		},
349 		.num_parents = 1,
350 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
351 	},
352 };
353 
354 static struct clk_regmap gxl_hdmi_pll = {
355 	.data = &(struct clk_regmap_div_data){
356 		.offset = HHI_HDMI_PLL_CNTL + 8,
357 		.shift = 19,
358 		.width = 2,
359 		.flags = CLK_DIVIDER_POWER_OF_TWO,
360 	},
361 	.hw.init = &(struct clk_init_data){
362 		.name = "hdmi_pll",
363 		.ops = &clk_regmap_divider_ro_ops,
364 		.parent_hws = (const struct clk_hw *[]) {
365 			&gxl_hdmi_pll_od2.hw
366 		},
367 		.num_parents = 1,
368 		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
369 	},
370 };
371 
372 static struct clk_regmap gxbb_sys_pll_dco = {
373 	.data = &(struct meson_clk_pll_data){
374 		.en = {
375 			.reg_off = HHI_SYS_PLL_CNTL,
376 			.shift   = 30,
377 			.width   = 1,
378 		},
379 		.m = {
380 			.reg_off = HHI_SYS_PLL_CNTL,
381 			.shift   = 0,
382 			.width   = 9,
383 		},
384 		.n = {
385 			.reg_off = HHI_SYS_PLL_CNTL,
386 			.shift   = 9,
387 			.width   = 5,
388 		},
389 		.l = {
390 			.reg_off = HHI_SYS_PLL_CNTL,
391 			.shift   = 31,
392 			.width   = 1,
393 		},
394 		.rst = {
395 			.reg_off = HHI_SYS_PLL_CNTL,
396 			.shift   = 29,
397 			.width   = 1,
398 		},
399 	},
400 	.hw.init = &(struct clk_init_data){
401 		.name = "sys_pll_dco",
402 		.ops = &meson_clk_pll_ro_ops,
403 		.parent_data = &(const struct clk_parent_data) {
404 			.fw_name = "xtal",
405 		},
406 		.num_parents = 1,
407 	},
408 };
409 
410 static struct clk_regmap gxbb_sys_pll = {
411 	.data = &(struct clk_regmap_div_data){
412 		.offset = HHI_SYS_PLL_CNTL,
413 		.shift = 10,
414 		.width = 2,
415 		.flags = CLK_DIVIDER_POWER_OF_TWO,
416 	},
417 	.hw.init = &(struct clk_init_data){
418 		.name = "sys_pll",
419 		.ops = &clk_regmap_divider_ro_ops,
420 		.parent_hws = (const struct clk_hw *[]) {
421 			&gxbb_sys_pll_dco.hw
422 		},
423 		.num_parents = 1,
424 		.flags = CLK_SET_RATE_PARENT,
425 	},
426 };
427 
428 static const struct reg_sequence gxbb_gp0_init_regs[] = {
429 	{ .reg = HHI_GP0_PLL_CNTL2,	.def = 0x69c80000 },
430 	{ .reg = HHI_GP0_PLL_CNTL3,	.def = 0x0a5590c4 },
431 	{ .reg = HHI_GP0_PLL_CNTL4,	.def = 0x0000500d },
432 };
433 
434 static struct clk_regmap gxbb_gp0_pll_dco = {
435 	.data = &(struct meson_clk_pll_data){
436 		.en = {
437 			.reg_off = HHI_GP0_PLL_CNTL,
438 			.shift   = 30,
439 			.width   = 1,
440 		},
441 		.m = {
442 			.reg_off = HHI_GP0_PLL_CNTL,
443 			.shift   = 0,
444 			.width   = 9,
445 		},
446 		.n = {
447 			.reg_off = HHI_GP0_PLL_CNTL,
448 			.shift   = 9,
449 			.width   = 5,
450 		},
451 		.l = {
452 			.reg_off = HHI_GP0_PLL_CNTL,
453 			.shift   = 31,
454 			.width   = 1,
455 		},
456 		.rst = {
457 			.reg_off = HHI_GP0_PLL_CNTL,
458 			.shift   = 29,
459 			.width   = 1,
460 		},
461 		.table = gxbb_gp0_pll_params_table,
462 		.init_regs = gxbb_gp0_init_regs,
463 		.init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
464 	},
465 	.hw.init = &(struct clk_init_data){
466 		.name = "gp0_pll_dco",
467 		.ops = &meson_clk_pll_ops,
468 		.parent_data = &(const struct clk_parent_data) {
469 			.fw_name = "xtal",
470 		},
471 		.num_parents = 1,
472 	},
473 };
474 
475 static const struct reg_sequence gxl_gp0_init_regs[] = {
476 	{ .reg = HHI_GP0_PLL_CNTL1,	.def = 0xc084b000 },
477 	{ .reg = HHI_GP0_PLL_CNTL2,	.def = 0xb75020be },
478 	{ .reg = HHI_GP0_PLL_CNTL3,	.def = 0x0a59a288 },
479 	{ .reg = HHI_GP0_PLL_CNTL4,	.def = 0xc000004d },
480 	{ .reg = HHI_GP0_PLL_CNTL5,	.def = 0x00078000 },
481 };
482 
483 static struct clk_regmap gxl_gp0_pll_dco = {
484 	.data = &(struct meson_clk_pll_data){
485 		.en = {
486 			.reg_off = HHI_GP0_PLL_CNTL,
487 			.shift   = 30,
488 			.width   = 1,
489 		},
490 		.m = {
491 			.reg_off = HHI_GP0_PLL_CNTL,
492 			.shift   = 0,
493 			.width   = 9,
494 		},
495 		.n = {
496 			.reg_off = HHI_GP0_PLL_CNTL,
497 			.shift   = 9,
498 			.width   = 5,
499 		},
500 		.frac = {
501 			.reg_off = HHI_GP0_PLL_CNTL1,
502 			.shift   = 0,
503 			.width   = 10,
504 		},
505 		.l = {
506 			.reg_off = HHI_GP0_PLL_CNTL,
507 			.shift   = 31,
508 			.width   = 1,
509 		},
510 		.rst = {
511 			.reg_off = HHI_GP0_PLL_CNTL,
512 			.shift   = 29,
513 			.width   = 1,
514 		},
515 		.table = gxl_gp0_pll_params_table,
516 		.init_regs = gxl_gp0_init_regs,
517 		.init_count = ARRAY_SIZE(gxl_gp0_init_regs),
518 	},
519 	.hw.init = &(struct clk_init_data){
520 		.name = "gp0_pll_dco",
521 		.ops = &meson_clk_pll_ops,
522 		.parent_data = &(const struct clk_parent_data) {
523 			.fw_name = "xtal",
524 		},
525 		.num_parents = 1,
526 	},
527 };
528 
529 static struct clk_regmap gxbb_gp0_pll = {
530 	.data = &(struct clk_regmap_div_data){
531 		.offset = HHI_GP0_PLL_CNTL,
532 		.shift = 16,
533 		.width = 2,
534 		.flags = CLK_DIVIDER_POWER_OF_TWO,
535 	},
536 	.hw.init = &(struct clk_init_data){
537 		.name = "gp0_pll",
538 		.ops = &clk_regmap_divider_ops,
539 		.parent_data = &(const struct clk_parent_data) {
540 			/*
541 			 * Note:
542 			 * GXL and GXBB have different gp0_pll_dco (with
543 			 * different struct clk_hw). We fallback to the global
544 			 * naming string mechanism so gp0_pll picks up the
545 			 * appropriate one.
546 			 */
547 			.name = "gp0_pll_dco",
548 			.index = -1,
549 		},
550 		.num_parents = 1,
551 		.flags = CLK_SET_RATE_PARENT,
552 	},
553 };
554 
555 static struct clk_fixed_factor gxbb_fclk_div2_div = {
556 	.mult = 1,
557 	.div = 2,
558 	.hw.init = &(struct clk_init_data){
559 		.name = "fclk_div2_div",
560 		.ops = &clk_fixed_factor_ops,
561 		.parent_hws = (const struct clk_hw *[]) {
562 			&gxbb_fixed_pll.hw
563 		},
564 		.num_parents = 1,
565 	},
566 };
567 
568 static struct clk_regmap gxbb_fclk_div2 = {
569 	.data = &(struct clk_regmap_gate_data){
570 		.offset = HHI_MPLL_CNTL6,
571 		.bit_idx = 27,
572 	},
573 	.hw.init = &(struct clk_init_data){
574 		.name = "fclk_div2",
575 		.ops = &clk_regmap_gate_ops,
576 		.parent_hws = (const struct clk_hw *[]) {
577 			&gxbb_fclk_div2_div.hw
578 		},
579 		.num_parents = 1,
580 		.flags = CLK_IS_CRITICAL,
581 	},
582 };
583 
584 static struct clk_fixed_factor gxbb_fclk_div3_div = {
585 	.mult = 1,
586 	.div = 3,
587 	.hw.init = &(struct clk_init_data){
588 		.name = "fclk_div3_div",
589 		.ops = &clk_fixed_factor_ops,
590 		.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
591 		.num_parents = 1,
592 	},
593 };
594 
595 static struct clk_regmap gxbb_fclk_div3 = {
596 	.data = &(struct clk_regmap_gate_data){
597 		.offset = HHI_MPLL_CNTL6,
598 		.bit_idx = 28,
599 	},
600 	.hw.init = &(struct clk_init_data){
601 		.name = "fclk_div3",
602 		.ops = &clk_regmap_gate_ops,
603 		.parent_hws = (const struct clk_hw *[]) {
604 			&gxbb_fclk_div3_div.hw
605 		},
606 		.num_parents = 1,
607 		/*
608 		 * FIXME:
609 		 * This clock, as fdiv2, is used by the SCPI FW and is required
610 		 * by the platform to operate correctly.
611 		 * Until the following condition are met, we need this clock to
612 		 * be marked as critical:
613 		 * a) The SCPI generic driver claims and enable all the clocks
614 		 *    it needs
615 		 * b) CCF has a clock hand-off mechanism to make the sure the
616 		 *    clock stays on until the proper driver comes along
617 		 */
618 		.flags = CLK_IS_CRITICAL,
619 	},
620 };
621 
622 static struct clk_fixed_factor gxbb_fclk_div4_div = {
623 	.mult = 1,
624 	.div = 4,
625 	.hw.init = &(struct clk_init_data){
626 		.name = "fclk_div4_div",
627 		.ops = &clk_fixed_factor_ops,
628 		.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
629 		.num_parents = 1,
630 	},
631 };
632 
633 static struct clk_regmap gxbb_fclk_div4 = {
634 	.data = &(struct clk_regmap_gate_data){
635 		.offset = HHI_MPLL_CNTL6,
636 		.bit_idx = 29,
637 	},
638 	.hw.init = &(struct clk_init_data){
639 		.name = "fclk_div4",
640 		.ops = &clk_regmap_gate_ops,
641 		.parent_hws = (const struct clk_hw *[]) {
642 			&gxbb_fclk_div4_div.hw
643 		},
644 		.num_parents = 1,
645 	},
646 };
647 
648 static struct clk_fixed_factor gxbb_fclk_div5_div = {
649 	.mult = 1,
650 	.div = 5,
651 	.hw.init = &(struct clk_init_data){
652 		.name = "fclk_div5_div",
653 		.ops = &clk_fixed_factor_ops,
654 		.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
655 		.num_parents = 1,
656 	},
657 };
658 
659 static struct clk_regmap gxbb_fclk_div5 = {
660 	.data = &(struct clk_regmap_gate_data){
661 		.offset = HHI_MPLL_CNTL6,
662 		.bit_idx = 30,
663 	},
664 	.hw.init = &(struct clk_init_data){
665 		.name = "fclk_div5",
666 		.ops = &clk_regmap_gate_ops,
667 		.parent_hws = (const struct clk_hw *[]) {
668 			&gxbb_fclk_div5_div.hw
669 		},
670 		.num_parents = 1,
671 	},
672 };
673 
674 static struct clk_fixed_factor gxbb_fclk_div7_div = {
675 	.mult = 1,
676 	.div = 7,
677 	.hw.init = &(struct clk_init_data){
678 		.name = "fclk_div7_div",
679 		.ops = &clk_fixed_factor_ops,
680 		.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
681 		.num_parents = 1,
682 	},
683 };
684 
685 static struct clk_regmap gxbb_fclk_div7 = {
686 	.data = &(struct clk_regmap_gate_data){
687 		.offset = HHI_MPLL_CNTL6,
688 		.bit_idx = 31,
689 	},
690 	.hw.init = &(struct clk_init_data){
691 		.name = "fclk_div7",
692 		.ops = &clk_regmap_gate_ops,
693 		.parent_hws = (const struct clk_hw *[]) {
694 			&gxbb_fclk_div7_div.hw
695 		},
696 		.num_parents = 1,
697 	},
698 };
699 
700 static struct clk_regmap gxbb_mpll_prediv = {
701 	.data = &(struct clk_regmap_div_data){
702 		.offset = HHI_MPLL_CNTL5,
703 		.shift = 12,
704 		.width = 1,
705 	},
706 	.hw.init = &(struct clk_init_data){
707 		.name = "mpll_prediv",
708 		.ops = &clk_regmap_divider_ro_ops,
709 		.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
710 		.num_parents = 1,
711 	},
712 };
713 
714 static struct clk_regmap gxbb_mpll0_div = {
715 	.data = &(struct meson_clk_mpll_data){
716 		.sdm = {
717 			.reg_off = HHI_MPLL_CNTL7,
718 			.shift   = 0,
719 			.width   = 14,
720 		},
721 		.sdm_en = {
722 			.reg_off = HHI_MPLL_CNTL7,
723 			.shift   = 15,
724 			.width	 = 1,
725 		},
726 		.n2 = {
727 			.reg_off = HHI_MPLL_CNTL7,
728 			.shift   = 16,
729 			.width   = 9,
730 		},
731 		.lock = &meson_clk_lock,
732 	},
733 	.hw.init = &(struct clk_init_data){
734 		.name = "mpll0_div",
735 		.ops = &meson_clk_mpll_ops,
736 		.parent_hws = (const struct clk_hw *[]) {
737 			&gxbb_mpll_prediv.hw
738 		},
739 		.num_parents = 1,
740 	},
741 };
742 
743 static struct clk_regmap gxbb_mpll0 = {
744 	.data = &(struct clk_regmap_gate_data){
745 		.offset = HHI_MPLL_CNTL7,
746 		.bit_idx = 14,
747 	},
748 	.hw.init = &(struct clk_init_data){
749 		.name = "mpll0",
750 		.ops = &clk_regmap_gate_ops,
751 		.parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },
752 		.num_parents = 1,
753 		.flags = CLK_SET_RATE_PARENT,
754 	},
755 };
756 
757 static struct clk_regmap gxbb_mpll1_div = {
758 	.data = &(struct meson_clk_mpll_data){
759 		.sdm = {
760 			.reg_off = HHI_MPLL_CNTL8,
761 			.shift   = 0,
762 			.width   = 14,
763 		},
764 		.sdm_en = {
765 			.reg_off = HHI_MPLL_CNTL8,
766 			.shift   = 15,
767 			.width	 = 1,
768 		},
769 		.n2 = {
770 			.reg_off = HHI_MPLL_CNTL8,
771 			.shift   = 16,
772 			.width   = 9,
773 		},
774 		.lock = &meson_clk_lock,
775 	},
776 	.hw.init = &(struct clk_init_data){
777 		.name = "mpll1_div",
778 		.ops = &meson_clk_mpll_ops,
779 		.parent_hws = (const struct clk_hw *[]) {
780 			&gxbb_mpll_prediv.hw
781 		},
782 		.num_parents = 1,
783 	},
784 };
785 
786 static struct clk_regmap gxbb_mpll1 = {
787 	.data = &(struct clk_regmap_gate_data){
788 		.offset = HHI_MPLL_CNTL8,
789 		.bit_idx = 14,
790 	},
791 	.hw.init = &(struct clk_init_data){
792 		.name = "mpll1",
793 		.ops = &clk_regmap_gate_ops,
794 		.parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
795 		.num_parents = 1,
796 		.flags = CLK_SET_RATE_PARENT,
797 	},
798 };
799 
800 static struct clk_regmap gxbb_mpll2_div = {
801 	.data = &(struct meson_clk_mpll_data){
802 		.sdm = {
803 			.reg_off = HHI_MPLL_CNTL9,
804 			.shift   = 0,
805 			.width   = 14,
806 		},
807 		.sdm_en = {
808 			.reg_off = HHI_MPLL_CNTL9,
809 			.shift   = 15,
810 			.width	 = 1,
811 		},
812 		.n2 = {
813 			.reg_off = HHI_MPLL_CNTL9,
814 			.shift   = 16,
815 			.width   = 9,
816 		},
817 		.lock = &meson_clk_lock,
818 	},
819 	.hw.init = &(struct clk_init_data){
820 		.name = "mpll2_div",
821 		.ops = &meson_clk_mpll_ops,
822 		.parent_hws = (const struct clk_hw *[]) {
823 			&gxbb_mpll_prediv.hw
824 		},
825 		.num_parents = 1,
826 	},
827 };
828 
829 static struct clk_regmap gxbb_mpll2 = {
830 	.data = &(struct clk_regmap_gate_data){
831 		.offset = HHI_MPLL_CNTL9,
832 		.bit_idx = 14,
833 	},
834 	.hw.init = &(struct clk_init_data){
835 		.name = "mpll2",
836 		.ops = &clk_regmap_gate_ops,
837 		.parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
838 		.num_parents = 1,
839 		.flags = CLK_SET_RATE_PARENT,
840 	},
841 };
842 
843 static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };
844 static const struct clk_parent_data clk81_parent_data[] = {
845 	{ .fw_name = "xtal", },
846 	{ .hw = &gxbb_fclk_div7.hw },
847 	{ .hw = &gxbb_mpll1.hw },
848 	{ .hw = &gxbb_mpll2.hw },
849 	{ .hw = &gxbb_fclk_div4.hw },
850 	{ .hw = &gxbb_fclk_div3.hw },
851 	{ .hw = &gxbb_fclk_div5.hw },
852 };
853 
854 static struct clk_regmap gxbb_mpeg_clk_sel = {
855 	.data = &(struct clk_regmap_mux_data){
856 		.offset = HHI_MPEG_CLK_CNTL,
857 		.mask = 0x7,
858 		.shift = 12,
859 		.table = mux_table_clk81,
860 	},
861 	.hw.init = &(struct clk_init_data){
862 		.name = "mpeg_clk_sel",
863 		.ops = &clk_regmap_mux_ro_ops,
864 		/*
865 		 * bits 14:12 selects from 8 possible parents:
866 		 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
867 		 * fclk_div4, fclk_div3, fclk_div5
868 		 */
869 		.parent_data = clk81_parent_data,
870 		.num_parents = ARRAY_SIZE(clk81_parent_data),
871 	},
872 };
873 
874 static struct clk_regmap gxbb_mpeg_clk_div = {
875 	.data = &(struct clk_regmap_div_data){
876 		.offset = HHI_MPEG_CLK_CNTL,
877 		.shift = 0,
878 		.width = 7,
879 	},
880 	.hw.init = &(struct clk_init_data){
881 		.name = "mpeg_clk_div",
882 		.ops = &clk_regmap_divider_ro_ops,
883 		.parent_hws = (const struct clk_hw *[]) {
884 			&gxbb_mpeg_clk_sel.hw
885 		},
886 		.num_parents = 1,
887 	},
888 };
889 
890 /* the mother of dragons gates */
891 static struct clk_regmap gxbb_clk81 = {
892 	.data = &(struct clk_regmap_gate_data){
893 		.offset = HHI_MPEG_CLK_CNTL,
894 		.bit_idx = 7,
895 	},
896 	.hw.init = &(struct clk_init_data){
897 		.name = "clk81",
898 		.ops = &clk_regmap_gate_ops,
899 		.parent_hws = (const struct clk_hw *[]) {
900 			&gxbb_mpeg_clk_div.hw
901 		},
902 		.num_parents = 1,
903 		.flags = CLK_IS_CRITICAL,
904 	},
905 };
906 
907 static struct clk_regmap gxbb_sar_adc_clk_sel = {
908 	.data = &(struct clk_regmap_mux_data){
909 		.offset = HHI_SAR_CLK_CNTL,
910 		.mask = 0x3,
911 		.shift = 9,
912 	},
913 	.hw.init = &(struct clk_init_data){
914 		.name = "sar_adc_clk_sel",
915 		.ops = &clk_regmap_mux_ops,
916 		/* NOTE: The datasheet doesn't list the parents for bit 10 */
917 		.parent_data = (const struct clk_parent_data []) {
918 			{ .fw_name = "xtal", },
919 			{ .hw = &gxbb_clk81.hw },
920 		},
921 		.num_parents = 2,
922 	},
923 };
924 
925 static struct clk_regmap gxbb_sar_adc_clk_div = {
926 	.data = &(struct clk_regmap_div_data){
927 		.offset = HHI_SAR_CLK_CNTL,
928 		.shift = 0,
929 		.width = 8,
930 	},
931 	.hw.init = &(struct clk_init_data){
932 		.name = "sar_adc_clk_div",
933 		.ops = &clk_regmap_divider_ops,
934 		.parent_hws = (const struct clk_hw *[]) {
935 			&gxbb_sar_adc_clk_sel.hw
936 		},
937 		.num_parents = 1,
938 	},
939 };
940 
941 static struct clk_regmap gxbb_sar_adc_clk = {
942 	.data = &(struct clk_regmap_gate_data){
943 		.offset = HHI_SAR_CLK_CNTL,
944 		.bit_idx = 8,
945 	},
946 	.hw.init = &(struct clk_init_data){
947 		.name = "sar_adc_clk",
948 		.ops = &clk_regmap_gate_ops,
949 		.parent_hws = (const struct clk_hw *[]) {
950 			&gxbb_sar_adc_clk_div.hw
951 		},
952 		.num_parents = 1,
953 		.flags = CLK_SET_RATE_PARENT,
954 	},
955 };
956 
957 /*
958  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
959  * muxed by a glitch-free switch.
960  */
961 
962 static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
963 	{ .fw_name = "xtal", },
964 	{ .hw = &gxbb_gp0_pll.hw },
965 	{ .hw = &gxbb_mpll2.hw },
966 	{ .hw = &gxbb_mpll1.hw },
967 	{ .hw = &gxbb_fclk_div7.hw },
968 	{ .hw = &gxbb_fclk_div4.hw },
969 	{ .hw = &gxbb_fclk_div3.hw },
970 	{ .hw = &gxbb_fclk_div5.hw },
971 };
972 
973 static struct clk_regmap gxbb_mali_0_sel = {
974 	.data = &(struct clk_regmap_mux_data){
975 		.offset = HHI_MALI_CLK_CNTL,
976 		.mask = 0x7,
977 		.shift = 9,
978 	},
979 	.hw.init = &(struct clk_init_data){
980 		.name = "mali_0_sel",
981 		.ops = &clk_regmap_mux_ops,
982 		/*
983 		 * bits 10:9 selects from 8 possible parents:
984 		 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
985 		 * fclk_div4, fclk_div3, fclk_div5
986 		 */
987 		.parent_data = gxbb_mali_0_1_parent_data,
988 		.num_parents = 8,
989 		.flags = CLK_SET_RATE_NO_REPARENT,
990 	},
991 };
992 
993 static struct clk_regmap gxbb_mali_0_div = {
994 	.data = &(struct clk_regmap_div_data){
995 		.offset = HHI_MALI_CLK_CNTL,
996 		.shift = 0,
997 		.width = 7,
998 	},
999 	.hw.init = &(struct clk_init_data){
1000 		.name = "mali_0_div",
1001 		.ops = &clk_regmap_divider_ops,
1002 		.parent_hws = (const struct clk_hw *[]) {
1003 			&gxbb_mali_0_sel.hw
1004 		},
1005 		.num_parents = 1,
1006 		.flags = CLK_SET_RATE_NO_REPARENT,
1007 	},
1008 };
1009 
1010 static struct clk_regmap gxbb_mali_0 = {
1011 	.data = &(struct clk_regmap_gate_data){
1012 		.offset = HHI_MALI_CLK_CNTL,
1013 		.bit_idx = 8,
1014 	},
1015 	.hw.init = &(struct clk_init_data){
1016 		.name = "mali_0",
1017 		.ops = &clk_regmap_gate_ops,
1018 		.parent_hws = (const struct clk_hw *[]) {
1019 			&gxbb_mali_0_div.hw
1020 		},
1021 		.num_parents = 1,
1022 		.flags = CLK_SET_RATE_PARENT,
1023 	},
1024 };
1025 
1026 static struct clk_regmap gxbb_mali_1_sel = {
1027 	.data = &(struct clk_regmap_mux_data){
1028 		.offset = HHI_MALI_CLK_CNTL,
1029 		.mask = 0x7,
1030 		.shift = 25,
1031 	},
1032 	.hw.init = &(struct clk_init_data){
1033 		.name = "mali_1_sel",
1034 		.ops = &clk_regmap_mux_ops,
1035 		/*
1036 		 * bits 10:9 selects from 8 possible parents:
1037 		 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
1038 		 * fclk_div4, fclk_div3, fclk_div5
1039 		 */
1040 		.parent_data = gxbb_mali_0_1_parent_data,
1041 		.num_parents = 8,
1042 		.flags = CLK_SET_RATE_NO_REPARENT,
1043 	},
1044 };
1045 
1046 static struct clk_regmap gxbb_mali_1_div = {
1047 	.data = &(struct clk_regmap_div_data){
1048 		.offset = HHI_MALI_CLK_CNTL,
1049 		.shift = 16,
1050 		.width = 7,
1051 	},
1052 	.hw.init = &(struct clk_init_data){
1053 		.name = "mali_1_div",
1054 		.ops = &clk_regmap_divider_ops,
1055 		.parent_hws = (const struct clk_hw *[]) {
1056 			&gxbb_mali_1_sel.hw
1057 		},
1058 		.num_parents = 1,
1059 		.flags = CLK_SET_RATE_NO_REPARENT,
1060 	},
1061 };
1062 
1063 static struct clk_regmap gxbb_mali_1 = {
1064 	.data = &(struct clk_regmap_gate_data){
1065 		.offset = HHI_MALI_CLK_CNTL,
1066 		.bit_idx = 24,
1067 	},
1068 	.hw.init = &(struct clk_init_data){
1069 		.name = "mali_1",
1070 		.ops = &clk_regmap_gate_ops,
1071 		.parent_hws = (const struct clk_hw *[]) {
1072 			&gxbb_mali_1_div.hw
1073 		},
1074 		.num_parents = 1,
1075 		.flags = CLK_SET_RATE_PARENT,
1076 	},
1077 };
1078 
1079 static const struct clk_hw *gxbb_mali_parent_hws[] = {
1080 	&gxbb_mali_0.hw,
1081 	&gxbb_mali_1.hw,
1082 };
1083 
1084 static struct clk_regmap gxbb_mali = {
1085 	.data = &(struct clk_regmap_mux_data){
1086 		.offset = HHI_MALI_CLK_CNTL,
1087 		.mask = 1,
1088 		.shift = 31,
1089 	},
1090 	.hw.init = &(struct clk_init_data){
1091 		.name = "mali",
1092 		.ops = &clk_regmap_mux_ops,
1093 		.parent_hws = gxbb_mali_parent_hws,
1094 		.num_parents = 2,
1095 		.flags = CLK_SET_RATE_NO_REPARENT,
1096 	},
1097 };
1098 
1099 static struct clk_regmap gxbb_cts_amclk_sel = {
1100 	.data = &(struct clk_regmap_mux_data){
1101 		.offset = HHI_AUD_CLK_CNTL,
1102 		.mask = 0x3,
1103 		.shift = 9,
1104 		.table = (u32[]){ 1, 2, 3 },
1105 		.flags = CLK_MUX_ROUND_CLOSEST,
1106 	},
1107 	.hw.init = &(struct clk_init_data){
1108 		.name = "cts_amclk_sel",
1109 		.ops = &clk_regmap_mux_ops,
1110 		.parent_hws = (const struct clk_hw *[]) {
1111 			&gxbb_mpll0.hw,
1112 			&gxbb_mpll1.hw,
1113 			&gxbb_mpll2.hw,
1114 		},
1115 		.num_parents = 3,
1116 	},
1117 };
1118 
1119 static struct clk_regmap gxbb_cts_amclk_div = {
1120 	.data = &(struct clk_regmap_div_data) {
1121 		.offset = HHI_AUD_CLK_CNTL,
1122 		.shift = 0,
1123 		.width = 8,
1124 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1125 	},
1126 	.hw.init = &(struct clk_init_data){
1127 		.name = "cts_amclk_div",
1128 		.ops = &clk_regmap_divider_ops,
1129 		.parent_hws = (const struct clk_hw *[]) {
1130 			&gxbb_cts_amclk_sel.hw
1131 		},
1132 		.num_parents = 1,
1133 		.flags = CLK_SET_RATE_PARENT,
1134 	},
1135 };
1136 
1137 static struct clk_regmap gxbb_cts_amclk = {
1138 	.data = &(struct clk_regmap_gate_data){
1139 		.offset = HHI_AUD_CLK_CNTL,
1140 		.bit_idx = 8,
1141 	},
1142 	.hw.init = &(struct clk_init_data){
1143 		.name = "cts_amclk",
1144 		.ops = &clk_regmap_gate_ops,
1145 		.parent_hws = (const struct clk_hw *[]) {
1146 			&gxbb_cts_amclk_div.hw
1147 		},
1148 		.num_parents = 1,
1149 		.flags = CLK_SET_RATE_PARENT,
1150 	},
1151 };
1152 
1153 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1154 	.data = &(struct clk_regmap_mux_data){
1155 		.offset = HHI_AUD_CLK_CNTL2,
1156 		.mask = 0x3,
1157 		.shift = 25,
1158 		.table = (u32[]){ 1, 2, 3 },
1159 		.flags = CLK_MUX_ROUND_CLOSEST,
1160 	},
1161 	.hw.init = &(struct clk_init_data) {
1162 		.name = "cts_mclk_i958_sel",
1163 		.ops = &clk_regmap_mux_ops,
1164 		.parent_hws = (const struct clk_hw *[]) {
1165 			&gxbb_mpll0.hw,
1166 			&gxbb_mpll1.hw,
1167 			&gxbb_mpll2.hw,
1168 		},
1169 		.num_parents = 3,
1170 	},
1171 };
1172 
1173 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1174 	.data = &(struct clk_regmap_div_data){
1175 		.offset = HHI_AUD_CLK_CNTL2,
1176 		.shift = 16,
1177 		.width = 8,
1178 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1179 	},
1180 	.hw.init = &(struct clk_init_data) {
1181 		.name = "cts_mclk_i958_div",
1182 		.ops = &clk_regmap_divider_ops,
1183 		.parent_hws = (const struct clk_hw *[]) {
1184 			&gxbb_cts_mclk_i958_sel.hw
1185 		},
1186 		.num_parents = 1,
1187 		.flags = CLK_SET_RATE_PARENT,
1188 	},
1189 };
1190 
1191 static struct clk_regmap gxbb_cts_mclk_i958 = {
1192 	.data = &(struct clk_regmap_gate_data){
1193 		.offset = HHI_AUD_CLK_CNTL2,
1194 		.bit_idx = 24,
1195 	},
1196 	.hw.init = &(struct clk_init_data){
1197 		.name = "cts_mclk_i958",
1198 		.ops = &clk_regmap_gate_ops,
1199 		.parent_hws = (const struct clk_hw *[]) {
1200 			&gxbb_cts_mclk_i958_div.hw
1201 		},
1202 		.num_parents = 1,
1203 		.flags = CLK_SET_RATE_PARENT,
1204 	},
1205 };
1206 
1207 static struct clk_regmap gxbb_cts_i958 = {
1208 	.data = &(struct clk_regmap_mux_data){
1209 		.offset = HHI_AUD_CLK_CNTL2,
1210 		.mask = 0x1,
1211 		.shift = 27,
1212 		},
1213 	.hw.init = &(struct clk_init_data){
1214 		.name = "cts_i958",
1215 		.ops = &clk_regmap_mux_ops,
1216 		.parent_hws = (const struct clk_hw *[]) {
1217 			&gxbb_cts_amclk.hw,
1218 			&gxbb_cts_mclk_i958.hw
1219 		},
1220 		.num_parents = 2,
1221 		/*
1222 		 *The parent is specific to origin of the audio data. Let the
1223 		 * consumer choose the appropriate parent
1224 		 */
1225 		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1226 	},
1227 };
1228 
1229 static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1230 	{ .fw_name = "xtal", },
1231 	/*
1232 	 * FIXME: This clock is provided by the ao clock controller but the
1233 	 * clock is not yet part of the binding of this controller, so string
1234 	 * name must be use to set this parent.
1235 	 */
1236 	{ .name = "cts_slow_oscin", .index = -1 },
1237 	{ .hw = &gxbb_fclk_div3.hw },
1238 	{ .hw = &gxbb_fclk_div5.hw },
1239 };
1240 
1241 static struct clk_regmap gxbb_32k_clk_sel = {
1242 	.data = &(struct clk_regmap_mux_data){
1243 		.offset = HHI_32K_CLK_CNTL,
1244 		.mask = 0x3,
1245 		.shift = 16,
1246 		},
1247 	.hw.init = &(struct clk_init_data){
1248 		.name = "32k_clk_sel",
1249 		.ops = &clk_regmap_mux_ops,
1250 		.parent_data = gxbb_32k_clk_parent_data,
1251 		.num_parents = 4,
1252 		.flags = CLK_SET_RATE_PARENT,
1253 	},
1254 };
1255 
1256 static struct clk_regmap gxbb_32k_clk_div = {
1257 	.data = &(struct clk_regmap_div_data){
1258 		.offset = HHI_32K_CLK_CNTL,
1259 		.shift = 0,
1260 		.width = 14,
1261 	},
1262 	.hw.init = &(struct clk_init_data){
1263 		.name = "32k_clk_div",
1264 		.ops = &clk_regmap_divider_ops,
1265 		.parent_hws = (const struct clk_hw *[]) {
1266 			&gxbb_32k_clk_sel.hw
1267 		},
1268 		.num_parents = 1,
1269 		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1270 	},
1271 };
1272 
1273 static struct clk_regmap gxbb_32k_clk = {
1274 	.data = &(struct clk_regmap_gate_data){
1275 		.offset = HHI_32K_CLK_CNTL,
1276 		.bit_idx = 15,
1277 	},
1278 	.hw.init = &(struct clk_init_data){
1279 		.name = "32k_clk",
1280 		.ops = &clk_regmap_gate_ops,
1281 		.parent_hws = (const struct clk_hw *[]) {
1282 			&gxbb_32k_clk_div.hw
1283 		},
1284 		.num_parents = 1,
1285 		.flags = CLK_SET_RATE_PARENT,
1286 	},
1287 };
1288 
1289 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1290 	{ .fw_name = "xtal", },
1291 	{ .hw = &gxbb_fclk_div2.hw },
1292 	{ .hw = &gxbb_fclk_div3.hw },
1293 	{ .hw = &gxbb_fclk_div5.hw },
1294 	{ .hw = &gxbb_fclk_div7.hw },
1295 	/*
1296 	 * Following these parent clocks, we should also have had mpll2, mpll3
1297 	 * and gp0_pll but these clocks are too precious to be used here. All
1298 	 * the necessary rates for MMC and NAND operation can be acheived using
1299 	 * xtal or fclk_div clocks
1300 	 */
1301 };
1302 
1303 /* SDIO clock */
1304 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1305 	.data = &(struct clk_regmap_mux_data){
1306 		.offset = HHI_SD_EMMC_CLK_CNTL,
1307 		.mask = 0x7,
1308 		.shift = 9,
1309 	},
1310 	.hw.init = &(struct clk_init_data) {
1311 		.name = "sd_emmc_a_clk0_sel",
1312 		.ops = &clk_regmap_mux_ops,
1313 		.parent_data = gxbb_sd_emmc_clk0_parent_data,
1314 		.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1315 		.flags = CLK_SET_RATE_PARENT,
1316 	},
1317 };
1318 
1319 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1320 	.data = &(struct clk_regmap_div_data){
1321 		.offset = HHI_SD_EMMC_CLK_CNTL,
1322 		.shift = 0,
1323 		.width = 7,
1324 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1325 	},
1326 	.hw.init = &(struct clk_init_data) {
1327 		.name = "sd_emmc_a_clk0_div",
1328 		.ops = &clk_regmap_divider_ops,
1329 		.parent_hws = (const struct clk_hw *[]) {
1330 			&gxbb_sd_emmc_a_clk0_sel.hw
1331 		},
1332 		.num_parents = 1,
1333 		.flags = CLK_SET_RATE_PARENT,
1334 	},
1335 };
1336 
1337 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1338 	.data = &(struct clk_regmap_gate_data){
1339 		.offset = HHI_SD_EMMC_CLK_CNTL,
1340 		.bit_idx = 7,
1341 	},
1342 	.hw.init = &(struct clk_init_data){
1343 		.name = "sd_emmc_a_clk0",
1344 		.ops = &clk_regmap_gate_ops,
1345 		.parent_hws = (const struct clk_hw *[]) {
1346 			&gxbb_sd_emmc_a_clk0_div.hw
1347 		},
1348 		.num_parents = 1,
1349 		.flags = CLK_SET_RATE_PARENT,
1350 	},
1351 };
1352 
1353 /* SDcard clock */
1354 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1355 	.data = &(struct clk_regmap_mux_data){
1356 		.offset = HHI_SD_EMMC_CLK_CNTL,
1357 		.mask = 0x7,
1358 		.shift = 25,
1359 	},
1360 	.hw.init = &(struct clk_init_data) {
1361 		.name = "sd_emmc_b_clk0_sel",
1362 		.ops = &clk_regmap_mux_ops,
1363 		.parent_data = gxbb_sd_emmc_clk0_parent_data,
1364 		.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1365 		.flags = CLK_SET_RATE_PARENT,
1366 	},
1367 };
1368 
1369 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1370 	.data = &(struct clk_regmap_div_data){
1371 		.offset = HHI_SD_EMMC_CLK_CNTL,
1372 		.shift = 16,
1373 		.width = 7,
1374 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1375 	},
1376 	.hw.init = &(struct clk_init_data) {
1377 		.name = "sd_emmc_b_clk0_div",
1378 		.ops = &clk_regmap_divider_ops,
1379 		.parent_hws = (const struct clk_hw *[]) {
1380 			&gxbb_sd_emmc_b_clk0_sel.hw
1381 		},
1382 		.num_parents = 1,
1383 		.flags = CLK_SET_RATE_PARENT,
1384 	},
1385 };
1386 
1387 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1388 	.data = &(struct clk_regmap_gate_data){
1389 		.offset = HHI_SD_EMMC_CLK_CNTL,
1390 		.bit_idx = 23,
1391 	},
1392 	.hw.init = &(struct clk_init_data){
1393 		.name = "sd_emmc_b_clk0",
1394 		.ops = &clk_regmap_gate_ops,
1395 		.parent_hws = (const struct clk_hw *[]) {
1396 			&gxbb_sd_emmc_b_clk0_div.hw
1397 		},
1398 		.num_parents = 1,
1399 		.flags = CLK_SET_RATE_PARENT,
1400 	},
1401 };
1402 
1403 /* EMMC/NAND clock */
1404 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1405 	.data = &(struct clk_regmap_mux_data){
1406 		.offset = HHI_NAND_CLK_CNTL,
1407 		.mask = 0x7,
1408 		.shift = 9,
1409 	},
1410 	.hw.init = &(struct clk_init_data) {
1411 		.name = "sd_emmc_c_clk0_sel",
1412 		.ops = &clk_regmap_mux_ops,
1413 		.parent_data = gxbb_sd_emmc_clk0_parent_data,
1414 		.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1415 		.flags = CLK_SET_RATE_PARENT,
1416 	},
1417 };
1418 
1419 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1420 	.data = &(struct clk_regmap_div_data){
1421 		.offset = HHI_NAND_CLK_CNTL,
1422 		.shift = 0,
1423 		.width = 7,
1424 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1425 	},
1426 	.hw.init = &(struct clk_init_data) {
1427 		.name = "sd_emmc_c_clk0_div",
1428 		.ops = &clk_regmap_divider_ops,
1429 		.parent_hws = (const struct clk_hw *[]) {
1430 			&gxbb_sd_emmc_c_clk0_sel.hw
1431 		},
1432 		.num_parents = 1,
1433 		.flags = CLK_SET_RATE_PARENT,
1434 	},
1435 };
1436 
1437 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1438 	.data = &(struct clk_regmap_gate_data){
1439 		.offset = HHI_NAND_CLK_CNTL,
1440 		.bit_idx = 7,
1441 	},
1442 	.hw.init = &(struct clk_init_data){
1443 		.name = "sd_emmc_c_clk0",
1444 		.ops = &clk_regmap_gate_ops,
1445 		.parent_hws = (const struct clk_hw *[]) {
1446 			&gxbb_sd_emmc_c_clk0_div.hw
1447 		},
1448 		.num_parents = 1,
1449 		.flags = CLK_SET_RATE_PARENT,
1450 	},
1451 };
1452 
1453 /* VPU Clock */
1454 
1455 static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1456 	&gxbb_fclk_div4.hw,
1457 	&gxbb_fclk_div3.hw,
1458 	&gxbb_fclk_div5.hw,
1459 	&gxbb_fclk_div7.hw,
1460 };
1461 
1462 static struct clk_regmap gxbb_vpu_0_sel = {
1463 	.data = &(struct clk_regmap_mux_data){
1464 		.offset = HHI_VPU_CLK_CNTL,
1465 		.mask = 0x3,
1466 		.shift = 9,
1467 	},
1468 	.hw.init = &(struct clk_init_data){
1469 		.name = "vpu_0_sel",
1470 		.ops = &clk_regmap_mux_ops,
1471 		/*
1472 		 * bits 9:10 selects from 4 possible parents:
1473 		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1474 		 */
1475 		.parent_hws = gxbb_vpu_parent_hws,
1476 		.num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1477 		.flags = CLK_SET_RATE_NO_REPARENT,
1478 	},
1479 };
1480 
1481 static struct clk_regmap gxbb_vpu_0_div = {
1482 	.data = &(struct clk_regmap_div_data){
1483 		.offset = HHI_VPU_CLK_CNTL,
1484 		.shift = 0,
1485 		.width = 7,
1486 	},
1487 	.hw.init = &(struct clk_init_data){
1488 		.name = "vpu_0_div",
1489 		.ops = &clk_regmap_divider_ops,
1490 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1491 		.num_parents = 1,
1492 		.flags = CLK_SET_RATE_PARENT,
1493 	},
1494 };
1495 
1496 static struct clk_regmap gxbb_vpu_0 = {
1497 	.data = &(struct clk_regmap_gate_data){
1498 		.offset = HHI_VPU_CLK_CNTL,
1499 		.bit_idx = 8,
1500 	},
1501 	.hw.init = &(struct clk_init_data) {
1502 		.name = "vpu_0",
1503 		.ops = &clk_regmap_gate_ops,
1504 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1505 		.num_parents = 1,
1506 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1507 	},
1508 };
1509 
1510 static struct clk_regmap gxbb_vpu_1_sel = {
1511 	.data = &(struct clk_regmap_mux_data){
1512 		.offset = HHI_VPU_CLK_CNTL,
1513 		.mask = 0x3,
1514 		.shift = 25,
1515 	},
1516 	.hw.init = &(struct clk_init_data){
1517 		.name = "vpu_1_sel",
1518 		.ops = &clk_regmap_mux_ops,
1519 		/*
1520 		 * bits 25:26 selects from 4 possible parents:
1521 		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1522 		 */
1523 		.parent_hws = gxbb_vpu_parent_hws,
1524 		.num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1525 		.flags = CLK_SET_RATE_NO_REPARENT,
1526 	},
1527 };
1528 
1529 static struct clk_regmap gxbb_vpu_1_div = {
1530 	.data = &(struct clk_regmap_div_data){
1531 		.offset = HHI_VPU_CLK_CNTL,
1532 		.shift = 16,
1533 		.width = 7,
1534 	},
1535 	.hw.init = &(struct clk_init_data){
1536 		.name = "vpu_1_div",
1537 		.ops = &clk_regmap_divider_ops,
1538 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1539 		.num_parents = 1,
1540 		.flags = CLK_SET_RATE_PARENT,
1541 	},
1542 };
1543 
1544 static struct clk_regmap gxbb_vpu_1 = {
1545 	.data = &(struct clk_regmap_gate_data){
1546 		.offset = HHI_VPU_CLK_CNTL,
1547 		.bit_idx = 24,
1548 	},
1549 	.hw.init = &(struct clk_init_data) {
1550 		.name = "vpu_1",
1551 		.ops = &clk_regmap_gate_ops,
1552 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1553 		.num_parents = 1,
1554 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1555 	},
1556 };
1557 
1558 static struct clk_regmap gxbb_vpu = {
1559 	.data = &(struct clk_regmap_mux_data){
1560 		.offset = HHI_VPU_CLK_CNTL,
1561 		.mask = 1,
1562 		.shift = 31,
1563 	},
1564 	.hw.init = &(struct clk_init_data){
1565 		.name = "vpu",
1566 		.ops = &clk_regmap_mux_ops,
1567 		/*
1568 		 * bit 31 selects from 2 possible parents:
1569 		 * vpu_0 or vpu_1
1570 		 */
1571 		.parent_hws = (const struct clk_hw *[]) {
1572 			&gxbb_vpu_0.hw,
1573 			&gxbb_vpu_1.hw
1574 		},
1575 		.num_parents = 2,
1576 		.flags = CLK_SET_RATE_NO_REPARENT,
1577 	},
1578 };
1579 
1580 /* VAPB Clock */
1581 
1582 static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1583 	&gxbb_fclk_div4.hw,
1584 	&gxbb_fclk_div3.hw,
1585 	&gxbb_fclk_div5.hw,
1586 	&gxbb_fclk_div7.hw,
1587 };
1588 
1589 static struct clk_regmap gxbb_vapb_0_sel = {
1590 	.data = &(struct clk_regmap_mux_data){
1591 		.offset = HHI_VAPBCLK_CNTL,
1592 		.mask = 0x3,
1593 		.shift = 9,
1594 	},
1595 	.hw.init = &(struct clk_init_data){
1596 		.name = "vapb_0_sel",
1597 		.ops = &clk_regmap_mux_ops,
1598 		/*
1599 		 * bits 9:10 selects from 4 possible parents:
1600 		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1601 		 */
1602 		.parent_hws = gxbb_vapb_parent_hws,
1603 		.num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1604 		.flags = CLK_SET_RATE_NO_REPARENT,
1605 	},
1606 };
1607 
1608 static struct clk_regmap gxbb_vapb_0_div = {
1609 	.data = &(struct clk_regmap_div_data){
1610 		.offset = HHI_VAPBCLK_CNTL,
1611 		.shift = 0,
1612 		.width = 7,
1613 	},
1614 	.hw.init = &(struct clk_init_data){
1615 		.name = "vapb_0_div",
1616 		.ops = &clk_regmap_divider_ops,
1617 		.parent_hws = (const struct clk_hw *[]) {
1618 			&gxbb_vapb_0_sel.hw
1619 		},
1620 		.num_parents = 1,
1621 		.flags = CLK_SET_RATE_PARENT,
1622 	},
1623 };
1624 
1625 static struct clk_regmap gxbb_vapb_0 = {
1626 	.data = &(struct clk_regmap_gate_data){
1627 		.offset = HHI_VAPBCLK_CNTL,
1628 		.bit_idx = 8,
1629 	},
1630 	.hw.init = &(struct clk_init_data) {
1631 		.name = "vapb_0",
1632 		.ops = &clk_regmap_gate_ops,
1633 		.parent_hws = (const struct clk_hw *[]) {
1634 			&gxbb_vapb_0_div.hw
1635 		},
1636 		.num_parents = 1,
1637 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1638 	},
1639 };
1640 
1641 static struct clk_regmap gxbb_vapb_1_sel = {
1642 	.data = &(struct clk_regmap_mux_data){
1643 		.offset = HHI_VAPBCLK_CNTL,
1644 		.mask = 0x3,
1645 		.shift = 25,
1646 	},
1647 	.hw.init = &(struct clk_init_data){
1648 		.name = "vapb_1_sel",
1649 		.ops = &clk_regmap_mux_ops,
1650 		/*
1651 		 * bits 25:26 selects from 4 possible parents:
1652 		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1653 		 */
1654 		.parent_hws = gxbb_vapb_parent_hws,
1655 		.num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1656 		.flags = CLK_SET_RATE_NO_REPARENT,
1657 	},
1658 };
1659 
1660 static struct clk_regmap gxbb_vapb_1_div = {
1661 	.data = &(struct clk_regmap_div_data){
1662 		.offset = HHI_VAPBCLK_CNTL,
1663 		.shift = 16,
1664 		.width = 7,
1665 	},
1666 	.hw.init = &(struct clk_init_data){
1667 		.name = "vapb_1_div",
1668 		.ops = &clk_regmap_divider_ops,
1669 		.parent_hws = (const struct clk_hw *[]) {
1670 			&gxbb_vapb_1_sel.hw
1671 		},
1672 		.num_parents = 1,
1673 		.flags = CLK_SET_RATE_PARENT,
1674 	},
1675 };
1676 
1677 static struct clk_regmap gxbb_vapb_1 = {
1678 	.data = &(struct clk_regmap_gate_data){
1679 		.offset = HHI_VAPBCLK_CNTL,
1680 		.bit_idx = 24,
1681 	},
1682 	.hw.init = &(struct clk_init_data) {
1683 		.name = "vapb_1",
1684 		.ops = &clk_regmap_gate_ops,
1685 		.parent_hws = (const struct clk_hw *[]) {
1686 			&gxbb_vapb_1_div.hw
1687 		},
1688 		.num_parents = 1,
1689 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1690 	},
1691 };
1692 
1693 static struct clk_regmap gxbb_vapb_sel = {
1694 	.data = &(struct clk_regmap_mux_data){
1695 		.offset = HHI_VAPBCLK_CNTL,
1696 		.mask = 1,
1697 		.shift = 31,
1698 	},
1699 	.hw.init = &(struct clk_init_data){
1700 		.name = "vapb_sel",
1701 		.ops = &clk_regmap_mux_ops,
1702 		/*
1703 		 * bit 31 selects from 2 possible parents:
1704 		 * vapb_0 or vapb_1
1705 		 */
1706 		.parent_hws = (const struct clk_hw *[]) {
1707 			&gxbb_vapb_0.hw,
1708 			&gxbb_vapb_1.hw
1709 		},
1710 		.num_parents = 2,
1711 		.flags = CLK_SET_RATE_NO_REPARENT,
1712 	},
1713 };
1714 
1715 static struct clk_regmap gxbb_vapb = {
1716 	.data = &(struct clk_regmap_gate_data){
1717 		.offset = HHI_VAPBCLK_CNTL,
1718 		.bit_idx = 30,
1719 	},
1720 	.hw.init = &(struct clk_init_data) {
1721 		.name = "vapb",
1722 		.ops = &clk_regmap_gate_ops,
1723 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1724 		.num_parents = 1,
1725 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1726 	},
1727 };
1728 
1729 /* Video Clocks */
1730 
1731 static struct clk_regmap gxbb_vid_pll_div = {
1732 	.data = &(struct meson_vid_pll_div_data){
1733 		.val = {
1734 			.reg_off = HHI_VID_PLL_CLK_DIV,
1735 			.shift   = 0,
1736 			.width   = 15,
1737 		},
1738 		.sel = {
1739 			.reg_off = HHI_VID_PLL_CLK_DIV,
1740 			.shift   = 16,
1741 			.width   = 2,
1742 		},
1743 	},
1744 	.hw.init = &(struct clk_init_data) {
1745 		.name = "vid_pll_div",
1746 		.ops = &meson_vid_pll_div_ro_ops,
1747 		.parent_data = &(const struct clk_parent_data) {
1748 			/*
1749 			 * Note:
1750 			 * GXL and GXBB have different hdmi_plls (with
1751 			 * different struct clk_hw). We fallback to the global
1752 			 * naming string mechanism so vid_pll_div picks up the
1753 			 * appropriate one.
1754 			 */
1755 			.name = "hdmi_pll",
1756 			.index = -1,
1757 		},
1758 		.num_parents = 1,
1759 		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1760 	},
1761 };
1762 
1763 static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1764 	{ .hw = &gxbb_vid_pll_div.hw },
1765 	/*
1766 	 * Note:
1767 	 * GXL and GXBB have different hdmi_plls (with
1768 	 * different struct clk_hw). We fallback to the global
1769 	 * naming string mechanism so vid_pll_div picks up the
1770 	 * appropriate one.
1771 	 */
1772 	{ .name = "hdmi_pll", .index = -1 },
1773 };
1774 
1775 static struct clk_regmap gxbb_vid_pll_sel = {
1776 	.data = &(struct clk_regmap_mux_data){
1777 		.offset = HHI_VID_PLL_CLK_DIV,
1778 		.mask = 0x1,
1779 		.shift = 18,
1780 	},
1781 	.hw.init = &(struct clk_init_data){
1782 		.name = "vid_pll_sel",
1783 		.ops = &clk_regmap_mux_ops,
1784 		/*
1785 		 * bit 18 selects from 2 possible parents:
1786 		 * vid_pll_div or hdmi_pll
1787 		 */
1788 		.parent_data = gxbb_vid_pll_parent_data,
1789 		.num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1790 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1791 	},
1792 };
1793 
1794 static struct clk_regmap gxbb_vid_pll = {
1795 	.data = &(struct clk_regmap_gate_data){
1796 		.offset = HHI_VID_PLL_CLK_DIV,
1797 		.bit_idx = 19,
1798 	},
1799 	.hw.init = &(struct clk_init_data) {
1800 		.name = "vid_pll",
1801 		.ops = &clk_regmap_gate_ops,
1802 		.parent_hws = (const struct clk_hw *[]) {
1803 			&gxbb_vid_pll_sel.hw
1804 		},
1805 		.num_parents = 1,
1806 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1807 	},
1808 };
1809 
1810 static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1811 	&gxbb_vid_pll.hw,
1812 	&gxbb_fclk_div4.hw,
1813 	&gxbb_fclk_div3.hw,
1814 	&gxbb_fclk_div5.hw,
1815 	&gxbb_vid_pll.hw,
1816 	&gxbb_fclk_div7.hw,
1817 	&gxbb_mpll1.hw,
1818 };
1819 
1820 static struct clk_regmap gxbb_vclk_sel = {
1821 	.data = &(struct clk_regmap_mux_data){
1822 		.offset = HHI_VID_CLK_CNTL,
1823 		.mask = 0x7,
1824 		.shift = 16,
1825 	},
1826 	.hw.init = &(struct clk_init_data){
1827 		.name = "vclk_sel",
1828 		.ops = &clk_regmap_mux_ops,
1829 		/*
1830 		 * bits 16:18 selects from 8 possible parents:
1831 		 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1832 		 * vid_pll, fclk_div7, mp1
1833 		 */
1834 		.parent_hws = gxbb_vclk_parent_hws,
1835 		.num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1836 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1837 	},
1838 };
1839 
1840 static struct clk_regmap gxbb_vclk2_sel = {
1841 	.data = &(struct clk_regmap_mux_data){
1842 		.offset = HHI_VIID_CLK_CNTL,
1843 		.mask = 0x7,
1844 		.shift = 16,
1845 	},
1846 	.hw.init = &(struct clk_init_data){
1847 		.name = "vclk2_sel",
1848 		.ops = &clk_regmap_mux_ops,
1849 		/*
1850 		 * bits 16:18 selects from 8 possible parents:
1851 		 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1852 		 * vid_pll, fclk_div7, mp1
1853 		 */
1854 		.parent_hws = gxbb_vclk_parent_hws,
1855 		.num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1856 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1857 	},
1858 };
1859 
1860 static struct clk_regmap gxbb_vclk_input = {
1861 	.data = &(struct clk_regmap_gate_data){
1862 		.offset = HHI_VID_CLK_DIV,
1863 		.bit_idx = 16,
1864 	},
1865 	.hw.init = &(struct clk_init_data) {
1866 		.name = "vclk_input",
1867 		.ops = &clk_regmap_gate_ops,
1868 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1869 		.num_parents = 1,
1870 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1871 	},
1872 };
1873 
1874 static struct clk_regmap gxbb_vclk2_input = {
1875 	.data = &(struct clk_regmap_gate_data){
1876 		.offset = HHI_VIID_CLK_DIV,
1877 		.bit_idx = 16,
1878 	},
1879 	.hw.init = &(struct clk_init_data) {
1880 		.name = "vclk2_input",
1881 		.ops = &clk_regmap_gate_ops,
1882 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1883 		.num_parents = 1,
1884 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1885 	},
1886 };
1887 
1888 static struct clk_regmap gxbb_vclk_div = {
1889 	.data = &(struct clk_regmap_div_data){
1890 		.offset = HHI_VID_CLK_DIV,
1891 		.shift = 0,
1892 		.width = 8,
1893 	},
1894 	.hw.init = &(struct clk_init_data){
1895 		.name = "vclk_div",
1896 		.ops = &clk_regmap_divider_ops,
1897 		.parent_hws = (const struct clk_hw *[]) {
1898 			&gxbb_vclk_input.hw
1899 		},
1900 		.num_parents = 1,
1901 		.flags = CLK_GET_RATE_NOCACHE,
1902 	},
1903 };
1904 
1905 static struct clk_regmap gxbb_vclk2_div = {
1906 	.data = &(struct clk_regmap_div_data){
1907 		.offset = HHI_VIID_CLK_DIV,
1908 		.shift = 0,
1909 		.width = 8,
1910 	},
1911 	.hw.init = &(struct clk_init_data){
1912 		.name = "vclk2_div",
1913 		.ops = &clk_regmap_divider_ops,
1914 		.parent_hws = (const struct clk_hw *[]) {
1915 			&gxbb_vclk2_input.hw
1916 		},
1917 		.num_parents = 1,
1918 		.flags = CLK_GET_RATE_NOCACHE,
1919 	},
1920 };
1921 
1922 static struct clk_regmap gxbb_vclk = {
1923 	.data = &(struct clk_regmap_gate_data){
1924 		.offset = HHI_VID_CLK_CNTL,
1925 		.bit_idx = 19,
1926 	},
1927 	.hw.init = &(struct clk_init_data) {
1928 		.name = "vclk",
1929 		.ops = &clk_regmap_gate_ops,
1930 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1931 		.num_parents = 1,
1932 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1933 	},
1934 };
1935 
1936 static struct clk_regmap gxbb_vclk2 = {
1937 	.data = &(struct clk_regmap_gate_data){
1938 		.offset = HHI_VIID_CLK_CNTL,
1939 		.bit_idx = 19,
1940 	},
1941 	.hw.init = &(struct clk_init_data) {
1942 		.name = "vclk2",
1943 		.ops = &clk_regmap_gate_ops,
1944 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1945 		.num_parents = 1,
1946 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1947 	},
1948 };
1949 
1950 static struct clk_regmap gxbb_vclk_div1 = {
1951 	.data = &(struct clk_regmap_gate_data){
1952 		.offset = HHI_VID_CLK_CNTL,
1953 		.bit_idx = 0,
1954 	},
1955 	.hw.init = &(struct clk_init_data) {
1956 		.name = "vclk_div1",
1957 		.ops = &clk_regmap_gate_ops,
1958 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1959 		.num_parents = 1,
1960 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1961 	},
1962 };
1963 
1964 static struct clk_regmap gxbb_vclk_div2_en = {
1965 	.data = &(struct clk_regmap_gate_data){
1966 		.offset = HHI_VID_CLK_CNTL,
1967 		.bit_idx = 1,
1968 	},
1969 	.hw.init = &(struct clk_init_data) {
1970 		.name = "vclk_div2_en",
1971 		.ops = &clk_regmap_gate_ops,
1972 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1973 		.num_parents = 1,
1974 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1975 	},
1976 };
1977 
1978 static struct clk_regmap gxbb_vclk_div4_en = {
1979 	.data = &(struct clk_regmap_gate_data){
1980 		.offset = HHI_VID_CLK_CNTL,
1981 		.bit_idx = 2,
1982 	},
1983 	.hw.init = &(struct clk_init_data) {
1984 		.name = "vclk_div4_en",
1985 		.ops = &clk_regmap_gate_ops,
1986 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1987 		.num_parents = 1,
1988 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1989 	},
1990 };
1991 
1992 static struct clk_regmap gxbb_vclk_div6_en = {
1993 	.data = &(struct clk_regmap_gate_data){
1994 		.offset = HHI_VID_CLK_CNTL,
1995 		.bit_idx = 3,
1996 	},
1997 	.hw.init = &(struct clk_init_data) {
1998 		.name = "vclk_div6_en",
1999 		.ops = &clk_regmap_gate_ops,
2000 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2001 		.num_parents = 1,
2002 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2003 	},
2004 };
2005 
2006 static struct clk_regmap gxbb_vclk_div12_en = {
2007 	.data = &(struct clk_regmap_gate_data){
2008 		.offset = HHI_VID_CLK_CNTL,
2009 		.bit_idx = 4,
2010 	},
2011 	.hw.init = &(struct clk_init_data) {
2012 		.name = "vclk_div12_en",
2013 		.ops = &clk_regmap_gate_ops,
2014 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2015 		.num_parents = 1,
2016 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2017 	},
2018 };
2019 
2020 static struct clk_regmap gxbb_vclk2_div1 = {
2021 	.data = &(struct clk_regmap_gate_data){
2022 		.offset = HHI_VIID_CLK_CNTL,
2023 		.bit_idx = 0,
2024 	},
2025 	.hw.init = &(struct clk_init_data) {
2026 		.name = "vclk2_div1",
2027 		.ops = &clk_regmap_gate_ops,
2028 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2029 		.num_parents = 1,
2030 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2031 	},
2032 };
2033 
2034 static struct clk_regmap gxbb_vclk2_div2_en = {
2035 	.data = &(struct clk_regmap_gate_data){
2036 		.offset = HHI_VIID_CLK_CNTL,
2037 		.bit_idx = 1,
2038 	},
2039 	.hw.init = &(struct clk_init_data) {
2040 		.name = "vclk2_div2_en",
2041 		.ops = &clk_regmap_gate_ops,
2042 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2043 		.num_parents = 1,
2044 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2045 	},
2046 };
2047 
2048 static struct clk_regmap gxbb_vclk2_div4_en = {
2049 	.data = &(struct clk_regmap_gate_data){
2050 		.offset = HHI_VIID_CLK_CNTL,
2051 		.bit_idx = 2,
2052 	},
2053 	.hw.init = &(struct clk_init_data) {
2054 		.name = "vclk2_div4_en",
2055 		.ops = &clk_regmap_gate_ops,
2056 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2057 		.num_parents = 1,
2058 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2059 	},
2060 };
2061 
2062 static struct clk_regmap gxbb_vclk2_div6_en = {
2063 	.data = &(struct clk_regmap_gate_data){
2064 		.offset = HHI_VIID_CLK_CNTL,
2065 		.bit_idx = 3,
2066 	},
2067 	.hw.init = &(struct clk_init_data) {
2068 		.name = "vclk2_div6_en",
2069 		.ops = &clk_regmap_gate_ops,
2070 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2071 		.num_parents = 1,
2072 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2073 	},
2074 };
2075 
2076 static struct clk_regmap gxbb_vclk2_div12_en = {
2077 	.data = &(struct clk_regmap_gate_data){
2078 		.offset = HHI_VIID_CLK_CNTL,
2079 		.bit_idx = 4,
2080 	},
2081 	.hw.init = &(struct clk_init_data) {
2082 		.name = "vclk2_div12_en",
2083 		.ops = &clk_regmap_gate_ops,
2084 		.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2085 		.num_parents = 1,
2086 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2087 	},
2088 };
2089 
2090 static struct clk_fixed_factor gxbb_vclk_div2 = {
2091 	.mult = 1,
2092 	.div = 2,
2093 	.hw.init = &(struct clk_init_data){
2094 		.name = "vclk_div2",
2095 		.ops = &clk_fixed_factor_ops,
2096 		.parent_hws = (const struct clk_hw *[]) {
2097 			&gxbb_vclk_div2_en.hw
2098 		},
2099 		.num_parents = 1,
2100 	},
2101 };
2102 
2103 static struct clk_fixed_factor gxbb_vclk_div4 = {
2104 	.mult = 1,
2105 	.div = 4,
2106 	.hw.init = &(struct clk_init_data){
2107 		.name = "vclk_div4",
2108 		.ops = &clk_fixed_factor_ops,
2109 		.parent_hws = (const struct clk_hw *[]) {
2110 			&gxbb_vclk_div4_en.hw
2111 		},
2112 		.num_parents = 1,
2113 	},
2114 };
2115 
2116 static struct clk_fixed_factor gxbb_vclk_div6 = {
2117 	.mult = 1,
2118 	.div = 6,
2119 	.hw.init = &(struct clk_init_data){
2120 		.name = "vclk_div6",
2121 		.ops = &clk_fixed_factor_ops,
2122 		.parent_hws = (const struct clk_hw *[]) {
2123 			&gxbb_vclk_div6_en.hw
2124 		},
2125 		.num_parents = 1,
2126 	},
2127 };
2128 
2129 static struct clk_fixed_factor gxbb_vclk_div12 = {
2130 	.mult = 1,
2131 	.div = 12,
2132 	.hw.init = &(struct clk_init_data){
2133 		.name = "vclk_div12",
2134 		.ops = &clk_fixed_factor_ops,
2135 		.parent_hws = (const struct clk_hw *[]) {
2136 			&gxbb_vclk_div12_en.hw
2137 		},
2138 		.num_parents = 1,
2139 	},
2140 };
2141 
2142 static struct clk_fixed_factor gxbb_vclk2_div2 = {
2143 	.mult = 1,
2144 	.div = 2,
2145 	.hw.init = &(struct clk_init_data){
2146 		.name = "vclk2_div2",
2147 		.ops = &clk_fixed_factor_ops,
2148 		.parent_hws = (const struct clk_hw *[]) {
2149 			&gxbb_vclk2_div2_en.hw
2150 		},
2151 		.num_parents = 1,
2152 	},
2153 };
2154 
2155 static struct clk_fixed_factor gxbb_vclk2_div4 = {
2156 	.mult = 1,
2157 	.div = 4,
2158 	.hw.init = &(struct clk_init_data){
2159 		.name = "vclk2_div4",
2160 		.ops = &clk_fixed_factor_ops,
2161 		.parent_hws = (const struct clk_hw *[]) {
2162 			&gxbb_vclk2_div4_en.hw
2163 		},
2164 		.num_parents = 1,
2165 	},
2166 };
2167 
2168 static struct clk_fixed_factor gxbb_vclk2_div6 = {
2169 	.mult = 1,
2170 	.div = 6,
2171 	.hw.init = &(struct clk_init_data){
2172 		.name = "vclk2_div6",
2173 		.ops = &clk_fixed_factor_ops,
2174 		.parent_hws = (const struct clk_hw *[]) {
2175 			&gxbb_vclk2_div6_en.hw
2176 		},
2177 		.num_parents = 1,
2178 	},
2179 };
2180 
2181 static struct clk_fixed_factor gxbb_vclk2_div12 = {
2182 	.mult = 1,
2183 	.div = 12,
2184 	.hw.init = &(struct clk_init_data){
2185 		.name = "vclk2_div12",
2186 		.ops = &clk_fixed_factor_ops,
2187 		.parent_hws = (const struct clk_hw *[]) {
2188 			&gxbb_vclk2_div12_en.hw
2189 		},
2190 		.num_parents = 1,
2191 	},
2192 };
2193 
2194 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2195 static const struct clk_hw *gxbb_cts_parent_hws[] = {
2196 	&gxbb_vclk_div1.hw,
2197 	&gxbb_vclk_div2.hw,
2198 	&gxbb_vclk_div4.hw,
2199 	&gxbb_vclk_div6.hw,
2200 	&gxbb_vclk_div12.hw,
2201 	&gxbb_vclk2_div1.hw,
2202 	&gxbb_vclk2_div2.hw,
2203 	&gxbb_vclk2_div4.hw,
2204 	&gxbb_vclk2_div6.hw,
2205 	&gxbb_vclk2_div12.hw,
2206 };
2207 
2208 static struct clk_regmap gxbb_cts_enci_sel = {
2209 	.data = &(struct clk_regmap_mux_data){
2210 		.offset = HHI_VID_CLK_DIV,
2211 		.mask = 0xf,
2212 		.shift = 28,
2213 		.table = mux_table_cts_sel,
2214 	},
2215 	.hw.init = &(struct clk_init_data){
2216 		.name = "cts_enci_sel",
2217 		.ops = &clk_regmap_mux_ops,
2218 		.parent_hws = gxbb_cts_parent_hws,
2219 		.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2220 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2221 	},
2222 };
2223 
2224 static struct clk_regmap gxbb_cts_encp_sel = {
2225 	.data = &(struct clk_regmap_mux_data){
2226 		.offset = HHI_VID_CLK_DIV,
2227 		.mask = 0xf,
2228 		.shift = 20,
2229 		.table = mux_table_cts_sel,
2230 	},
2231 	.hw.init = &(struct clk_init_data){
2232 		.name = "cts_encp_sel",
2233 		.ops = &clk_regmap_mux_ops,
2234 		.parent_hws = gxbb_cts_parent_hws,
2235 		.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2236 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2237 	},
2238 };
2239 
2240 static struct clk_regmap gxbb_cts_vdac_sel = {
2241 	.data = &(struct clk_regmap_mux_data){
2242 		.offset = HHI_VIID_CLK_DIV,
2243 		.mask = 0xf,
2244 		.shift = 28,
2245 		.table = mux_table_cts_sel,
2246 	},
2247 	.hw.init = &(struct clk_init_data){
2248 		.name = "cts_vdac_sel",
2249 		.ops = &clk_regmap_mux_ops,
2250 		.parent_hws = gxbb_cts_parent_hws,
2251 		.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2252 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2253 	},
2254 };
2255 
2256 /* TOFIX: add support for cts_tcon */
2257 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2258 static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2259 	&gxbb_vclk_div1.hw,
2260 	&gxbb_vclk_div2.hw,
2261 	&gxbb_vclk_div4.hw,
2262 	&gxbb_vclk_div6.hw,
2263 	&gxbb_vclk_div12.hw,
2264 	&gxbb_vclk2_div1.hw,
2265 	&gxbb_vclk2_div2.hw,
2266 	&gxbb_vclk2_div4.hw,
2267 	&gxbb_vclk2_div6.hw,
2268 	&gxbb_vclk2_div12.hw,
2269 };
2270 
2271 static struct clk_regmap gxbb_hdmi_tx_sel = {
2272 	.data = &(struct clk_regmap_mux_data){
2273 		.offset = HHI_HDMI_CLK_CNTL,
2274 		.mask = 0xf,
2275 		.shift = 16,
2276 		.table = mux_table_hdmi_tx_sel,
2277 	},
2278 	.hw.init = &(struct clk_init_data){
2279 		.name = "hdmi_tx_sel",
2280 		.ops = &clk_regmap_mux_ops,
2281 		/*
2282 		 * bits 31:28 selects from 12 possible parents:
2283 		 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2284 		 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2285 		 * cts_tcon
2286 		 */
2287 		.parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2288 		.num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2289 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2290 	},
2291 };
2292 
2293 static struct clk_regmap gxbb_cts_enci = {
2294 	.data = &(struct clk_regmap_gate_data){
2295 		.offset = HHI_VID_CLK_CNTL2,
2296 		.bit_idx = 0,
2297 	},
2298 	.hw.init = &(struct clk_init_data) {
2299 		.name = "cts_enci",
2300 		.ops = &clk_regmap_gate_ops,
2301 		.parent_hws = (const struct clk_hw *[]) {
2302 			&gxbb_cts_enci_sel.hw
2303 		},
2304 		.num_parents = 1,
2305 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2306 	},
2307 };
2308 
2309 static struct clk_regmap gxbb_cts_encp = {
2310 	.data = &(struct clk_regmap_gate_data){
2311 		.offset = HHI_VID_CLK_CNTL2,
2312 		.bit_idx = 2,
2313 	},
2314 	.hw.init = &(struct clk_init_data) {
2315 		.name = "cts_encp",
2316 		.ops = &clk_regmap_gate_ops,
2317 		.parent_hws = (const struct clk_hw *[]) {
2318 			&gxbb_cts_encp_sel.hw
2319 		},
2320 		.num_parents = 1,
2321 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2322 	},
2323 };
2324 
2325 static struct clk_regmap gxbb_cts_vdac = {
2326 	.data = &(struct clk_regmap_gate_data){
2327 		.offset = HHI_VID_CLK_CNTL2,
2328 		.bit_idx = 4,
2329 	},
2330 	.hw.init = &(struct clk_init_data) {
2331 		.name = "cts_vdac",
2332 		.ops = &clk_regmap_gate_ops,
2333 		.parent_hws = (const struct clk_hw *[]) {
2334 			&gxbb_cts_vdac_sel.hw
2335 		},
2336 		.num_parents = 1,
2337 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2338 	},
2339 };
2340 
2341 static struct clk_regmap gxbb_hdmi_tx = {
2342 	.data = &(struct clk_regmap_gate_data){
2343 		.offset = HHI_VID_CLK_CNTL2,
2344 		.bit_idx = 5,
2345 	},
2346 	.hw.init = &(struct clk_init_data) {
2347 		.name = "hdmi_tx",
2348 		.ops = &clk_regmap_gate_ops,
2349 		.parent_hws = (const struct clk_hw *[]) {
2350 			&gxbb_hdmi_tx_sel.hw
2351 		},
2352 		.num_parents = 1,
2353 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2354 	},
2355 };
2356 
2357 /* HDMI Clocks */
2358 
2359 static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2360 	{ .fw_name = "xtal", },
2361 	{ .hw = &gxbb_fclk_div4.hw },
2362 	{ .hw = &gxbb_fclk_div3.hw },
2363 	{ .hw = &gxbb_fclk_div5.hw },
2364 };
2365 
2366 static struct clk_regmap gxbb_hdmi_sel = {
2367 	.data = &(struct clk_regmap_mux_data){
2368 		.offset = HHI_HDMI_CLK_CNTL,
2369 		.mask = 0x3,
2370 		.shift = 9,
2371 		.flags = CLK_MUX_ROUND_CLOSEST,
2372 	},
2373 	.hw.init = &(struct clk_init_data){
2374 		.name = "hdmi_sel",
2375 		.ops = &clk_regmap_mux_ops,
2376 		.parent_data = gxbb_hdmi_parent_data,
2377 		.num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2378 		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2379 	},
2380 };
2381 
2382 static struct clk_regmap gxbb_hdmi_div = {
2383 	.data = &(struct clk_regmap_div_data){
2384 		.offset = HHI_HDMI_CLK_CNTL,
2385 		.shift = 0,
2386 		.width = 7,
2387 	},
2388 	.hw.init = &(struct clk_init_data){
2389 		.name = "hdmi_div",
2390 		.ops = &clk_regmap_divider_ops,
2391 		.parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2392 		.num_parents = 1,
2393 		.flags = CLK_GET_RATE_NOCACHE,
2394 	},
2395 };
2396 
2397 static struct clk_regmap gxbb_hdmi = {
2398 	.data = &(struct clk_regmap_gate_data){
2399 		.offset = HHI_HDMI_CLK_CNTL,
2400 		.bit_idx = 8,
2401 	},
2402 	.hw.init = &(struct clk_init_data) {
2403 		.name = "hdmi",
2404 		.ops = &clk_regmap_gate_ops,
2405 		.parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2406 		.num_parents = 1,
2407 		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2408 	},
2409 };
2410 
2411 /* VDEC clocks */
2412 
2413 static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2414 	&gxbb_fclk_div4.hw,
2415 	&gxbb_fclk_div3.hw,
2416 	&gxbb_fclk_div5.hw,
2417 	&gxbb_fclk_div7.hw,
2418 };
2419 
2420 static struct clk_regmap gxbb_vdec_1_sel = {
2421 	.data = &(struct clk_regmap_mux_data){
2422 		.offset = HHI_VDEC_CLK_CNTL,
2423 		.mask = 0x3,
2424 		.shift = 9,
2425 		.flags = CLK_MUX_ROUND_CLOSEST,
2426 	},
2427 	.hw.init = &(struct clk_init_data){
2428 		.name = "vdec_1_sel",
2429 		.ops = &clk_regmap_mux_ops,
2430 		.parent_hws = gxbb_vdec_parent_hws,
2431 		.num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2432 		.flags = CLK_SET_RATE_PARENT,
2433 	},
2434 };
2435 
2436 static struct clk_regmap gxbb_vdec_1_div = {
2437 	.data = &(struct clk_regmap_div_data){
2438 		.offset = HHI_VDEC_CLK_CNTL,
2439 		.shift = 0,
2440 		.width = 7,
2441 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2442 	},
2443 	.hw.init = &(struct clk_init_data){
2444 		.name = "vdec_1_div",
2445 		.ops = &clk_regmap_divider_ops,
2446 		.parent_hws = (const struct clk_hw *[]) {
2447 			&gxbb_vdec_1_sel.hw
2448 		},
2449 		.num_parents = 1,
2450 		.flags = CLK_SET_RATE_PARENT,
2451 	},
2452 };
2453 
2454 static struct clk_regmap gxbb_vdec_1 = {
2455 	.data = &(struct clk_regmap_gate_data){
2456 		.offset = HHI_VDEC_CLK_CNTL,
2457 		.bit_idx = 8,
2458 	},
2459 	.hw.init = &(struct clk_init_data) {
2460 		.name = "vdec_1",
2461 		.ops = &clk_regmap_gate_ops,
2462 		.parent_hws = (const struct clk_hw *[]) {
2463 			&gxbb_vdec_1_div.hw
2464 		},
2465 		.num_parents = 1,
2466 		.flags = CLK_SET_RATE_PARENT,
2467 	},
2468 };
2469 
2470 static struct clk_regmap gxbb_vdec_hevc_sel = {
2471 	.data = &(struct clk_regmap_mux_data){
2472 		.offset = HHI_VDEC2_CLK_CNTL,
2473 		.mask = 0x3,
2474 		.shift = 25,
2475 		.flags = CLK_MUX_ROUND_CLOSEST,
2476 	},
2477 	.hw.init = &(struct clk_init_data){
2478 		.name = "vdec_hevc_sel",
2479 		.ops = &clk_regmap_mux_ops,
2480 		.parent_hws = gxbb_vdec_parent_hws,
2481 		.num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2482 		.flags = CLK_SET_RATE_PARENT,
2483 	},
2484 };
2485 
2486 static struct clk_regmap gxbb_vdec_hevc_div = {
2487 	.data = &(struct clk_regmap_div_data){
2488 		.offset = HHI_VDEC2_CLK_CNTL,
2489 		.shift = 16,
2490 		.width = 7,
2491 		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2492 	},
2493 	.hw.init = &(struct clk_init_data){
2494 		.name = "vdec_hevc_div",
2495 		.ops = &clk_regmap_divider_ops,
2496 		.parent_hws = (const struct clk_hw *[]) {
2497 			&gxbb_vdec_hevc_sel.hw
2498 		},
2499 		.num_parents = 1,
2500 		.flags = CLK_SET_RATE_PARENT,
2501 	},
2502 };
2503 
2504 static struct clk_regmap gxbb_vdec_hevc = {
2505 	.data = &(struct clk_regmap_gate_data){
2506 		.offset = HHI_VDEC2_CLK_CNTL,
2507 		.bit_idx = 24,
2508 	},
2509 	.hw.init = &(struct clk_init_data) {
2510 		.name = "vdec_hevc",
2511 		.ops = &clk_regmap_gate_ops,
2512 		.parent_hws = (const struct clk_hw *[]) {
2513 			&gxbb_vdec_hevc_div.hw
2514 		},
2515 		.num_parents = 1,
2516 		.flags = CLK_SET_RATE_PARENT,
2517 	},
2518 };
2519 
2520 static u32 mux_table_gen_clk[]	= { 0, 4, 5, 6, 7, 8,
2521 				    9, 10, 11, 13, 14, };
2522 static const struct clk_parent_data gen_clk_parent_data[] = {
2523 	{ .fw_name = "xtal", },
2524 	{ .hw = &gxbb_vdec_1.hw },
2525 	{ .hw = &gxbb_vdec_hevc.hw },
2526 	{ .hw = &gxbb_mpll0.hw },
2527 	{ .hw = &gxbb_mpll1.hw },
2528 	{ .hw = &gxbb_mpll2.hw },
2529 	{ .hw = &gxbb_fclk_div4.hw },
2530 	{ .hw = &gxbb_fclk_div3.hw },
2531 	{ .hw = &gxbb_fclk_div5.hw },
2532 	{ .hw = &gxbb_fclk_div7.hw },
2533 	{ .hw = &gxbb_gp0_pll.hw },
2534 };
2535 
2536 static struct clk_regmap gxbb_gen_clk_sel = {
2537 	.data = &(struct clk_regmap_mux_data){
2538 		.offset = HHI_GEN_CLK_CNTL,
2539 		.mask = 0xf,
2540 		.shift = 12,
2541 		.table = mux_table_gen_clk,
2542 	},
2543 	.hw.init = &(struct clk_init_data){
2544 		.name = "gen_clk_sel",
2545 		.ops = &clk_regmap_mux_ops,
2546 		/*
2547 		 * bits 15:12 selects from 14 possible parents:
2548 		 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2549 		 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2550 		 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2551 		 */
2552 		.parent_data = gen_clk_parent_data,
2553 		.num_parents = ARRAY_SIZE(gen_clk_parent_data),
2554 	},
2555 };
2556 
2557 static struct clk_regmap gxbb_gen_clk_div = {
2558 	.data = &(struct clk_regmap_div_data){
2559 		.offset = HHI_GEN_CLK_CNTL,
2560 		.shift = 0,
2561 		.width = 11,
2562 	},
2563 	.hw.init = &(struct clk_init_data){
2564 		.name = "gen_clk_div",
2565 		.ops = &clk_regmap_divider_ops,
2566 		.parent_hws = (const struct clk_hw *[]) {
2567 			&gxbb_gen_clk_sel.hw
2568 		},
2569 		.num_parents = 1,
2570 		.flags = CLK_SET_RATE_PARENT,
2571 	},
2572 };
2573 
2574 static struct clk_regmap gxbb_gen_clk = {
2575 	.data = &(struct clk_regmap_gate_data){
2576 		.offset = HHI_GEN_CLK_CNTL,
2577 		.bit_idx = 7,
2578 	},
2579 	.hw.init = &(struct clk_init_data){
2580 		.name = "gen_clk",
2581 		.ops = &clk_regmap_gate_ops,
2582 		.parent_hws = (const struct clk_hw *[]) {
2583 			&gxbb_gen_clk_div.hw
2584 		},
2585 		.num_parents = 1,
2586 		.flags = CLK_SET_RATE_PARENT,
2587 	},
2588 };
2589 
2590 #define MESON_GATE(_name, _reg, _bit) \
2591 	MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2592 
2593 /* Everything Else (EE) domain gates */
2594 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2595 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2596 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2597 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2598 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2599 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2600 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2601 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2602 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2603 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2604 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2605 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2606 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2607 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2608 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2609 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2610 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2611 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2612 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2613 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2614 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2615 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2616 
2617 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2618 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2619 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2620 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
2621 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
2622 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
2623 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
2624 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
2625 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
2626 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
2627 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
2628 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2629 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2630 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2631 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2632 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2633 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2634 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2635 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2636 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2637 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2638 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2639 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2640 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2641 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2642 
2643 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2644 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2645 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2646 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2647 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2648 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2649 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2650 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2651 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2652 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2653 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2654 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2655 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2656 
2657 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2658 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2659 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2660 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2661 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2662 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2663 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2664 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2665 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2666 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2667 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2668 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2669 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2670 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2671 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2672 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2673 
2674 /* Always On (AO) domain gates */
2675 
2676 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2677 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2678 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2679 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2680 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2681 
2682 /* Array of all clocks provided by this provider */
2683 
2684 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
2685 	.hws = {
2686 		[CLKID_SYS_PLL]		    = &gxbb_sys_pll.hw,
2687 		[CLKID_HDMI_PLL]	    = &gxbb_hdmi_pll.hw,
2688 		[CLKID_FIXED_PLL]	    = &gxbb_fixed_pll.hw,
2689 		[CLKID_FCLK_DIV2]	    = &gxbb_fclk_div2.hw,
2690 		[CLKID_FCLK_DIV3]	    = &gxbb_fclk_div3.hw,
2691 		[CLKID_FCLK_DIV4]	    = &gxbb_fclk_div4.hw,
2692 		[CLKID_FCLK_DIV5]	    = &gxbb_fclk_div5.hw,
2693 		[CLKID_FCLK_DIV7]	    = &gxbb_fclk_div7.hw,
2694 		[CLKID_GP0_PLL]		    = &gxbb_gp0_pll.hw,
2695 		[CLKID_MPEG_SEL]	    = &gxbb_mpeg_clk_sel.hw,
2696 		[CLKID_MPEG_DIV]	    = &gxbb_mpeg_clk_div.hw,
2697 		[CLKID_CLK81]		    = &gxbb_clk81.hw,
2698 		[CLKID_MPLL0]		    = &gxbb_mpll0.hw,
2699 		[CLKID_MPLL1]		    = &gxbb_mpll1.hw,
2700 		[CLKID_MPLL2]		    = &gxbb_mpll2.hw,
2701 		[CLKID_DDR]		    = &gxbb_ddr.hw,
2702 		[CLKID_DOS]		    = &gxbb_dos.hw,
2703 		[CLKID_ISA]		    = &gxbb_isa.hw,
2704 		[CLKID_PL301]		    = &gxbb_pl301.hw,
2705 		[CLKID_PERIPHS]		    = &gxbb_periphs.hw,
2706 		[CLKID_SPICC]		    = &gxbb_spicc.hw,
2707 		[CLKID_I2C]		    = &gxbb_i2c.hw,
2708 		[CLKID_SAR_ADC]		    = &gxbb_sar_adc.hw,
2709 		[CLKID_SMART_CARD]	    = &gxbb_smart_card.hw,
2710 		[CLKID_RNG0]		    = &gxbb_rng0.hw,
2711 		[CLKID_UART0]		    = &gxbb_uart0.hw,
2712 		[CLKID_SDHC]		    = &gxbb_sdhc.hw,
2713 		[CLKID_STREAM]		    = &gxbb_stream.hw,
2714 		[CLKID_ASYNC_FIFO]	    = &gxbb_async_fifo.hw,
2715 		[CLKID_SDIO]		    = &gxbb_sdio.hw,
2716 		[CLKID_ABUF]		    = &gxbb_abuf.hw,
2717 		[CLKID_HIU_IFACE]	    = &gxbb_hiu_iface.hw,
2718 		[CLKID_ASSIST_MISC]	    = &gxbb_assist_misc.hw,
2719 		[CLKID_SPI]		    = &gxbb_spi.hw,
2720 		[CLKID_I2S_SPDIF]	    = &gxbb_i2s_spdif.hw,
2721 		[CLKID_ETH]		    = &gxbb_eth.hw,
2722 		[CLKID_DEMUX]		    = &gxbb_demux.hw,
2723 		[CLKID_AIU_GLUE]	    = &gxbb_aiu_glue.hw,
2724 		[CLKID_IEC958]		    = &gxbb_iec958.hw,
2725 		[CLKID_I2S_OUT]		    = &gxbb_i2s_out.hw,
2726 		[CLKID_AMCLK]		    = &gxbb_amclk.hw,
2727 		[CLKID_AIFIFO2]		    = &gxbb_aififo2.hw,
2728 		[CLKID_MIXER]		    = &gxbb_mixer.hw,
2729 		[CLKID_MIXER_IFACE]	    = &gxbb_mixer_iface.hw,
2730 		[CLKID_ADC]		    = &gxbb_adc.hw,
2731 		[CLKID_BLKMV]		    = &gxbb_blkmv.hw,
2732 		[CLKID_AIU]		    = &gxbb_aiu.hw,
2733 		[CLKID_UART1]		    = &gxbb_uart1.hw,
2734 		[CLKID_G2D]		    = &gxbb_g2d.hw,
2735 		[CLKID_USB0]		    = &gxbb_usb0.hw,
2736 		[CLKID_USB1]		    = &gxbb_usb1.hw,
2737 		[CLKID_RESET]		    = &gxbb_reset.hw,
2738 		[CLKID_NAND]		    = &gxbb_nand.hw,
2739 		[CLKID_DOS_PARSER]	    = &gxbb_dos_parser.hw,
2740 		[CLKID_USB]		    = &gxbb_usb.hw,
2741 		[CLKID_VDIN1]		    = &gxbb_vdin1.hw,
2742 		[CLKID_AHB_ARB0]	    = &gxbb_ahb_arb0.hw,
2743 		[CLKID_EFUSE]		    = &gxbb_efuse.hw,
2744 		[CLKID_BOOT_ROM]	    = &gxbb_boot_rom.hw,
2745 		[CLKID_AHB_DATA_BUS]	    = &gxbb_ahb_data_bus.hw,
2746 		[CLKID_AHB_CTRL_BUS]	    = &gxbb_ahb_ctrl_bus.hw,
2747 		[CLKID_HDMI_INTR_SYNC]	    = &gxbb_hdmi_intr_sync.hw,
2748 		[CLKID_HDMI_PCLK]	    = &gxbb_hdmi_pclk.hw,
2749 		[CLKID_USB1_DDR_BRIDGE]	    = &gxbb_usb1_ddr_bridge.hw,
2750 		[CLKID_USB0_DDR_BRIDGE]	    = &gxbb_usb0_ddr_bridge.hw,
2751 		[CLKID_MMC_PCLK]	    = &gxbb_mmc_pclk.hw,
2752 		[CLKID_DVIN]		    = &gxbb_dvin.hw,
2753 		[CLKID_UART2]		    = &gxbb_uart2.hw,
2754 		[CLKID_SANA]		    = &gxbb_sana.hw,
2755 		[CLKID_VPU_INTR]	    = &gxbb_vpu_intr.hw,
2756 		[CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2757 		[CLKID_CLK81_A53]	    = &gxbb_clk81_a53.hw,
2758 		[CLKID_VCLK2_VENCI0]	    = &gxbb_vclk2_venci0.hw,
2759 		[CLKID_VCLK2_VENCI1]	    = &gxbb_vclk2_venci1.hw,
2760 		[CLKID_VCLK2_VENCP0]	    = &gxbb_vclk2_vencp0.hw,
2761 		[CLKID_VCLK2_VENCP1]	    = &gxbb_vclk2_vencp1.hw,
2762 		[CLKID_GCLK_VENCI_INT0]	    = &gxbb_gclk_venci_int0.hw,
2763 		[CLKID_GCLK_VENCI_INT]	    = &gxbb_gclk_vencp_int.hw,
2764 		[CLKID_DAC_CLK]		    = &gxbb_dac_clk.hw,
2765 		[CLKID_AOCLK_GATE]	    = &gxbb_aoclk_gate.hw,
2766 		[CLKID_IEC958_GATE]	    = &gxbb_iec958_gate.hw,
2767 		[CLKID_ENC480P]		    = &gxbb_enc480p.hw,
2768 		[CLKID_RNG1]		    = &gxbb_rng1.hw,
2769 		[CLKID_GCLK_VENCI_INT1]	    = &gxbb_gclk_venci_int1.hw,
2770 		[CLKID_VCLK2_VENCLMCC]	    = &gxbb_vclk2_venclmcc.hw,
2771 		[CLKID_VCLK2_VENCL]	    = &gxbb_vclk2_vencl.hw,
2772 		[CLKID_VCLK_OTHER]	    = &gxbb_vclk_other.hw,
2773 		[CLKID_EDP]		    = &gxbb_edp.hw,
2774 		[CLKID_AO_MEDIA_CPU]	    = &gxbb_ao_media_cpu.hw,
2775 		[CLKID_AO_AHB_SRAM]	    = &gxbb_ao_ahb_sram.hw,
2776 		[CLKID_AO_AHB_BUS]	    = &gxbb_ao_ahb_bus.hw,
2777 		[CLKID_AO_IFACE]	    = &gxbb_ao_iface.hw,
2778 		[CLKID_AO_I2C]		    = &gxbb_ao_i2c.hw,
2779 		[CLKID_SD_EMMC_A]	    = &gxbb_emmc_a.hw,
2780 		[CLKID_SD_EMMC_B]	    = &gxbb_emmc_b.hw,
2781 		[CLKID_SD_EMMC_C]	    = &gxbb_emmc_c.hw,
2782 		[CLKID_SAR_ADC_CLK]	    = &gxbb_sar_adc_clk.hw,
2783 		[CLKID_SAR_ADC_SEL]	    = &gxbb_sar_adc_clk_sel.hw,
2784 		[CLKID_SAR_ADC_DIV]	    = &gxbb_sar_adc_clk_div.hw,
2785 		[CLKID_MALI_0_SEL]	    = &gxbb_mali_0_sel.hw,
2786 		[CLKID_MALI_0_DIV]	    = &gxbb_mali_0_div.hw,
2787 		[CLKID_MALI_0]		    = &gxbb_mali_0.hw,
2788 		[CLKID_MALI_1_SEL]	    = &gxbb_mali_1_sel.hw,
2789 		[CLKID_MALI_1_DIV]	    = &gxbb_mali_1_div.hw,
2790 		[CLKID_MALI_1]		    = &gxbb_mali_1.hw,
2791 		[CLKID_MALI]		    = &gxbb_mali.hw,
2792 		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
2793 		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
2794 		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
2795 		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
2796 		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2797 		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2798 		[CLKID_CTS_I958]	    = &gxbb_cts_i958.hw,
2799 		[CLKID_32K_CLK]		    = &gxbb_32k_clk.hw,
2800 		[CLKID_32K_CLK_SEL]	    = &gxbb_32k_clk_sel.hw,
2801 		[CLKID_32K_CLK_DIV]	    = &gxbb_32k_clk_div.hw,
2802 		[CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2803 		[CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2804 		[CLKID_SD_EMMC_A_CLK0]	    = &gxbb_sd_emmc_a_clk0.hw,
2805 		[CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2806 		[CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2807 		[CLKID_SD_EMMC_B_CLK0]	    = &gxbb_sd_emmc_b_clk0.hw,
2808 		[CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2809 		[CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2810 		[CLKID_SD_EMMC_C_CLK0]	    = &gxbb_sd_emmc_c_clk0.hw,
2811 		[CLKID_VPU_0_SEL]	    = &gxbb_vpu_0_sel.hw,
2812 		[CLKID_VPU_0_DIV]	    = &gxbb_vpu_0_div.hw,
2813 		[CLKID_VPU_0]		    = &gxbb_vpu_0.hw,
2814 		[CLKID_VPU_1_SEL]	    = &gxbb_vpu_1_sel.hw,
2815 		[CLKID_VPU_1_DIV]	    = &gxbb_vpu_1_div.hw,
2816 		[CLKID_VPU_1]		    = &gxbb_vpu_1.hw,
2817 		[CLKID_VPU]		    = &gxbb_vpu.hw,
2818 		[CLKID_VAPB_0_SEL]	    = &gxbb_vapb_0_sel.hw,
2819 		[CLKID_VAPB_0_DIV]	    = &gxbb_vapb_0_div.hw,
2820 		[CLKID_VAPB_0]		    = &gxbb_vapb_0.hw,
2821 		[CLKID_VAPB_1_SEL]	    = &gxbb_vapb_1_sel.hw,
2822 		[CLKID_VAPB_1_DIV]	    = &gxbb_vapb_1_div.hw,
2823 		[CLKID_VAPB_1]		    = &gxbb_vapb_1.hw,
2824 		[CLKID_VAPB_SEL]	    = &gxbb_vapb_sel.hw,
2825 		[CLKID_VAPB]		    = &gxbb_vapb.hw,
2826 		[CLKID_HDMI_PLL_PRE_MULT]   = &gxbb_hdmi_pll_pre_mult.hw,
2827 		[CLKID_MPLL0_DIV]	    = &gxbb_mpll0_div.hw,
2828 		[CLKID_MPLL1_DIV]	    = &gxbb_mpll1_div.hw,
2829 		[CLKID_MPLL2_DIV]	    = &gxbb_mpll2_div.hw,
2830 		[CLKID_MPLL_PREDIV]	    = &gxbb_mpll_prediv.hw,
2831 		[CLKID_FCLK_DIV2_DIV]	    = &gxbb_fclk_div2_div.hw,
2832 		[CLKID_FCLK_DIV3_DIV]	    = &gxbb_fclk_div3_div.hw,
2833 		[CLKID_FCLK_DIV4_DIV]	    = &gxbb_fclk_div4_div.hw,
2834 		[CLKID_FCLK_DIV5_DIV]	    = &gxbb_fclk_div5_div.hw,
2835 		[CLKID_FCLK_DIV7_DIV]	    = &gxbb_fclk_div7_div.hw,
2836 		[CLKID_VDEC_1_SEL]	    = &gxbb_vdec_1_sel.hw,
2837 		[CLKID_VDEC_1_DIV]	    = &gxbb_vdec_1_div.hw,
2838 		[CLKID_VDEC_1]		    = &gxbb_vdec_1.hw,
2839 		[CLKID_VDEC_HEVC_SEL]	    = &gxbb_vdec_hevc_sel.hw,
2840 		[CLKID_VDEC_HEVC_DIV]	    = &gxbb_vdec_hevc_div.hw,
2841 		[CLKID_VDEC_HEVC]	    = &gxbb_vdec_hevc.hw,
2842 		[CLKID_GEN_CLK_SEL]	    = &gxbb_gen_clk_sel.hw,
2843 		[CLKID_GEN_CLK_DIV]	    = &gxbb_gen_clk_div.hw,
2844 		[CLKID_GEN_CLK]		    = &gxbb_gen_clk.hw,
2845 		[CLKID_FIXED_PLL_DCO]	    = &gxbb_fixed_pll_dco.hw,
2846 		[CLKID_HDMI_PLL_DCO]	    = &gxbb_hdmi_pll_dco.hw,
2847 		[CLKID_HDMI_PLL_OD]	    = &gxbb_hdmi_pll_od.hw,
2848 		[CLKID_HDMI_PLL_OD2]	    = &gxbb_hdmi_pll_od2.hw,
2849 		[CLKID_SYS_PLL_DCO]	    = &gxbb_sys_pll_dco.hw,
2850 		[CLKID_GP0_PLL_DCO]	    = &gxbb_gp0_pll_dco.hw,
2851 		[CLKID_VID_PLL_DIV]	    = &gxbb_vid_pll_div.hw,
2852 		[CLKID_VID_PLL_SEL]	    = &gxbb_vid_pll_sel.hw,
2853 		[CLKID_VID_PLL]		    = &gxbb_vid_pll.hw,
2854 		[CLKID_VCLK_SEL]	    = &gxbb_vclk_sel.hw,
2855 		[CLKID_VCLK2_SEL]	    = &gxbb_vclk2_sel.hw,
2856 		[CLKID_VCLK_INPUT]	    = &gxbb_vclk_input.hw,
2857 		[CLKID_VCLK2_INPUT]	    = &gxbb_vclk2_input.hw,
2858 		[CLKID_VCLK_DIV]	    = &gxbb_vclk_div.hw,
2859 		[CLKID_VCLK2_DIV]	    = &gxbb_vclk2_div.hw,
2860 		[CLKID_VCLK]		    = &gxbb_vclk.hw,
2861 		[CLKID_VCLK2]		    = &gxbb_vclk2.hw,
2862 		[CLKID_VCLK_DIV1]	    = &gxbb_vclk_div1.hw,
2863 		[CLKID_VCLK_DIV2_EN]	    = &gxbb_vclk_div2_en.hw,
2864 		[CLKID_VCLK_DIV2]	    = &gxbb_vclk_div2.hw,
2865 		[CLKID_VCLK_DIV4_EN]	    = &gxbb_vclk_div4_en.hw,
2866 		[CLKID_VCLK_DIV4]	    = &gxbb_vclk_div4.hw,
2867 		[CLKID_VCLK_DIV6_EN]	    = &gxbb_vclk_div6_en.hw,
2868 		[CLKID_VCLK_DIV6]	    = &gxbb_vclk_div6.hw,
2869 		[CLKID_VCLK_DIV12_EN]	    = &gxbb_vclk_div12_en.hw,
2870 		[CLKID_VCLK_DIV12]	    = &gxbb_vclk_div12.hw,
2871 		[CLKID_VCLK2_DIV1]	    = &gxbb_vclk2_div1.hw,
2872 		[CLKID_VCLK2_DIV2_EN]	    = &gxbb_vclk2_div2_en.hw,
2873 		[CLKID_VCLK2_DIV2]	    = &gxbb_vclk2_div2.hw,
2874 		[CLKID_VCLK2_DIV4_EN]	    = &gxbb_vclk2_div4_en.hw,
2875 		[CLKID_VCLK2_DIV4]	    = &gxbb_vclk2_div4.hw,
2876 		[CLKID_VCLK2_DIV6_EN]	    = &gxbb_vclk2_div6_en.hw,
2877 		[CLKID_VCLK2_DIV6]	    = &gxbb_vclk2_div6.hw,
2878 		[CLKID_VCLK2_DIV12_EN]	    = &gxbb_vclk2_div12_en.hw,
2879 		[CLKID_VCLK2_DIV12]	    = &gxbb_vclk2_div12.hw,
2880 		[CLKID_CTS_ENCI_SEL]	    = &gxbb_cts_enci_sel.hw,
2881 		[CLKID_CTS_ENCP_SEL]	    = &gxbb_cts_encp_sel.hw,
2882 		[CLKID_CTS_VDAC_SEL]	    = &gxbb_cts_vdac_sel.hw,
2883 		[CLKID_HDMI_TX_SEL]	    = &gxbb_hdmi_tx_sel.hw,
2884 		[CLKID_CTS_ENCI]	    = &gxbb_cts_enci.hw,
2885 		[CLKID_CTS_ENCP]	    = &gxbb_cts_encp.hw,
2886 		[CLKID_CTS_VDAC]	    = &gxbb_cts_vdac.hw,
2887 		[CLKID_HDMI_TX]		    = &gxbb_hdmi_tx.hw,
2888 		[CLKID_HDMI_SEL]	    = &gxbb_hdmi_sel.hw,
2889 		[CLKID_HDMI_DIV]	    = &gxbb_hdmi_div.hw,
2890 		[CLKID_HDMI]		    = &gxbb_hdmi.hw,
2891 		[NR_CLKS]		    = NULL,
2892 	},
2893 	.num = NR_CLKS,
2894 };
2895 
2896 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2897 	.hws = {
2898 		[CLKID_SYS_PLL]		    = &gxbb_sys_pll.hw,
2899 		[CLKID_HDMI_PLL]	    = &gxl_hdmi_pll.hw,
2900 		[CLKID_FIXED_PLL]	    = &gxbb_fixed_pll.hw,
2901 		[CLKID_FCLK_DIV2]	    = &gxbb_fclk_div2.hw,
2902 		[CLKID_FCLK_DIV3]	    = &gxbb_fclk_div3.hw,
2903 		[CLKID_FCLK_DIV4]	    = &gxbb_fclk_div4.hw,
2904 		[CLKID_FCLK_DIV5]	    = &gxbb_fclk_div5.hw,
2905 		[CLKID_FCLK_DIV7]	    = &gxbb_fclk_div7.hw,
2906 		[CLKID_GP0_PLL]		    = &gxbb_gp0_pll.hw,
2907 		[CLKID_MPEG_SEL]	    = &gxbb_mpeg_clk_sel.hw,
2908 		[CLKID_MPEG_DIV]	    = &gxbb_mpeg_clk_div.hw,
2909 		[CLKID_CLK81]		    = &gxbb_clk81.hw,
2910 		[CLKID_MPLL0]		    = &gxbb_mpll0.hw,
2911 		[CLKID_MPLL1]		    = &gxbb_mpll1.hw,
2912 		[CLKID_MPLL2]		    = &gxbb_mpll2.hw,
2913 		[CLKID_DDR]		    = &gxbb_ddr.hw,
2914 		[CLKID_DOS]		    = &gxbb_dos.hw,
2915 		[CLKID_ISA]		    = &gxbb_isa.hw,
2916 		[CLKID_PL301]		    = &gxbb_pl301.hw,
2917 		[CLKID_PERIPHS]		    = &gxbb_periphs.hw,
2918 		[CLKID_SPICC]		    = &gxbb_spicc.hw,
2919 		[CLKID_I2C]		    = &gxbb_i2c.hw,
2920 		[CLKID_SAR_ADC]		    = &gxbb_sar_adc.hw,
2921 		[CLKID_SMART_CARD]	    = &gxbb_smart_card.hw,
2922 		[CLKID_RNG0]		    = &gxbb_rng0.hw,
2923 		[CLKID_UART0]		    = &gxbb_uart0.hw,
2924 		[CLKID_SDHC]		    = &gxbb_sdhc.hw,
2925 		[CLKID_STREAM]		    = &gxbb_stream.hw,
2926 		[CLKID_ASYNC_FIFO]	    = &gxbb_async_fifo.hw,
2927 		[CLKID_SDIO]		    = &gxbb_sdio.hw,
2928 		[CLKID_ABUF]		    = &gxbb_abuf.hw,
2929 		[CLKID_HIU_IFACE]	    = &gxbb_hiu_iface.hw,
2930 		[CLKID_ASSIST_MISC]	    = &gxbb_assist_misc.hw,
2931 		[CLKID_SPI]		    = &gxbb_spi.hw,
2932 		[CLKID_I2S_SPDIF]	    = &gxbb_i2s_spdif.hw,
2933 		[CLKID_ETH]		    = &gxbb_eth.hw,
2934 		[CLKID_DEMUX]		    = &gxbb_demux.hw,
2935 		[CLKID_AIU_GLUE]	    = &gxbb_aiu_glue.hw,
2936 		[CLKID_IEC958]		    = &gxbb_iec958.hw,
2937 		[CLKID_I2S_OUT]		    = &gxbb_i2s_out.hw,
2938 		[CLKID_AMCLK]		    = &gxbb_amclk.hw,
2939 		[CLKID_AIFIFO2]		    = &gxbb_aififo2.hw,
2940 		[CLKID_MIXER]		    = &gxbb_mixer.hw,
2941 		[CLKID_MIXER_IFACE]	    = &gxbb_mixer_iface.hw,
2942 		[CLKID_ADC]		    = &gxbb_adc.hw,
2943 		[CLKID_BLKMV]		    = &gxbb_blkmv.hw,
2944 		[CLKID_AIU]		    = &gxbb_aiu.hw,
2945 		[CLKID_UART1]		    = &gxbb_uart1.hw,
2946 		[CLKID_G2D]		    = &gxbb_g2d.hw,
2947 		[CLKID_USB0]		    = &gxbb_usb0.hw,
2948 		[CLKID_USB1]		    = &gxbb_usb1.hw,
2949 		[CLKID_RESET]		    = &gxbb_reset.hw,
2950 		[CLKID_NAND]		    = &gxbb_nand.hw,
2951 		[CLKID_DOS_PARSER]	    = &gxbb_dos_parser.hw,
2952 		[CLKID_USB]		    = &gxbb_usb.hw,
2953 		[CLKID_VDIN1]		    = &gxbb_vdin1.hw,
2954 		[CLKID_AHB_ARB0]	    = &gxbb_ahb_arb0.hw,
2955 		[CLKID_EFUSE]		    = &gxbb_efuse.hw,
2956 		[CLKID_BOOT_ROM]	    = &gxbb_boot_rom.hw,
2957 		[CLKID_AHB_DATA_BUS]	    = &gxbb_ahb_data_bus.hw,
2958 		[CLKID_AHB_CTRL_BUS]	    = &gxbb_ahb_ctrl_bus.hw,
2959 		[CLKID_HDMI_INTR_SYNC]	    = &gxbb_hdmi_intr_sync.hw,
2960 		[CLKID_HDMI_PCLK]	    = &gxbb_hdmi_pclk.hw,
2961 		[CLKID_USB1_DDR_BRIDGE]	    = &gxbb_usb1_ddr_bridge.hw,
2962 		[CLKID_USB0_DDR_BRIDGE]	    = &gxbb_usb0_ddr_bridge.hw,
2963 		[CLKID_MMC_PCLK]	    = &gxbb_mmc_pclk.hw,
2964 		[CLKID_DVIN]		    = &gxbb_dvin.hw,
2965 		[CLKID_UART2]		    = &gxbb_uart2.hw,
2966 		[CLKID_SANA]		    = &gxbb_sana.hw,
2967 		[CLKID_VPU_INTR]	    = &gxbb_vpu_intr.hw,
2968 		[CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2969 		[CLKID_CLK81_A53]	    = &gxbb_clk81_a53.hw,
2970 		[CLKID_VCLK2_VENCI0]	    = &gxbb_vclk2_venci0.hw,
2971 		[CLKID_VCLK2_VENCI1]	    = &gxbb_vclk2_venci1.hw,
2972 		[CLKID_VCLK2_VENCP0]	    = &gxbb_vclk2_vencp0.hw,
2973 		[CLKID_VCLK2_VENCP1]	    = &gxbb_vclk2_vencp1.hw,
2974 		[CLKID_GCLK_VENCI_INT0]	    = &gxbb_gclk_venci_int0.hw,
2975 		[CLKID_GCLK_VENCI_INT]	    = &gxbb_gclk_vencp_int.hw,
2976 		[CLKID_DAC_CLK]		    = &gxbb_dac_clk.hw,
2977 		[CLKID_AOCLK_GATE]	    = &gxbb_aoclk_gate.hw,
2978 		[CLKID_IEC958_GATE]	    = &gxbb_iec958_gate.hw,
2979 		[CLKID_ENC480P]		    = &gxbb_enc480p.hw,
2980 		[CLKID_RNG1]		    = &gxbb_rng1.hw,
2981 		[CLKID_GCLK_VENCI_INT1]	    = &gxbb_gclk_venci_int1.hw,
2982 		[CLKID_VCLK2_VENCLMCC]	    = &gxbb_vclk2_venclmcc.hw,
2983 		[CLKID_VCLK2_VENCL]	    = &gxbb_vclk2_vencl.hw,
2984 		[CLKID_VCLK_OTHER]	    = &gxbb_vclk_other.hw,
2985 		[CLKID_EDP]		    = &gxbb_edp.hw,
2986 		[CLKID_AO_MEDIA_CPU]	    = &gxbb_ao_media_cpu.hw,
2987 		[CLKID_AO_AHB_SRAM]	    = &gxbb_ao_ahb_sram.hw,
2988 		[CLKID_AO_AHB_BUS]	    = &gxbb_ao_ahb_bus.hw,
2989 		[CLKID_AO_IFACE]	    = &gxbb_ao_iface.hw,
2990 		[CLKID_AO_I2C]		    = &gxbb_ao_i2c.hw,
2991 		[CLKID_SD_EMMC_A]	    = &gxbb_emmc_a.hw,
2992 		[CLKID_SD_EMMC_B]	    = &gxbb_emmc_b.hw,
2993 		[CLKID_SD_EMMC_C]	    = &gxbb_emmc_c.hw,
2994 		[CLKID_SAR_ADC_CLK]	    = &gxbb_sar_adc_clk.hw,
2995 		[CLKID_SAR_ADC_SEL]	    = &gxbb_sar_adc_clk_sel.hw,
2996 		[CLKID_SAR_ADC_DIV]	    = &gxbb_sar_adc_clk_div.hw,
2997 		[CLKID_MALI_0_SEL]	    = &gxbb_mali_0_sel.hw,
2998 		[CLKID_MALI_0_DIV]	    = &gxbb_mali_0_div.hw,
2999 		[CLKID_MALI_0]		    = &gxbb_mali_0.hw,
3000 		[CLKID_MALI_1_SEL]	    = &gxbb_mali_1_sel.hw,
3001 		[CLKID_MALI_1_DIV]	    = &gxbb_mali_1_div.hw,
3002 		[CLKID_MALI_1]		    = &gxbb_mali_1.hw,
3003 		[CLKID_MALI]		    = &gxbb_mali.hw,
3004 		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
3005 		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
3006 		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
3007 		[CLKID_CTS_MCLK_I958]	    = &gxbb_cts_mclk_i958.hw,
3008 		[CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
3009 		[CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
3010 		[CLKID_CTS_I958]	    = &gxbb_cts_i958.hw,
3011 		[CLKID_32K_CLK]		    = &gxbb_32k_clk.hw,
3012 		[CLKID_32K_CLK_SEL]	    = &gxbb_32k_clk_sel.hw,
3013 		[CLKID_32K_CLK_DIV]	    = &gxbb_32k_clk_div.hw,
3014 		[CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
3015 		[CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
3016 		[CLKID_SD_EMMC_A_CLK0]	    = &gxbb_sd_emmc_a_clk0.hw,
3017 		[CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
3018 		[CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
3019 		[CLKID_SD_EMMC_B_CLK0]	    = &gxbb_sd_emmc_b_clk0.hw,
3020 		[CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
3021 		[CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
3022 		[CLKID_SD_EMMC_C_CLK0]	    = &gxbb_sd_emmc_c_clk0.hw,
3023 		[CLKID_VPU_0_SEL]	    = &gxbb_vpu_0_sel.hw,
3024 		[CLKID_VPU_0_DIV]	    = &gxbb_vpu_0_div.hw,
3025 		[CLKID_VPU_0]		    = &gxbb_vpu_0.hw,
3026 		[CLKID_VPU_1_SEL]	    = &gxbb_vpu_1_sel.hw,
3027 		[CLKID_VPU_1_DIV]	    = &gxbb_vpu_1_div.hw,
3028 		[CLKID_VPU_1]		    = &gxbb_vpu_1.hw,
3029 		[CLKID_VPU]		    = &gxbb_vpu.hw,
3030 		[CLKID_VAPB_0_SEL]	    = &gxbb_vapb_0_sel.hw,
3031 		[CLKID_VAPB_0_DIV]	    = &gxbb_vapb_0_div.hw,
3032 		[CLKID_VAPB_0]		    = &gxbb_vapb_0.hw,
3033 		[CLKID_VAPB_1_SEL]	    = &gxbb_vapb_1_sel.hw,
3034 		[CLKID_VAPB_1_DIV]	    = &gxbb_vapb_1_div.hw,
3035 		[CLKID_VAPB_1]		    = &gxbb_vapb_1.hw,
3036 		[CLKID_VAPB_SEL]	    = &gxbb_vapb_sel.hw,
3037 		[CLKID_VAPB]		    = &gxbb_vapb.hw,
3038 		[CLKID_MPLL0_DIV]	    = &gxbb_mpll0_div.hw,
3039 		[CLKID_MPLL1_DIV]	    = &gxbb_mpll1_div.hw,
3040 		[CLKID_MPLL2_DIV]	    = &gxbb_mpll2_div.hw,
3041 		[CLKID_MPLL_PREDIV]	    = &gxbb_mpll_prediv.hw,
3042 		[CLKID_FCLK_DIV2_DIV]	    = &gxbb_fclk_div2_div.hw,
3043 		[CLKID_FCLK_DIV3_DIV]	    = &gxbb_fclk_div3_div.hw,
3044 		[CLKID_FCLK_DIV4_DIV]	    = &gxbb_fclk_div4_div.hw,
3045 		[CLKID_FCLK_DIV5_DIV]	    = &gxbb_fclk_div5_div.hw,
3046 		[CLKID_FCLK_DIV7_DIV]	    = &gxbb_fclk_div7_div.hw,
3047 		[CLKID_VDEC_1_SEL]	    = &gxbb_vdec_1_sel.hw,
3048 		[CLKID_VDEC_1_DIV]	    = &gxbb_vdec_1_div.hw,
3049 		[CLKID_VDEC_1]		    = &gxbb_vdec_1.hw,
3050 		[CLKID_VDEC_HEVC_SEL]	    = &gxbb_vdec_hevc_sel.hw,
3051 		[CLKID_VDEC_HEVC_DIV]	    = &gxbb_vdec_hevc_div.hw,
3052 		[CLKID_VDEC_HEVC]	    = &gxbb_vdec_hevc.hw,
3053 		[CLKID_GEN_CLK_SEL]	    = &gxbb_gen_clk_sel.hw,
3054 		[CLKID_GEN_CLK_DIV]	    = &gxbb_gen_clk_div.hw,
3055 		[CLKID_GEN_CLK]		    = &gxbb_gen_clk.hw,
3056 		[CLKID_FIXED_PLL_DCO]	    = &gxbb_fixed_pll_dco.hw,
3057 		[CLKID_HDMI_PLL_DCO]	    = &gxl_hdmi_pll_dco.hw,
3058 		[CLKID_HDMI_PLL_OD]	    = &gxl_hdmi_pll_od.hw,
3059 		[CLKID_HDMI_PLL_OD2]	    = &gxl_hdmi_pll_od2.hw,
3060 		[CLKID_SYS_PLL_DCO]	    = &gxbb_sys_pll_dco.hw,
3061 		[CLKID_GP0_PLL_DCO]	    = &gxl_gp0_pll_dco.hw,
3062 		[CLKID_VID_PLL_DIV]	    = &gxbb_vid_pll_div.hw,
3063 		[CLKID_VID_PLL_SEL]	    = &gxbb_vid_pll_sel.hw,
3064 		[CLKID_VID_PLL]		    = &gxbb_vid_pll.hw,
3065 		[CLKID_VCLK_SEL]	    = &gxbb_vclk_sel.hw,
3066 		[CLKID_VCLK2_SEL]	    = &gxbb_vclk2_sel.hw,
3067 		[CLKID_VCLK_INPUT]	    = &gxbb_vclk_input.hw,
3068 		[CLKID_VCLK2_INPUT]	    = &gxbb_vclk2_input.hw,
3069 		[CLKID_VCLK_DIV]	    = &gxbb_vclk_div.hw,
3070 		[CLKID_VCLK2_DIV]	    = &gxbb_vclk2_div.hw,
3071 		[CLKID_VCLK]		    = &gxbb_vclk.hw,
3072 		[CLKID_VCLK2]		    = &gxbb_vclk2.hw,
3073 		[CLKID_VCLK_DIV1]	    = &gxbb_vclk_div1.hw,
3074 		[CLKID_VCLK_DIV2_EN]	    = &gxbb_vclk_div2_en.hw,
3075 		[CLKID_VCLK_DIV2]	    = &gxbb_vclk_div2.hw,
3076 		[CLKID_VCLK_DIV4_EN]	    = &gxbb_vclk_div4_en.hw,
3077 		[CLKID_VCLK_DIV4]	    = &gxbb_vclk_div4.hw,
3078 		[CLKID_VCLK_DIV6_EN]	    = &gxbb_vclk_div6_en.hw,
3079 		[CLKID_VCLK_DIV6]	    = &gxbb_vclk_div6.hw,
3080 		[CLKID_VCLK_DIV12_EN]	    = &gxbb_vclk_div12_en.hw,
3081 		[CLKID_VCLK_DIV12]	    = &gxbb_vclk_div12.hw,
3082 		[CLKID_VCLK2_DIV1]	    = &gxbb_vclk2_div1.hw,
3083 		[CLKID_VCLK2_DIV2_EN]	    = &gxbb_vclk2_div2_en.hw,
3084 		[CLKID_VCLK2_DIV2]	    = &gxbb_vclk2_div2.hw,
3085 		[CLKID_VCLK2_DIV4_EN]	    = &gxbb_vclk2_div4_en.hw,
3086 		[CLKID_VCLK2_DIV4]	    = &gxbb_vclk2_div4.hw,
3087 		[CLKID_VCLK2_DIV6_EN]	    = &gxbb_vclk2_div6_en.hw,
3088 		[CLKID_VCLK2_DIV6]	    = &gxbb_vclk2_div6.hw,
3089 		[CLKID_VCLK2_DIV12_EN]	    = &gxbb_vclk2_div12_en.hw,
3090 		[CLKID_VCLK2_DIV12]	    = &gxbb_vclk2_div12.hw,
3091 		[CLKID_CTS_ENCI_SEL]	    = &gxbb_cts_enci_sel.hw,
3092 		[CLKID_CTS_ENCP_SEL]	    = &gxbb_cts_encp_sel.hw,
3093 		[CLKID_CTS_VDAC_SEL]	    = &gxbb_cts_vdac_sel.hw,
3094 		[CLKID_HDMI_TX_SEL]	    = &gxbb_hdmi_tx_sel.hw,
3095 		[CLKID_CTS_ENCI]	    = &gxbb_cts_enci.hw,
3096 		[CLKID_CTS_ENCP]	    = &gxbb_cts_encp.hw,
3097 		[CLKID_CTS_VDAC]	    = &gxbb_cts_vdac.hw,
3098 		[CLKID_HDMI_TX]		    = &gxbb_hdmi_tx.hw,
3099 		[CLKID_HDMI_SEL]	    = &gxbb_hdmi_sel.hw,
3100 		[CLKID_HDMI_DIV]	    = &gxbb_hdmi_div.hw,
3101 		[CLKID_HDMI]		    = &gxbb_hdmi.hw,
3102 		[NR_CLKS]		    = NULL,
3103 	},
3104 	.num = NR_CLKS,
3105 };
3106 
3107 static struct clk_regmap *const gxbb_clk_regmaps[] = {
3108 	&gxbb_clk81,
3109 	&gxbb_ddr,
3110 	&gxbb_dos,
3111 	&gxbb_isa,
3112 	&gxbb_pl301,
3113 	&gxbb_periphs,
3114 	&gxbb_spicc,
3115 	&gxbb_i2c,
3116 	&gxbb_sar_adc,
3117 	&gxbb_smart_card,
3118 	&gxbb_rng0,
3119 	&gxbb_uart0,
3120 	&gxbb_sdhc,
3121 	&gxbb_stream,
3122 	&gxbb_async_fifo,
3123 	&gxbb_sdio,
3124 	&gxbb_abuf,
3125 	&gxbb_hiu_iface,
3126 	&gxbb_assist_misc,
3127 	&gxbb_spi,
3128 	&gxbb_i2s_spdif,
3129 	&gxbb_eth,
3130 	&gxbb_demux,
3131 	&gxbb_aiu_glue,
3132 	&gxbb_iec958,
3133 	&gxbb_i2s_out,
3134 	&gxbb_amclk,
3135 	&gxbb_aififo2,
3136 	&gxbb_mixer,
3137 	&gxbb_mixer_iface,
3138 	&gxbb_adc,
3139 	&gxbb_blkmv,
3140 	&gxbb_aiu,
3141 	&gxbb_uart1,
3142 	&gxbb_g2d,
3143 	&gxbb_usb0,
3144 	&gxbb_usb1,
3145 	&gxbb_reset,
3146 	&gxbb_nand,
3147 	&gxbb_dos_parser,
3148 	&gxbb_usb,
3149 	&gxbb_vdin1,
3150 	&gxbb_ahb_arb0,
3151 	&gxbb_efuse,
3152 	&gxbb_boot_rom,
3153 	&gxbb_ahb_data_bus,
3154 	&gxbb_ahb_ctrl_bus,
3155 	&gxbb_hdmi_intr_sync,
3156 	&gxbb_hdmi_pclk,
3157 	&gxbb_usb1_ddr_bridge,
3158 	&gxbb_usb0_ddr_bridge,
3159 	&gxbb_mmc_pclk,
3160 	&gxbb_dvin,
3161 	&gxbb_uart2,
3162 	&gxbb_sana,
3163 	&gxbb_vpu_intr,
3164 	&gxbb_sec_ahb_ahb3_bridge,
3165 	&gxbb_clk81_a53,
3166 	&gxbb_vclk2_venci0,
3167 	&gxbb_vclk2_venci1,
3168 	&gxbb_vclk2_vencp0,
3169 	&gxbb_vclk2_vencp1,
3170 	&gxbb_gclk_venci_int0,
3171 	&gxbb_gclk_vencp_int,
3172 	&gxbb_dac_clk,
3173 	&gxbb_aoclk_gate,
3174 	&gxbb_iec958_gate,
3175 	&gxbb_enc480p,
3176 	&gxbb_rng1,
3177 	&gxbb_gclk_venci_int1,
3178 	&gxbb_vclk2_venclmcc,
3179 	&gxbb_vclk2_vencl,
3180 	&gxbb_vclk_other,
3181 	&gxbb_edp,
3182 	&gxbb_ao_media_cpu,
3183 	&gxbb_ao_ahb_sram,
3184 	&gxbb_ao_ahb_bus,
3185 	&gxbb_ao_iface,
3186 	&gxbb_ao_i2c,
3187 	&gxbb_emmc_a,
3188 	&gxbb_emmc_b,
3189 	&gxbb_emmc_c,
3190 	&gxbb_sar_adc_clk,
3191 	&gxbb_mali_0,
3192 	&gxbb_mali_1,
3193 	&gxbb_cts_amclk,
3194 	&gxbb_cts_mclk_i958,
3195 	&gxbb_32k_clk,
3196 	&gxbb_sd_emmc_a_clk0,
3197 	&gxbb_sd_emmc_b_clk0,
3198 	&gxbb_sd_emmc_c_clk0,
3199 	&gxbb_vpu_0,
3200 	&gxbb_vpu_1,
3201 	&gxbb_vapb_0,
3202 	&gxbb_vapb_1,
3203 	&gxbb_vapb,
3204 	&gxbb_mpeg_clk_div,
3205 	&gxbb_sar_adc_clk_div,
3206 	&gxbb_mali_0_div,
3207 	&gxbb_mali_1_div,
3208 	&gxbb_cts_mclk_i958_div,
3209 	&gxbb_32k_clk_div,
3210 	&gxbb_sd_emmc_a_clk0_div,
3211 	&gxbb_sd_emmc_b_clk0_div,
3212 	&gxbb_sd_emmc_c_clk0_div,
3213 	&gxbb_vpu_0_div,
3214 	&gxbb_vpu_1_div,
3215 	&gxbb_vapb_0_div,
3216 	&gxbb_vapb_1_div,
3217 	&gxbb_mpeg_clk_sel,
3218 	&gxbb_sar_adc_clk_sel,
3219 	&gxbb_mali_0_sel,
3220 	&gxbb_mali_1_sel,
3221 	&gxbb_mali,
3222 	&gxbb_cts_amclk_sel,
3223 	&gxbb_cts_mclk_i958_sel,
3224 	&gxbb_cts_i958,
3225 	&gxbb_32k_clk_sel,
3226 	&gxbb_sd_emmc_a_clk0_sel,
3227 	&gxbb_sd_emmc_b_clk0_sel,
3228 	&gxbb_sd_emmc_c_clk0_sel,
3229 	&gxbb_vpu_0_sel,
3230 	&gxbb_vpu_1_sel,
3231 	&gxbb_vpu,
3232 	&gxbb_vapb_0_sel,
3233 	&gxbb_vapb_1_sel,
3234 	&gxbb_vapb_sel,
3235 	&gxbb_mpll0,
3236 	&gxbb_mpll1,
3237 	&gxbb_mpll2,
3238 	&gxbb_mpll0_div,
3239 	&gxbb_mpll1_div,
3240 	&gxbb_mpll2_div,
3241 	&gxbb_cts_amclk_div,
3242 	&gxbb_fixed_pll,
3243 	&gxbb_sys_pll,
3244 	&gxbb_mpll_prediv,
3245 	&gxbb_fclk_div2,
3246 	&gxbb_fclk_div3,
3247 	&gxbb_fclk_div4,
3248 	&gxbb_fclk_div5,
3249 	&gxbb_fclk_div7,
3250 	&gxbb_vdec_1_sel,
3251 	&gxbb_vdec_1_div,
3252 	&gxbb_vdec_1,
3253 	&gxbb_vdec_hevc_sel,
3254 	&gxbb_vdec_hevc_div,
3255 	&gxbb_vdec_hevc,
3256 	&gxbb_gen_clk_sel,
3257 	&gxbb_gen_clk_div,
3258 	&gxbb_gen_clk,
3259 	&gxbb_fixed_pll_dco,
3260 	&gxbb_sys_pll_dco,
3261 	&gxbb_gp0_pll,
3262 	&gxbb_vid_pll,
3263 	&gxbb_vid_pll_sel,
3264 	&gxbb_vid_pll_div,
3265 	&gxbb_vclk,
3266 	&gxbb_vclk_sel,
3267 	&gxbb_vclk_div,
3268 	&gxbb_vclk_input,
3269 	&gxbb_vclk_div1,
3270 	&gxbb_vclk_div2_en,
3271 	&gxbb_vclk_div4_en,
3272 	&gxbb_vclk_div6_en,
3273 	&gxbb_vclk_div12_en,
3274 	&gxbb_vclk2,
3275 	&gxbb_vclk2_sel,
3276 	&gxbb_vclk2_div,
3277 	&gxbb_vclk2_input,
3278 	&gxbb_vclk2_div1,
3279 	&gxbb_vclk2_div2_en,
3280 	&gxbb_vclk2_div4_en,
3281 	&gxbb_vclk2_div6_en,
3282 	&gxbb_vclk2_div12_en,
3283 	&gxbb_cts_enci,
3284 	&gxbb_cts_enci_sel,
3285 	&gxbb_cts_encp,
3286 	&gxbb_cts_encp_sel,
3287 	&gxbb_cts_vdac,
3288 	&gxbb_cts_vdac_sel,
3289 	&gxbb_hdmi_tx,
3290 	&gxbb_hdmi_tx_sel,
3291 	&gxbb_hdmi_sel,
3292 	&gxbb_hdmi_div,
3293 	&gxbb_hdmi,
3294 	&gxbb_gp0_pll_dco,
3295 	&gxbb_hdmi_pll,
3296 	&gxbb_hdmi_pll_od,
3297 	&gxbb_hdmi_pll_od2,
3298 	&gxbb_hdmi_pll_dco,
3299 };
3300 
3301 static struct clk_regmap *const gxl_clk_regmaps[] = {
3302 	&gxbb_clk81,
3303 	&gxbb_ddr,
3304 	&gxbb_dos,
3305 	&gxbb_isa,
3306 	&gxbb_pl301,
3307 	&gxbb_periphs,
3308 	&gxbb_spicc,
3309 	&gxbb_i2c,
3310 	&gxbb_sar_adc,
3311 	&gxbb_smart_card,
3312 	&gxbb_rng0,
3313 	&gxbb_uart0,
3314 	&gxbb_sdhc,
3315 	&gxbb_stream,
3316 	&gxbb_async_fifo,
3317 	&gxbb_sdio,
3318 	&gxbb_abuf,
3319 	&gxbb_hiu_iface,
3320 	&gxbb_assist_misc,
3321 	&gxbb_spi,
3322 	&gxbb_i2s_spdif,
3323 	&gxbb_eth,
3324 	&gxbb_demux,
3325 	&gxbb_aiu_glue,
3326 	&gxbb_iec958,
3327 	&gxbb_i2s_out,
3328 	&gxbb_amclk,
3329 	&gxbb_aififo2,
3330 	&gxbb_mixer,
3331 	&gxbb_mixer_iface,
3332 	&gxbb_adc,
3333 	&gxbb_blkmv,
3334 	&gxbb_aiu,
3335 	&gxbb_uart1,
3336 	&gxbb_g2d,
3337 	&gxbb_usb0,
3338 	&gxbb_usb1,
3339 	&gxbb_reset,
3340 	&gxbb_nand,
3341 	&gxbb_dos_parser,
3342 	&gxbb_usb,
3343 	&gxbb_vdin1,
3344 	&gxbb_ahb_arb0,
3345 	&gxbb_efuse,
3346 	&gxbb_boot_rom,
3347 	&gxbb_ahb_data_bus,
3348 	&gxbb_ahb_ctrl_bus,
3349 	&gxbb_hdmi_intr_sync,
3350 	&gxbb_hdmi_pclk,
3351 	&gxbb_usb1_ddr_bridge,
3352 	&gxbb_usb0_ddr_bridge,
3353 	&gxbb_mmc_pclk,
3354 	&gxbb_dvin,
3355 	&gxbb_uart2,
3356 	&gxbb_sana,
3357 	&gxbb_vpu_intr,
3358 	&gxbb_sec_ahb_ahb3_bridge,
3359 	&gxbb_clk81_a53,
3360 	&gxbb_vclk2_venci0,
3361 	&gxbb_vclk2_venci1,
3362 	&gxbb_vclk2_vencp0,
3363 	&gxbb_vclk2_vencp1,
3364 	&gxbb_gclk_venci_int0,
3365 	&gxbb_gclk_vencp_int,
3366 	&gxbb_dac_clk,
3367 	&gxbb_aoclk_gate,
3368 	&gxbb_iec958_gate,
3369 	&gxbb_enc480p,
3370 	&gxbb_rng1,
3371 	&gxbb_gclk_venci_int1,
3372 	&gxbb_vclk2_venclmcc,
3373 	&gxbb_vclk2_vencl,
3374 	&gxbb_vclk_other,
3375 	&gxbb_edp,
3376 	&gxbb_ao_media_cpu,
3377 	&gxbb_ao_ahb_sram,
3378 	&gxbb_ao_ahb_bus,
3379 	&gxbb_ao_iface,
3380 	&gxbb_ao_i2c,
3381 	&gxbb_emmc_a,
3382 	&gxbb_emmc_b,
3383 	&gxbb_emmc_c,
3384 	&gxbb_sar_adc_clk,
3385 	&gxbb_mali_0,
3386 	&gxbb_mali_1,
3387 	&gxbb_cts_amclk,
3388 	&gxbb_cts_mclk_i958,
3389 	&gxbb_32k_clk,
3390 	&gxbb_sd_emmc_a_clk0,
3391 	&gxbb_sd_emmc_b_clk0,
3392 	&gxbb_sd_emmc_c_clk0,
3393 	&gxbb_vpu_0,
3394 	&gxbb_vpu_1,
3395 	&gxbb_vapb_0,
3396 	&gxbb_vapb_1,
3397 	&gxbb_vapb,
3398 	&gxbb_mpeg_clk_div,
3399 	&gxbb_sar_adc_clk_div,
3400 	&gxbb_mali_0_div,
3401 	&gxbb_mali_1_div,
3402 	&gxbb_cts_mclk_i958_div,
3403 	&gxbb_32k_clk_div,
3404 	&gxbb_sd_emmc_a_clk0_div,
3405 	&gxbb_sd_emmc_b_clk0_div,
3406 	&gxbb_sd_emmc_c_clk0_div,
3407 	&gxbb_vpu_0_div,
3408 	&gxbb_vpu_1_div,
3409 	&gxbb_vapb_0_div,
3410 	&gxbb_vapb_1_div,
3411 	&gxbb_mpeg_clk_sel,
3412 	&gxbb_sar_adc_clk_sel,
3413 	&gxbb_mali_0_sel,
3414 	&gxbb_mali_1_sel,
3415 	&gxbb_mali,
3416 	&gxbb_cts_amclk_sel,
3417 	&gxbb_cts_mclk_i958_sel,
3418 	&gxbb_cts_i958,
3419 	&gxbb_32k_clk_sel,
3420 	&gxbb_sd_emmc_a_clk0_sel,
3421 	&gxbb_sd_emmc_b_clk0_sel,
3422 	&gxbb_sd_emmc_c_clk0_sel,
3423 	&gxbb_vpu_0_sel,
3424 	&gxbb_vpu_1_sel,
3425 	&gxbb_vpu,
3426 	&gxbb_vapb_0_sel,
3427 	&gxbb_vapb_1_sel,
3428 	&gxbb_vapb_sel,
3429 	&gxbb_mpll0,
3430 	&gxbb_mpll1,
3431 	&gxbb_mpll2,
3432 	&gxbb_mpll0_div,
3433 	&gxbb_mpll1_div,
3434 	&gxbb_mpll2_div,
3435 	&gxbb_cts_amclk_div,
3436 	&gxbb_fixed_pll,
3437 	&gxbb_sys_pll,
3438 	&gxbb_mpll_prediv,
3439 	&gxbb_fclk_div2,
3440 	&gxbb_fclk_div3,
3441 	&gxbb_fclk_div4,
3442 	&gxbb_fclk_div5,
3443 	&gxbb_fclk_div7,
3444 	&gxbb_vdec_1_sel,
3445 	&gxbb_vdec_1_div,
3446 	&gxbb_vdec_1,
3447 	&gxbb_vdec_hevc_sel,
3448 	&gxbb_vdec_hevc_div,
3449 	&gxbb_vdec_hevc,
3450 	&gxbb_gen_clk_sel,
3451 	&gxbb_gen_clk_div,
3452 	&gxbb_gen_clk,
3453 	&gxbb_fixed_pll_dco,
3454 	&gxbb_sys_pll_dco,
3455 	&gxbb_gp0_pll,
3456 	&gxbb_vid_pll,
3457 	&gxbb_vid_pll_sel,
3458 	&gxbb_vid_pll_div,
3459 	&gxbb_vclk,
3460 	&gxbb_vclk_sel,
3461 	&gxbb_vclk_div,
3462 	&gxbb_vclk_input,
3463 	&gxbb_vclk_div1,
3464 	&gxbb_vclk_div2_en,
3465 	&gxbb_vclk_div4_en,
3466 	&gxbb_vclk_div6_en,
3467 	&gxbb_vclk_div12_en,
3468 	&gxbb_vclk2,
3469 	&gxbb_vclk2_sel,
3470 	&gxbb_vclk2_div,
3471 	&gxbb_vclk2_input,
3472 	&gxbb_vclk2_div1,
3473 	&gxbb_vclk2_div2_en,
3474 	&gxbb_vclk2_div4_en,
3475 	&gxbb_vclk2_div6_en,
3476 	&gxbb_vclk2_div12_en,
3477 	&gxbb_cts_enci,
3478 	&gxbb_cts_enci_sel,
3479 	&gxbb_cts_encp,
3480 	&gxbb_cts_encp_sel,
3481 	&gxbb_cts_vdac,
3482 	&gxbb_cts_vdac_sel,
3483 	&gxbb_hdmi_tx,
3484 	&gxbb_hdmi_tx_sel,
3485 	&gxbb_hdmi_sel,
3486 	&gxbb_hdmi_div,
3487 	&gxbb_hdmi,
3488 	&gxl_gp0_pll_dco,
3489 	&gxl_hdmi_pll,
3490 	&gxl_hdmi_pll_od,
3491 	&gxl_hdmi_pll_od2,
3492 	&gxl_hdmi_pll_dco,
3493 };
3494 
3495 static const struct meson_eeclkc_data gxbb_clkc_data = {
3496 	.regmap_clks = gxbb_clk_regmaps,
3497 	.regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3498 	.hw_onecell_data = &gxbb_hw_onecell_data,
3499 };
3500 
3501 static const struct meson_eeclkc_data gxl_clkc_data = {
3502 	.regmap_clks = gxl_clk_regmaps,
3503 	.regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3504 	.hw_onecell_data = &gxl_hw_onecell_data,
3505 };
3506 
3507 static const struct of_device_id clkc_match_table[] = {
3508 	{ .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3509 	{ .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3510 	{},
3511 };
3512 
3513 static struct platform_driver gxbb_driver = {
3514 	.probe		= meson_eeclkc_probe,
3515 	.driver		= {
3516 		.name	= "gxbb-clkc",
3517 		.of_match_table = clkc_match_table,
3518 	},
3519 };
3520 
3521 builtin_platform_driver(gxbb_driver);
3522